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[96.255.20.138]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8c37f4a7962sm1489152685a.11.2026.01.12.08.36.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jan 2026 08:36:01 -0800 (PST) From: Gregory Price To: linux-cxl@vger.kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave@stgolabs.net, jonathan.cameron@huawei.com, dave.jiang@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, dan.j.williams@intel.com Subject: [PATCH 3/6] cxl/core/region: move pmem memctrl logic into memctrl/pmem_region Date: Mon, 12 Jan 2026 11:35:11 -0500 Message-ID: <20260112163514.2551809-4-gourry@gourry.net> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260112163514.2551809-1-gourry@gourry.net> References: <20260112163514.2551809-1-gourry@gourry.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the pmem_region logic from region.c into memctrl/pmem_region.c. Restrict the valid controllers for pmem to the pmem controller. Simplify the controller selection logic in region probe. Cc:=20 Signed-off-by: Gregory Price Reviewed-by: Ben Cheatham --- drivers/cxl/core/core.h | 1 + drivers/cxl/core/memctrl/Makefile | 1 + drivers/cxl/core/memctrl/memctrl.c | 2 + drivers/cxl/core/memctrl/pmem_region.c | 191 +++++++++++++++++++++ drivers/cxl/core/region.c | 221 +++---------------------- drivers/cxl/cxl.h | 2 + 6 files changed, 217 insertions(+), 201 deletions(-) create mode 100644 drivers/cxl/core/memctrl/pmem_region.c diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 18cb84950500..59175890a6ac 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -46,6 +46,7 @@ u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct = cxl_memdev *cxlmd, u64 dpa); int cxl_enable_memctrl(struct cxl_region *cxlr); int devm_cxl_add_dax_region(struct cxl_region *cxlr); +int devm_cxl_add_pmem_region(struct cxl_region *cxlr); =20 #else static inline u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, diff --git a/drivers/cxl/core/memctrl/Makefile b/drivers/cxl/core/memctrl/M= akefile index 1c52c7d75570..efffc8ba2c0b 100644 --- a/drivers/cxl/core/memctrl/Makefile +++ b/drivers/cxl/core/memctrl/Makefile @@ -3,3 +3,4 @@ cxl_core-$(CONFIG_CXL_REGION) +=3D memctrl/memctrl.o cxl_core-$(CONFIG_CXL_REGION) +=3D memctrl/dax_region.o cxl_core-$(CONFIG_CXL_REGION) +=3D memctrl/sysram_region.o +cxl_core-$(CONFIG_CXL_REGION) +=3D memctrl/pmem_region.o diff --git a/drivers/cxl/core/memctrl/memctrl.c b/drivers/cxl/core/memctrl/= memctrl.c index 40ffb59353bb..1b661465bdeb 100644 --- a/drivers/cxl/core/memctrl/memctrl.c +++ b/drivers/cxl/core/memctrl/memctrl.c @@ -36,6 +36,8 @@ int cxl_enable_memctrl(struct cxl_region *cxlr) return devm_cxl_add_dax_region(cxlr); case CXL_MEMCTRL_SYSRAM: return devm_cxl_add_sysram_region(cxlr); + case CXL_MEMCTRL_PMEM: + return devm_cxl_add_pmem_region(cxlr); default: return -EINVAL; } diff --git a/drivers/cxl/core/memctrl/pmem_region.c b/drivers/cxl/core/memc= trl/pmem_region.c new file mode 100644 index 000000000000..57668dd82d71 --- /dev/null +++ b/drivers/cxl/core/memctrl/pmem_region.c @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright(c) 2022 Intel Corporation. All rights reserved. */ +#include +#include +#include +#include +#include "../core.h" + +static void cxl_pmem_region_release(struct device *dev) +{ + struct cxl_pmem_region *cxlr_pmem =3D to_cxl_pmem_region(dev); + int i; + + for (i =3D 0; i < cxlr_pmem->nr_mappings; i++) { + struct cxl_memdev *cxlmd =3D cxlr_pmem->mapping[i].cxlmd; + + put_device(&cxlmd->dev); + } + + kfree(cxlr_pmem); +} + +static const struct attribute_group *cxl_pmem_region_attribute_groups[] = =3D { + &cxl_base_attribute_group, + NULL, +}; + +const struct device_type cxl_pmem_region_type =3D { + .name =3D "cxl_pmem_region", + .release =3D cxl_pmem_region_release, + .groups =3D cxl_pmem_region_attribute_groups, +}; +bool is_cxl_pmem_region(struct device *dev) +{ + return dev->type =3D=3D &cxl_pmem_region_type; +} +EXPORT_SYMBOL_NS_GPL(is_cxl_pmem_region, "CXL"); + +struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) +{ + if (dev_WARN_ONCE(dev, !is_cxl_pmem_region(dev), + "not a cxl_pmem_region device\n")) + return NULL; + return container_of(dev, struct cxl_pmem_region, dev); +} +EXPORT_SYMBOL_NS_GPL(to_cxl_pmem_region, "CXL"); +static struct lock_class_key cxl_pmem_region_key; + +static int cxl_pmem_region_alloc(struct cxl_region *cxlr) +{ + struct cxl_region_params *p =3D &cxlr->params; + struct cxl_nvdimm_bridge *cxl_nvb; + struct device *dev; + int i; + + guard(rwsem_read)(&cxl_rwsem.region); + if (p->state !=3D CXL_CONFIG_COMMIT) + return -ENXIO; + + struct cxl_pmem_region *cxlr_pmem __free(kfree) =3D + kzalloc(struct_size(cxlr_pmem, mapping, p->nr_targets), GFP_KERNEL); + if (!cxlr_pmem) + return -ENOMEM; + + cxlr_pmem->hpa_range.start =3D p->res->start; + cxlr_pmem->hpa_range.end =3D p->res->end; + + /* Snapshot the region configuration underneath the cxl_rwsem.region */ + cxlr_pmem->nr_mappings =3D p->nr_targets; + for (i =3D 0; i < p->nr_targets; i++) { + struct cxl_endpoint_decoder *cxled =3D p->targets[i]; + struct cxl_memdev *cxlmd =3D cxled_to_memdev(cxled); + struct cxl_pmem_region_mapping *m =3D &cxlr_pmem->mapping[i]; + + /* + * Regions never span CXL root devices, so by definition the + * bridge for one device is the same for all. + */ + if (i =3D=3D 0) { + cxl_nvb =3D cxl_find_nvdimm_bridge(cxlmd->endpoint); + if (!cxl_nvb) + return -ENODEV; + cxlr->cxl_nvb =3D cxl_nvb; + } + m->cxlmd =3D cxlmd; + get_device(&cxlmd->dev); + m->start =3D cxled->dpa_res->start; + m->size =3D resource_size(cxled->dpa_res); + m->position =3D i; + } + + dev =3D &cxlr_pmem->dev; + device_initialize(dev); + lockdep_set_class(&dev->mutex, &cxl_pmem_region_key); + device_set_pm_not_required(dev); + dev->parent =3D &cxlr->dev; + dev->bus =3D &cxl_bus_type; + dev->type =3D &cxl_pmem_region_type; + cxlr_pmem->cxlr =3D cxlr; + cxlr->cxlr_pmem =3D no_free_ptr(cxlr_pmem); + + return 0; +} + +static void cxlr_pmem_unregister(void *_cxlr_pmem) +{ + struct cxl_pmem_region *cxlr_pmem =3D _cxlr_pmem; + struct cxl_region *cxlr =3D cxlr_pmem->cxlr; + struct cxl_nvdimm_bridge *cxl_nvb =3D cxlr->cxl_nvb; + + /* + * Either the bridge is in ->remove() context under the device_lock(), + * or cxlr_release_nvdimm() is cancelling the bridge's release action + * for @cxlr_pmem and doing it itself (while manually holding the bridge + * lock). + */ + device_lock_assert(&cxl_nvb->dev); + cxlr->cxlr_pmem =3D NULL; + cxlr_pmem->cxlr =3D NULL; + device_unregister(&cxlr_pmem->dev); +} + +static void cxlr_release_nvdimm(void *_cxlr) +{ + struct cxl_region *cxlr =3D _cxlr; + struct cxl_nvdimm_bridge *cxl_nvb =3D cxlr->cxl_nvb; + + scoped_guard(device, &cxl_nvb->dev) { + if (cxlr->cxlr_pmem) + devm_release_action(&cxl_nvb->dev, cxlr_pmem_unregister, + cxlr->cxlr_pmem); + } + cxlr->cxl_nvb =3D NULL; + put_device(&cxl_nvb->dev); +} + +/** + * devm_cxl_add_pmem_region() - add a cxl_region-to-nd_region bridge + * @cxlr: parent CXL region for this pmem region bridge device + * + * Return: 0 on success negative error code on failure. + */ +int devm_cxl_add_pmem_region(struct cxl_region *cxlr) +{ + struct cxl_pmem_region *cxlr_pmem; + struct cxl_nvdimm_bridge *cxl_nvb; + struct device *dev; + int rc; + + rc =3D cxl_pmem_region_alloc(cxlr); + if (rc) + return rc; + cxlr_pmem =3D cxlr->cxlr_pmem; + cxl_nvb =3D cxlr->cxl_nvb; + + dev =3D &cxlr_pmem->dev; + rc =3D dev_set_name(dev, "pmem_region%d", cxlr->id); + if (rc) + goto err; + + rc =3D device_add(dev); + if (rc) + goto err; + + dev_dbg(&cxlr->dev, "%s: register %s\n", dev_name(dev->parent), + dev_name(dev)); + + scoped_guard(device, &cxl_nvb->dev) { + if (cxl_nvb->dev.driver) + rc =3D devm_add_action_or_reset(&cxl_nvb->dev, + cxlr_pmem_unregister, + cxlr_pmem); + else + rc =3D -ENXIO; + } + + if (rc) + goto err_bridge; + + /* @cxlr carries a reference on @cxl_nvb until cxlr_release_nvdimm */ + return devm_add_action_or_reset(&cxlr->dev, cxlr_release_nvdimm, cxlr); + +err: + put_device(dev); +err_bridge: + put_device(&cxl_nvb->dev); + cxlr->cxl_nvb =3D NULL; + return rc; +} + + diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index eeab091f043a..85c20a09246d 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -642,6 +642,9 @@ static ssize_t ctrl_show(struct device *dev, struct dev= ice_attribute *attr, case CXL_MEMCTRL_SYSRAM: desc =3D "sysram"; break; + case CXL_MEMCTRL_PMEM: + desc =3D "pmem"; + break; default: desc =3D ""; break; @@ -661,6 +664,10 @@ static ssize_t ctrl_store(struct device *dev, struct d= evice_attribute *attr, if ((rc =3D ACQUIRE_ERR(rwsem_write_kill, &rwsem))) return rc; =20 + /* PMEM only has one controller - the pmem controller */ + if (cxlr->mode =3D=3D CXL_PARTMODE_PMEM) + return -EBUSY; + if (p->state >=3D CXL_CONFIG_COMMIT) return -EBUSY; =20 @@ -2648,7 +2655,11 @@ static struct cxl_region *devm_cxl_add_region(struct= cxl_root_decoder *cxlrd, return cxlr; cxlr->mode =3D mode; cxlr->type =3D type; - cxlr->memctrl =3D CXL_MEMCTRL_NONE; + + if (mode =3D=3D CXL_PARTMODE_PMEM) + cxlr->memctrl =3D CXL_MEMCTRL_PMEM; + else + cxlr->memctrl =3D CXL_MEMCTRL_NONE; =20 dev =3D &cxlr->dev; rc =3D dev_set_name(dev, "region%d", id); @@ -2797,46 +2808,6 @@ static ssize_t delete_region_store(struct device *de= v, } DEVICE_ATTR_WO(delete_region); =20 -static void cxl_pmem_region_release(struct device *dev) -{ - struct cxl_pmem_region *cxlr_pmem =3D to_cxl_pmem_region(dev); - int i; - - for (i =3D 0; i < cxlr_pmem->nr_mappings; i++) { - struct cxl_memdev *cxlmd =3D cxlr_pmem->mapping[i].cxlmd; - - put_device(&cxlmd->dev); - } - - kfree(cxlr_pmem); -} - -static const struct attribute_group *cxl_pmem_region_attribute_groups[] = =3D { - &cxl_base_attribute_group, - NULL, -}; - -const struct device_type cxl_pmem_region_type =3D { - .name =3D "cxl_pmem_region", - .release =3D cxl_pmem_region_release, - .groups =3D cxl_pmem_region_attribute_groups, -}; - -bool is_cxl_pmem_region(struct device *dev) -{ - return dev->type =3D=3D &cxl_pmem_region_type; -} -EXPORT_SYMBOL_NS_GPL(is_cxl_pmem_region, "CXL"); - -struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) -{ - if (dev_WARN_ONCE(dev, !is_cxl_pmem_region(dev), - "not a cxl_pmem_region device\n")) - return NULL; - return container_of(dev, struct cxl_pmem_region, dev); -} -EXPORT_SYMBOL_NS_GPL(to_cxl_pmem_region, "CXL"); - struct cxl_poison_context { struct cxl_port *port; int part; @@ -3268,64 +3239,6 @@ static int region_offset_to_dpa_result(struct cxl_re= gion *cxlr, u64 offset, return -ENXIO; } =20 -static struct lock_class_key cxl_pmem_region_key; - -static int cxl_pmem_region_alloc(struct cxl_region *cxlr) -{ - struct cxl_region_params *p =3D &cxlr->params; - struct cxl_nvdimm_bridge *cxl_nvb; - struct device *dev; - int i; - - guard(rwsem_read)(&cxl_rwsem.region); - if (p->state !=3D CXL_CONFIG_COMMIT) - return -ENXIO; - - struct cxl_pmem_region *cxlr_pmem __free(kfree) =3D - kzalloc(struct_size(cxlr_pmem, mapping, p->nr_targets), GFP_KERNEL); - if (!cxlr_pmem) - return -ENOMEM; - - cxlr_pmem->hpa_range.start =3D p->res->start; - cxlr_pmem->hpa_range.end =3D p->res->end; - - /* Snapshot the region configuration underneath the cxl_rwsem.region */ - cxlr_pmem->nr_mappings =3D p->nr_targets; - for (i =3D 0; i < p->nr_targets; i++) { - struct cxl_endpoint_decoder *cxled =3D p->targets[i]; - struct cxl_memdev *cxlmd =3D cxled_to_memdev(cxled); - struct cxl_pmem_region_mapping *m =3D &cxlr_pmem->mapping[i]; - - /* - * Regions never span CXL root devices, so by definition the - * bridge for one device is the same for all. - */ - if (i =3D=3D 0) { - cxl_nvb =3D cxl_find_nvdimm_bridge(cxlmd->endpoint); - if (!cxl_nvb) - return -ENODEV; - cxlr->cxl_nvb =3D cxl_nvb; - } - m->cxlmd =3D cxlmd; - get_device(&cxlmd->dev); - m->start =3D cxled->dpa_res->start; - m->size =3D resource_size(cxled->dpa_res); - m->position =3D i; - } - - dev =3D &cxlr_pmem->dev; - device_initialize(dev); - lockdep_set_class(&dev->mutex, &cxl_pmem_region_key); - device_set_pm_not_required(dev); - dev->parent =3D &cxlr->dev; - dev->bus =3D &cxl_bus_type; - dev->type =3D &cxl_pmem_region_type; - cxlr_pmem->cxlr =3D cxlr; - cxlr->cxlr_pmem =3D no_free_ptr(cxlr_pmem); - - return 0; -} - static void cxl_dax_region_release(struct device *dev) { struct cxl_dax_region *cxlr_dax =3D to_cxl_dax_region(dev); @@ -3358,92 +3271,6 @@ struct cxl_dax_region *to_cxl_dax_region(struct devi= ce *dev) } EXPORT_SYMBOL_NS_GPL(to_cxl_dax_region, "CXL"); =20 -static void cxlr_pmem_unregister(void *_cxlr_pmem) -{ - struct cxl_pmem_region *cxlr_pmem =3D _cxlr_pmem; - struct cxl_region *cxlr =3D cxlr_pmem->cxlr; - struct cxl_nvdimm_bridge *cxl_nvb =3D cxlr->cxl_nvb; - - /* - * Either the bridge is in ->remove() context under the device_lock(), - * or cxlr_release_nvdimm() is cancelling the bridge's release action - * for @cxlr_pmem and doing it itself (while manually holding the bridge - * lock). - */ - device_lock_assert(&cxl_nvb->dev); - cxlr->cxlr_pmem =3D NULL; - cxlr_pmem->cxlr =3D NULL; - device_unregister(&cxlr_pmem->dev); -} - -static void cxlr_release_nvdimm(void *_cxlr) -{ - struct cxl_region *cxlr =3D _cxlr; - struct cxl_nvdimm_bridge *cxl_nvb =3D cxlr->cxl_nvb; - - scoped_guard(device, &cxl_nvb->dev) { - if (cxlr->cxlr_pmem) - devm_release_action(&cxl_nvb->dev, cxlr_pmem_unregister, - cxlr->cxlr_pmem); - } - cxlr->cxl_nvb =3D NULL; - put_device(&cxl_nvb->dev); -} - -/** - * devm_cxl_add_pmem_region() - add a cxl_region-to-nd_region bridge - * @cxlr: parent CXL region for this pmem region bridge device - * - * Return: 0 on success negative error code on failure. - */ -static int devm_cxl_add_pmem_region(struct cxl_region *cxlr) -{ - struct cxl_pmem_region *cxlr_pmem; - struct cxl_nvdimm_bridge *cxl_nvb; - struct device *dev; - int rc; - - rc =3D cxl_pmem_region_alloc(cxlr); - if (rc) - return rc; - cxlr_pmem =3D cxlr->cxlr_pmem; - cxl_nvb =3D cxlr->cxl_nvb; - - dev =3D &cxlr_pmem->dev; - rc =3D dev_set_name(dev, "pmem_region%d", cxlr->id); - if (rc) - goto err; - - rc =3D device_add(dev); - if (rc) - goto err; - - dev_dbg(&cxlr->dev, "%s: register %s\n", dev_name(dev->parent), - dev_name(dev)); - - scoped_guard(device, &cxl_nvb->dev) { - if (cxl_nvb->dev.driver) - rc =3D devm_add_action_or_reset(&cxl_nvb->dev, - cxlr_pmem_unregister, - cxlr_pmem); - else - rc =3D -ENXIO; - } - - if (rc) - goto err_bridge; - - /* @cxlr carries a reference on @cxl_nvb until cxlr_release_nvdimm */ - return devm_add_action_or_reset(&cxlr->dev, cxlr_release_nvdimm, cxlr); - -err: - put_device(dev); -err_bridge: - put_device(&cxl_nvb->dev); - cxlr->cxl_nvb =3D NULL; - return rc; -} - static int match_decoder_by_range(struct device *dev, const void *data) { const struct range *r1, *r2 =3D data; @@ -3929,26 +3756,18 @@ static int cxl_region_probe(struct device *dev) return rc; } =20 - switch (cxlr->mode) { - case CXL_PARTMODE_PMEM: - rc =3D devm_cxl_region_edac_register(cxlr); - if (rc) - dev_dbg(&cxlr->dev, "CXL EDAC registration for region_id=3D%d failed\n", - cxlr->id); - - return devm_cxl_add_pmem_region(cxlr); - case CXL_PARTMODE_RAM: - rc =3D devm_cxl_region_edac_register(cxlr); - if (rc) - dev_dbg(&cxlr->dev, "CXL EDAC registration for region_id=3D%d failed\n", - cxlr->id); - - return cxl_enable_memctrl(cxlr); - default: + if (cxlr->mode > CXL_PARTMODE_PMEM) { dev_dbg(&cxlr->dev, "unsupported region mode: %d\n", cxlr->mode); return -ENXIO; } + + rc =3D devm_cxl_region_edac_register(cxlr); + if (rc) + dev_dbg(&cxlr->dev, "CXL EDAC registration for region_id=3D%d failed\n", + cxlr->id); + + return cxl_enable_memctrl(cxlr); } =20 static struct cxl_driver cxl_region_driver =3D { diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index bb4f877b4e8f..c69d27a2e97d 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -509,12 +509,14 @@ enum cxl_partition_mode { * Auto - either BIOS-configured as SysRAM, or default to DAX * DAX - creates a dax_region controller for the cxl_region * SYSRAM - hotplugs the region directly as System RAM + * PMEM - persistent memory controller (nvdimm) */ enum cxl_memctrl_mode { CXL_MEMCTRL_NONE, CXL_MEMCTRL_AUTO, CXL_MEMCTRL_DAX, CXL_MEMCTRL_SYSRAM, + CXL_MEMCTRL_PMEM, }; =20 /* --=20 2.52.0