From nobody Sun Feb 8 02:21:48 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1D2D29D28A for ; Mon, 12 Jan 2026 10:14:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768212871; cv=none; b=DGJHkAU8jfzXSXfHdUGJyMeM+z5Raac/Zvih5zL7HC/uo6VTaucQneQOiSHyetvvKRIuOOje66d5PA9tUOIHhhvvnQZuIJ4cRxvPWnPskhSvKn0F2nyBe98L6/iZI766bmTtkcAjNuZJsADW5PSh/HQU/pW0m7o+uETM3vMMy70= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768212871; c=relaxed/simple; bh=sU5K5hcXTa4o6eQuCTfla84bPf+52jnqSx3MVZTwGMo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MbRB8V5jvl1sgK5gjbUPu40KYC+LmmH+577aFNts6j7jpwDxrHVj+IyS9YMisXxXQFbVvbgkdsb27AXJ/06Mc8kdgUlgTEv57FhJBVJ43Q6IiIRewvRJCtFTXVsk+9yJyyat3ZMesSipKASSvncnr2cgFBNM/9iJ0wsYxS32Rbk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=LvVLyLnD; arc=none smtp.client-ip=170.10.129.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="LvVLyLnD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1768212866; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rFurCOq7m06qYdTncSUSeHZ26rBTB4/HSXWqKkQxEiM=; b=LvVLyLnDUYmHfFqLETd888sd9GMgtl/ZaiadlPl00idTVA+CrCeCn9LbakgRh2iNjaqaca vkuGcLGcblm/pAsYKCBCzc4iacaMCcogOxhVwGrzmHV4xTciLGXEygKAaL774/MuYibtC6 z8Zlk58ENT9hIs1ptJrpIcxgOmjkQ/Q= Received: from mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-665-7wUBYKvvNyScNtYTSq3CoQ-1; Mon, 12 Jan 2026 05:14:23 -0500 X-MC-Unique: 7wUBYKvvNyScNtYTSq3CoQ-1 X-Mimecast-MFC-AGG-ID: 7wUBYKvvNyScNtYTSq3CoQ_1768212861 Received: from mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id DC0BE1800359; Mon, 12 Jan 2026 10:14:20 +0000 (UTC) Received: from p16v.bos2.lab (unknown [10.44.32.158]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 4B81A18004D8; Mon, 12 Jan 2026 10:14:16 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Donald Hunter , Jakub Kicinski , "David S. Miller" , Eric Dumazet , Paolo Abeni , Simon Horman , Vadim Fedorenko , Arkadiusz Kubalewski , Jiri Pirko , Prathosh Satish , Petr Oros , linux-kernel@vger.kernel.org, Michal Schmidt Subject: [PATCH net-next 1/3] dpll: add dpll_device op to get supported modes Date: Mon, 12 Jan 2026 11:14:07 +0100 Message-ID: <20260112101409.804206-2-ivecera@redhat.com> In-Reply-To: <20260112101409.804206-1-ivecera@redhat.com> References: <20260112101409.804206-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Content-Type: text/plain; charset="utf-8" Currently, the DPLL subsystem assumes that the only supported mode is the one currently active on the device. When dpll_msg_add_mode_supported() is called, it relies on ops->mode_get() and reports that single mode to userspace. This prevents users from discovering other modes the device might be capable of. Add a new callback .supported_modes_get() to struct dpll_device_ops. This allows drivers to populate a bitmap indicating all modes supported by the hardware. Update dpll_msg_add_mode_supported() to utilize this new callback: * if ops->supported_modes_get is defined, use it to retrieve the full bitmap of supported modes. * if not defined, fall back to the existing behavior: retrieve the current mode via ops->mode_get and set the corresponding bit in the bitmap. Finally, iterate over the bitmap and add a DPLL_A_MODE_SUPPORTED netlink attribute for every set bit, accurately reporting the device's capabilities to userspace. Signed-off-by: Ivan Vecera Reviewed-by: Vadim Fedorenko --- drivers/dpll/dpll_netlink.c | 27 +++++++++++++++++++-------- include/linux/dpll.h | 3 +++ 2 files changed, 22 insertions(+), 8 deletions(-) diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c index 64944f601ee5a..d6a0e272d7038 100644 --- a/drivers/dpll/dpll_netlink.c +++ b/drivers/dpll/dpll_netlink.c @@ -128,18 +128,29 @@ dpll_msg_add_mode_supported(struct sk_buff *msg, stru= ct dpll_device *dpll, struct netlink_ext_ack *extack) { const struct dpll_device_ops *ops =3D dpll_device_ops(dpll); + DECLARE_BITMAP(modes, DPLL_MODE_MAX + 1) =3D { 0 }; enum dpll_mode mode; int ret; =20 - /* No mode change is supported now, so the only supported mode is the - * one obtained by mode_get(). - */ + if (ops->supported_modes_get) { + ret =3D ops->supported_modes_get(dpll, dpll_priv(dpll), modes, + extack); + if (ret) + return ret; + } else { + /* If the supported modes are not reported by the driver, the + * only supported mode is the one obtained by mode_get(). + */ + ret =3D ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); + if (ret) + return ret; =20 - ret =3D ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); - if (ret) - return ret; - if (nla_put_u32(msg, DPLL_A_MODE_SUPPORTED, mode)) - return -EMSGSIZE; + __set_bit(mode, modes); + } + + for_each_set_bit(mode, modes, DPLL_MODE_MAX + 1) + if (nla_put_u32(msg, DPLL_A_MODE_SUPPORTED, mode)) + return -EMSGSIZE; =20 return 0; } diff --git a/include/linux/dpll.h b/include/linux/dpll.h index 562f520b23c27..912a2ca3e0ee7 100644 --- a/include/linux/dpll.h +++ b/include/linux/dpll.h @@ -20,6 +20,9 @@ struct dpll_pin_esync; struct dpll_device_ops { int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv, enum dpll_mode *mode, struct netlink_ext_ack *extack); + int (*supported_modes_get)(const struct dpll_device *dpll, + void *dpll_priv, unsigned long *modes, + struct netlink_ext_ack *extack); int (*lock_status_get)(const struct dpll_device *dpll, void *dpll_priv, enum dpll_lock_status *status, enum dpll_lock_status_error *status_error, --=20 2.52.0 From nobody Sun Feb 8 02:21:48 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 415FC29D287 for ; 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Mon, 12 Jan 2026 05:14:27 -0500 X-MC-Unique: WgXpljyWN6S4yoHSAUGljw-1 X-Mimecast-MFC-AGG-ID: WgXpljyWN6S4yoHSAUGljw_1768212866 Received: from mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 987141956089; Mon, 12 Jan 2026 10:14:25 +0000 (UTC) Received: from p16v.bos2.lab (unknown [10.44.32.158]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 5B350180009E; Mon, 12 Jan 2026 10:14:21 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Donald Hunter , Jakub Kicinski , "David S. Miller" , Eric Dumazet , Paolo Abeni , Simon Horman , Vadim Fedorenko , Arkadiusz Kubalewski , Jiri Pirko , Prathosh Satish , Petr Oros , linux-kernel@vger.kernel.org, Michal Schmidt Subject: [PATCH net-next 2/3] dpll: add dpll_device op to set working mode Date: Mon, 12 Jan 2026 11:14:08 +0100 Message-ID: <20260112101409.804206-3-ivecera@redhat.com> In-Reply-To: <20260112101409.804206-1-ivecera@redhat.com> References: <20260112101409.804206-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Content-Type: text/plain; charset="utf-8" Currently, userspace can retrieve the DPLL working mode but cannot configure it. This prevents changing the device operation, such as switching from manual to automatic mode and vice versa. Add a new callback .mode_set() to struct dpll_device_ops. Extend the netlink policy and device-set command handling to process the DPLL_A_MODE attribute. Update the netlink YAML specification to include the mode attribute in the device-set operation. Signed-off-by: Ivan Vecera --- Documentation/netlink/specs/dpll.yaml | 1 + drivers/dpll/dpll_netlink.c | 44 +++++++++++++++++++++++++++ drivers/dpll/dpll_nl.c | 1 + include/linux/dpll.h | 2 ++ 4 files changed, 48 insertions(+) diff --git a/Documentation/netlink/specs/dpll.yaml b/Documentation/netlink/= specs/dpll.yaml index 78d0724d7e12c..b55afa77eac4b 100644 --- a/Documentation/netlink/specs/dpll.yaml +++ b/Documentation/netlink/specs/dpll.yaml @@ -550,6 +550,7 @@ operations: request: attributes: - id + - mode - phase-offset-monitor - phase-offset-avg-factor - diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c index d6a0e272d7038..37ca90ab841bd 100644 --- a/drivers/dpll/dpll_netlink.c +++ b/drivers/dpll/dpll_netlink.c @@ -853,6 +853,45 @@ int dpll_pin_change_ntf(struct dpll_pin *pin) } EXPORT_SYMBOL_GPL(dpll_pin_change_ntf); =20 +static int +dpll_mode_set(struct dpll_device *dpll, struct nlattr *a, + struct netlink_ext_ack *extack) +{ + const struct dpll_device_ops *ops =3D dpll_device_ops(dpll); + enum dpll_mode mode =3D nla_get_u32(a), old_mode; + DECLARE_BITMAP(modes, DPLL_MODE_MAX) =3D { 0 }; + int ret; + + if (!(ops->mode_set && ops->supported_modes_get)) { + NL_SET_ERR_MSG_ATTR(extack, a, + "dpll device does not support mode switch"); + return -EOPNOTSUPP; + } + + ret =3D ops->mode_get(dpll, dpll_priv(dpll), &old_mode, extack); + if (ret) { + NL_SET_ERR_MSG(extack, "unable to get current mode"); + return ret; + } + + if (mode =3D=3D old_mode) + return 0; + + ret =3D ops->supported_modes_get(dpll, dpll_priv(dpll), modes, extack); + if (ret) { + NL_SET_ERR_MSG(extack, "unable to get supported modes"); + return ret; + } + + if (!test_bit(mode, modes)) { + NL_SET_ERR_MSG(extack, + "dpll device does not support requested mode"); + return -EINVAL; + } + + return ops->mode_set(dpll, dpll_priv(dpll), mode, extack); +} + static int dpll_phase_offset_monitor_set(struct dpll_device *dpll, struct nlattr *a, struct netlink_ext_ack *extack) @@ -1808,6 +1847,11 @@ dpll_set_from_nlattr(struct dpll_device *dpll, struc= t genl_info *info) nla_for_each_attr(a, genlmsg_data(info->genlhdr), genlmsg_len(info->genlhdr), rem) { switch (nla_type(a)) { + case DPLL_A_MODE: + ret =3D dpll_mode_set(dpll, a, info->extack); + if (ret) + return ret; + break; case DPLL_A_PHASE_OFFSET_MONITOR: ret =3D dpll_phase_offset_monitor_set(dpll, a, info->extack); diff --git a/drivers/dpll/dpll_nl.c b/drivers/dpll/dpll_nl.c index 36d11ff195df4..a2b22d4921142 100644 --- a/drivers/dpll/dpll_nl.c +++ b/drivers/dpll/dpll_nl.c @@ -45,6 +45,7 @@ static const struct nla_policy dpll_device_get_nl_policy[= DPLL_A_ID + 1] =3D { /* DPLL_CMD_DEVICE_SET - do */ static const struct nla_policy dpll_device_set_nl_policy[DPLL_A_PHASE_OFFS= ET_AVG_FACTOR + 1] =3D { [DPLL_A_ID] =3D { .type =3D NLA_U32, }, + [DPLL_A_MODE] =3D NLA_POLICY_RANGE(NLA_U32, 1, 2), [DPLL_A_PHASE_OFFSET_MONITOR] =3D NLA_POLICY_MAX(NLA_U32, 1), [DPLL_A_PHASE_OFFSET_AVG_FACTOR] =3D { .type =3D NLA_U32, }, }; diff --git a/include/linux/dpll.h b/include/linux/dpll.h index 912a2ca3e0ee7..c6d0248fa5273 100644 --- a/include/linux/dpll.h +++ b/include/linux/dpll.h @@ -20,6 +20,8 @@ struct dpll_pin_esync; struct dpll_device_ops { int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv, enum dpll_mode *mode, struct netlink_ext_ack *extack); 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Mon, 12 Jan 2026 10:14:30 +0000 (UTC) Received: from p16v.bos2.lab (unknown [10.44.32.158]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 12E4418004D8; Mon, 12 Jan 2026 10:14:25 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Donald Hunter , Jakub Kicinski , "David S. Miller" , Eric Dumazet , Paolo Abeni , Simon Horman , Vadim Fedorenko , Arkadiusz Kubalewski , Jiri Pirko , Prathosh Satish , Petr Oros , linux-kernel@vger.kernel.org, Michal Schmidt Subject: [PATCH net-next 3/3] dpll: zl3073x: Implement device mode setting support Date: Mon, 12 Jan 2026 11:14:09 +0100 Message-ID: <20260112101409.804206-4-ivecera@redhat.com> In-Reply-To: <20260112101409.804206-1-ivecera@redhat.com> References: <20260112101409.804206-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Content-Type: text/plain; charset="utf-8" Add support for .supported_modes_get() and .mode_set() callbacks to enable switching between manual and automatic modes via netlink. Implement .supported_modes_get() to report available modes based on the current hardware configuration: * manual mode is always supported * automatic mode is supported unless the dpll channel is configured in NCO (Numerically Controlled Oscillator) mode Implement .mode_set() to handle the specific logic required when transitioning between modes: 1) Transition to manual: * If a valid reference is currently active, switch the hardware to ref-lock mode (force lock to that reference). * If no reference is valid and the DPLL is unlocked, switch to freerun. * Otherwise, switch to Holdover. 2) Transition to automatic: * If the currently selected reference pin was previously marked as non-selectable (likely during a previous manual forcing operation), restore its priority and selectability in the hardware. * Switch the hardware to Automatic selection mode. Signed-off-by: Ivan Vecera --- drivers/dpll/zl3073x/dpll.c | 106 ++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/drivers/dpll/zl3073x/dpll.c b/drivers/dpll/zl3073x/dpll.c index 9879d85d29af0..d0a9c361dc1d8 100644 --- a/drivers/dpll/zl3073x/dpll.c +++ b/drivers/dpll/zl3073x/dpll.c @@ -100,6 +100,20 @@ zl3073x_dpll_pin_direction_get(const struct dpll_pin *= dpll_pin, void *pin_priv, return 0; } =20 +static struct zl3073x_dpll_pin * +zl3073x_dpll_pin_get_by_ref(struct zl3073x_dpll *zldpll, u8 ref_id) +{ + struct zl3073x_dpll_pin *pin; + + list_for_each_entry(pin, &zldpll->pins, list) { + if (zl3073x_dpll_is_input_pin(pin) && + zl3073x_input_pin_ref_get(pin->id) =3D=3D ref_id) + return pin; + } + + return NULL; +} + static int zl3073x_dpll_input_pin_esync_get(const struct dpll_pin *dpll_pin, void *pin_priv, @@ -1137,6 +1151,26 @@ zl3073x_dpll_lock_status_get(const struct dpll_devic= e *dpll, void *dpll_priv, return 0; } =20 +static int +zl3073x_dpll_supported_modes_get(const struct dpll_device *dpll, + void *dpll_priv, unsigned long *modes, + struct netlink_ext_ack *extack) +{ + struct zl3073x_dpll *zldpll =3D dpll_priv; + + /* We support switching between automatic and manual mode, except in + * a case where the DPLL channel is configured to run in NCO mode. + * In this case, report only the manual mode to which the NCO is mapped + * as the only supported one. + */ + if (zldpll->refsel_mode !=3D ZL_DPLL_MODE_REFSEL_MODE_NCO) + __set_bit(DPLL_MODE_AUTOMATIC, modes); + + __set_bit(DPLL_MODE_MANUAL, modes); + + return 0; +} + static int zl3073x_dpll_mode_get(const struct dpll_device *dpll, void *dpll_priv, enum dpll_mode *mode, struct netlink_ext_ack *extack) @@ -1217,6 +1251,76 @@ zl3073x_dpll_phase_offset_avg_factor_set(const struc= t dpll_device *dpll, return 0; } =20 +static int +zl3073x_dpll_mode_set(const struct dpll_device *dpll, void *dpll_priv, + enum dpll_mode mode, struct netlink_ext_ack *extack) +{ + struct zl3073x_dpll *zldpll =3D dpll_priv; + u8 hw_mode, mode_refsel, ref; + int rc; + + rc =3D zl3073x_dpll_selected_ref_get(zldpll, &ref); + if (rc) { + NL_SET_ERR_MSG_MOD(extack, "failed to get selected reference"); + return rc; + } + + if (mode =3D=3D DPLL_MODE_MANUAL) { + /* We are switching from automatic to manual mode: + * - if we have a valid reference selected during auto mode then + * we will switch to forced reference lock mode and use this + * reference for selection + * - if NO valid reference is selected, we will switch to forced + * holdover mode or freerun mode, depending on the current + * lock status + */ + if (ZL3073X_DPLL_REF_IS_VALID(ref)) + hw_mode =3D ZL_DPLL_MODE_REFSEL_MODE_REFLOCK; + else if (zldpll->lock_status =3D=3D DPLL_LOCK_STATUS_UNLOCKED) + hw_mode =3D ZL_DPLL_MODE_REFSEL_MODE_FREERUN; + else + hw_mode =3D ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER; + } else { + /* We are switching from manual to automatic mode: + * - if there is a valid reference selected then ensure that + * it is selectable after switch to automatic mode + * - switch to automatic mode + */ + struct zl3073x_dpll_pin *pin; + + pin =3D zl3073x_dpll_pin_get_by_ref(zldpll, ref); + if (pin && !pin->selectable) { + /* Restore pin priority in HW */ + rc =3D zl3073x_dpll_ref_prio_set(pin, pin->prio); + if (rc) + return rc; + + pin->selectable =3D true; + } + + hw_mode =3D ZL_DPLL_MODE_REFSEL_MODE_AUTO; + } + + /* Build mode_refsel value */ + mode_refsel =3D FIELD_PREP(ZL_DPLL_MODE_REFSEL_MODE, hw_mode); + + if (ZL3073X_DPLL_REF_IS_VALID(ref)) + mode_refsel |=3D FIELD_PREP(ZL_DPLL_MODE_REFSEL_REF, ref); + + /* Update dpll_mode_refsel register */ + rc =3D zl3073x_write_u8(zldpll->dev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id), + mode_refsel); + if (rc) + return rc; + + zldpll->refsel_mode =3D hw_mode; + + if (ZL3073X_DPLL_REF_IS_VALID(ref)) + zldpll->forced_ref =3D ref; + + return 0; +} + static int zl3073x_dpll_phase_offset_monitor_get(const struct dpll_device *dpll, void *dpll_priv, @@ -1276,10 +1380,12 @@ static const struct dpll_pin_ops zl3073x_dpll_outpu= t_pin_ops =3D { static const struct dpll_device_ops zl3073x_dpll_device_ops =3D { .lock_status_get =3D zl3073x_dpll_lock_status_get, .mode_get =3D zl3073x_dpll_mode_get, + .mode_set =3D zl3073x_dpll_mode_set, .phase_offset_avg_factor_get =3D zl3073x_dpll_phase_offset_avg_factor_get, .phase_offset_avg_factor_set =3D zl3073x_dpll_phase_offset_avg_factor_set, .phase_offset_monitor_get =3D zl3073x_dpll_phase_offset_monitor_get, .phase_offset_monitor_set =3D zl3073x_dpll_phase_offset_monitor_set, + .supported_modes_get =3D zl3073x_dpll_supported_modes_get, }; =20 /** --=20 2.52.0