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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jan 2026 08:52:46.6089 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 730e1591-3a1c-4645-e7ea-08de51b7f52b X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR10MB4321 Content-Type: text/plain; charset="utf-8" Each A72 core has one watchdog instance associated with it. Since j742s2 has 4 A72 cores, the common file should not define 8 watchdog instances. Refactor the last 4 extra watchdogs from the common file to j784s4 specific file, as j784s4 has 8 A72 cores and thus hardware description requires 8 watchdog instances. Fixes: 9cc161a4509c ("arm64: dts: ti: Refactor J784s4 SoC files to a common= file") Signed-off-by: Abhash Kumar Jha Reviewed-by: Udit Kumar --- .../dts/ti/k3-j784s4-j742s2-main-common.dtsi | 36 ------------------- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 36 +++++++++++++++++++ 2 files changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arc= h/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index 9cc0901d58fb..c2636e624f18 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -2378,42 +2378,6 @@ watchdog3: watchdog@2230000 { assigned-clock-parents =3D <&k3_clks 351 4>; }; =20 - watchdog4: watchdog@2240000 { - compatible =3D "ti,j7-rti-wdt"; - reg =3D <0x00 0x2240000 0x00 0x100>; - clocks =3D <&k3_clks 352 0>; - power-domains =3D <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks =3D <&k3_clks 352 0>; - assigned-clock-parents =3D <&k3_clks 352 4>; - }; - - watchdog5: watchdog@2250000 { - compatible =3D "ti,j7-rti-wdt"; - reg =3D <0x00 0x2250000 0x00 0x100>; - clocks =3D <&k3_clks 353 0>; - power-domains =3D <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks =3D <&k3_clks 353 0>; - assigned-clock-parents =3D <&k3_clks 353 4>; - }; - - watchdog6: watchdog@2260000 { - compatible =3D "ti,j7-rti-wdt"; - reg =3D <0x00 0x2260000 0x00 0x100>; - clocks =3D <&k3_clks 354 0>; - power-domains =3D <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks =3D <&k3_clks 354 0>; - assigned-clock-parents =3D <&k3_clks 354 4>; - }; - - watchdog7: watchdog@2270000 { - compatible =3D "ti,j7-rti-wdt"; - reg =3D <0x00 0x2270000 0x00 0x100>; - clocks =3D <&k3_clks 355 0>; - power-domains =3D <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks =3D <&k3_clks 355 0>; - assigned-clock-parents =3D <&k3_clks 355 4>; - }; - /* * The following RTI instances are coupled with MCU R5Fs, c7x and * GPU so keeping them reserved as these will be used by their diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index 5b7830a3c097..78fcd0c40abc 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -6,6 +6,42 @@ */ =20 &cbass_main { + watchdog4: watchdog@2240000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x2240000 0x00 0x100>; + clocks =3D <&k3_clks 352 0>; + power-domains =3D <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 352 0>; + assigned-clock-parents =3D <&k3_clks 352 4>; + }; + + watchdog5: watchdog@2250000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x2250000 0x00 0x100>; + clocks =3D <&k3_clks 353 0>; + power-domains =3D <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 353 0>; + assigned-clock-parents =3D <&k3_clks 353 4>; + }; + + watchdog6: watchdog@2260000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x2260000 0x00 0x100>; + clocks =3D <&k3_clks 354 0>; + power-domains =3D <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 354 0>; + assigned-clock-parents =3D <&k3_clks 354 4>; + }; + + watchdog7: watchdog@2270000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x2270000 0x00 0x100>; + clocks =3D <&k3_clks 355 0>; + power-domains =3D <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 355 0>; + assigned-clock-parents =3D <&k3_clks 355 4>; + }; + pcie2_rc: pcie@2920000 { compatible =3D "ti,j784s4-pcie-host"; reg =3D <0x00 0x02920000 0x00 0x1000>, --=20 2.34.1