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Sun, 11 Jan 2026 20:30:27 -0800 From: "Sheetal ." To: Mark Brown CC: Sander Vanheule , Greg Kroah-Hartman , "Rafael J . Wysocki" , Danilo Krummrich , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , "Thierry Reding" , Jonathan Hunter , Mohan kumar , , , , Sheetal Subject: [RFC PATCH v2 1/3] regmap: Add flat_cache_default_is_zero flag for flat cache Date: Mon, 12 Jan 2026 09:58:39 +0530 Message-ID: <20260112042841.51799-2-sheetal@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260112042841.51799-1-sheetal@nvidia.com> References: <20260112042841.51799-1-sheetal@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D3:EE_|LV8PR12MB9690:EE_ X-MS-Office365-Filtering-Correlation-Id: 798fc17c-1409-4b6e-f5f5-08de51935e1e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?5k4Ue3ftiubZxGU6u8/BfpM47d7lMcl1i66wWUchVfZhkmtWGkPEHTGDCNbk?= =?us-ascii?Q?3gtVj0US2ZmhpAaefuywrq7R68TSCX3lVWRGm1MNDMN4B+Og9ZQPpojGu6EF?= =?us-ascii?Q?W6xUh4nBmzliTEXKcsxXCHvfccKZbmSRqqqg639bZ+kzptiBJcTUcjHtuJb7?= =?us-ascii?Q?u7cOEmuVBM5rdw3T/X2bUTw3O0N31nQehl9DAVDlUUC6pD8EaGzpFLSTSIL8?= =?us-ascii?Q?Yn/s/gzZO8Vytep55vHU5dtgxyUyW/+0kxWOy80owVK7oV65tbxFaDyUCvF4?= =?us-ascii?Q?PFFZNfQu/aCkrMjLnUn6PN8X1EXxi0YCLdC+RK8pNZANTH/OKVhAIhhxWAp/?= =?us-ascii?Q?EYgWnL9yyiaqG1X8C1lhB/pXwb60ij0ytkjeZEvlt+jAZZKJGml3AjlS07ZC?= =?us-ascii?Q?Zz7ScwVFlm/OBZjLDMypINhCgaE63F/V1APjUpafsyFiOJPd3/ZZwzaQ4hSG?= =?us-ascii?Q?S7+3/tAIx7XNBtS8B9Xx3wB/W2vL7KdZ0YDWfZlXl9HBhltdrsBgzKBsD12q?= =?us-ascii?Q?aAtnKgVZqfGqUCj0Sy1aiXSBNpXjKfEdJT8Amc8n27CJ7/PzlClnYwVLxQyr?= =?us-ascii?Q?q2K0+1cvw1BpHqogeqR0wM0RztATyCxaVMMqOyVKKPMHirteutZ0EO3JCfgw?= =?us-ascii?Q?aRBVxkeFs/ghBfxodZTOd8V79MYqx7SG4LANuasA+kJ88RK5sWhykmb+oB+4?= =?us-ascii?Q?oD0KUP7YL7911XT6B4NYd4Na83Aw1A+MvZyOKSz58PTAi7dPxINNDXAcO8cO?= =?us-ascii?Q?U4d5CkwQW2JhmiV3Zg9C289BzBuB+sGtU07dyZ2nobBfXYx/a/z/9Ix3JmEf?= =?us-ascii?Q?cS96nbivETBKx6xquKWjYycL+QTWBG7p4+uSQmyPHUm002aRcITnblVkF/kM?= =?us-ascii?Q?tLE3/ommvrngCx0gGl3SDqMsyiJhJSybZTZEzyXlVQ3jXCvDMU/eMYqSM7J3?= =?us-ascii?Q?2WCq8s7hJ1v71mze4PJQgy7Q6m2Di7TsRw8CxTwy1g8KP8Jp4cpOLyBly+G2?= =?us-ascii?Q?/xQXaoVktazEkkzx7hGIYP2HegVPsqsxBxboPx7dlOWTQK7r/Nv+zZfBVNBE?= =?us-ascii?Q?oSXajH/M5wJ1unj6FHVtST/q5JrqUZCEOrn7NGs0VTP75pN+Zx8DdJ2xDwwk?= =?us-ascii?Q?0B0amD7PjmaJdeNMJSnHDqfa1d4PXwTfzmJr41ostGwiYC06985bA40RrnMQ?= =?us-ascii?Q?JKJq4NLG6T/96X+XRjKoLsCEKU4wiZI/yxYR+rNHTNhYIBNSndjgMwZHog6r?= =?us-ascii?Q?ApLl886KSpWSgVCtrt2d3Fa2LarZCxfdSlFdOeyKBGlGsjLqHI+jrxBHor3/?= =?us-ascii?Q?McjivHZPT8jTXYmhy4zqQkpGNWxzMxkkpRaT8RYTU/DNoNb6+vZCdqnCc4je?= =?us-ascii?Q?PUuZxS7rZ7ReAI2nz+C85cHo9+TaK41Nzt9YaxiQERdwjlZ0jPWw+cSq3325?= =?us-ascii?Q?FsRRJZRYsVyGLUQmw9ShXxKSNfgg78uaf5Jkoa9ep1VC+/AuVhKcSSeaq8xP?= =?us-ascii?Q?DBL2y3QgX7ImIvykGoYPUv3Gsq9GDeVc5rqjkOAUoynauS+f/B6llWixbt28?= =?us-ascii?Q?Lzd5eaYvZbOMnf00h9Y=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jan 2026 04:30:51.2906 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 798fc17c-1409-4b6e-f5f5-08de51935e1e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9690 Content-Type: text/plain; charset="utf-8" From: Sheetal Commit e062bdfdd6ad ("regmap: warn users about uninitialized flat cache") added a warning for drivers using REGCACHE_FLAT when reading registers not present in reg_defaults. For hardware where registers have a power-on-reset value of zero or drivers that wish to treat zero as a valid cache default, adding all such registers to reg_defaults has drawbacks: 1. Maintenance burden: Drivers must list every readable register regardless of its reset value. 2. No functional benefit: Entries like { REG, 0x0 } only set the validity bit; the flat cache value is already zero. 3. Code bloat: Large reg_defaults arrays increase driver size. Add a flat_cache_default_is_zero flag to struct regmap_config. When set, the flat cache marks registers as valid on first read instead of warning. The valid bit is set on first read rather than marking all registers valid at init time for the following reasons: - Avoids writes to register holes or unused addresses during sync. - Safer for drivers that don't have writeable_reg callback defined. Signed-off-by: Sheetal --- drivers/base/regmap/internal.h | 2 ++ drivers/base/regmap/regcache-flat.c | 12 ++++++++---- drivers/base/regmap/regcache.c | 1 + include/linux/regmap.h | 1 + 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/base/regmap/internal.h b/drivers/base/regmap/internal.h index 1477329410ec..xxxxxxxxxxxx 100644 --- a/drivers/base/regmap/internal.h +++ b/drivers/base/regmap/internal.h @@ -157,6 +157,8 @@ struct regmap { bool cache_dirty; /* if set, the HW registers are known to match map->reg_defaults */ bool no_sync_defaults; + /* if set, zero is a valid default for REGCACHE_FLAT cache type registers= not in reg_defaults */ + bool flat_cache_default_is_zero; =20 struct reg_sequence *patch; int patch_regs; diff --git a/drivers/base/regmap/regcache-flat.c b/drivers/base/regmap/regc= ache-flat.c index 53cc59c84e2f..xxxxxxxxxxxx 100644 --- a/drivers/base/regmap/regcache-flat.c +++ b/drivers/base/regmap/regcache-flat.c @@ -88,10 +88,14 @@ static int regcache_flat_read(struct regmap *map, struct regcache_flat_data *cache =3D map->cache; unsigned int index =3D regcache_flat_get_index(map, reg); =20 - /* legacy behavior: ignore validity, but warn the user */ - if (unlikely(!test_bit(index, cache->valid))) - dev_warn_once(map->dev, - "using zero-initialized flat cache, this may cause unexpected behavior"= ); + /* legacy behavior: ignore validity, but warn if zero is not a valid defa= ult */ + if (unlikely(!test_bit(index, cache->valid))) { + if (map->flat_cache_default_is_zero) + set_bit(index, cache->valid); + else + dev_warn_once(map->dev, + "using zero-initialized flat cache, this may cause unexpected be= havior"); + } =20 *value =3D cache->data[index]; =20 diff --git a/drivers/base/regmap/regcache.c b/drivers/base/regmap/regcache.c index 319c342bf5a0..xxxxxxxxxxxx 100644 --- a/drivers/base/regmap/regcache.c +++ b/drivers/base/regmap/regcache.c @@ -177,6 +177,7 @@ int regcache_init(struct regmap *map, const struct regm= ap_config *config) map->reg_defaults_raw =3D config->reg_defaults_raw; map->cache_word_size =3D BITS_TO_BYTES(config->val_bits); map->cache_size_raw =3D map->cache_word_size * config->num_reg_defaults_r= aw; + map->flat_cache_default_is_zero =3D config->flat_cache_default_is_zero; =20 map->cache =3D NULL; map->cache_ops =3D cache_types[i]; diff --git a/include/linux/regmap.h b/include/linux/regmap.h index b0b9be750d93..xxxxxxxxxxxx 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -452,6 +452,7 @@ struct regmap_config { enum regcache_type cache_type; const void *reg_defaults_raw; unsigned int num_reg_defaults_raw; + bool flat_cache_default_is_zero; =20 unsigned long read_flag_mask; unsigned long write_flag_mask; --=20 2.34.1