From nobody Tue Feb 10 00:39:42 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDA0934E75C for ; Mon, 12 Jan 2026 12:23:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768220629; cv=none; b=FAOWLiaQ0/ziyKkllrbbUOurb7NBFzrMOnM9GQorsL6KTzujkTMgtMUZRdSf+fkJJpcL3u0Meh8p0s+wguewQ2X756bEkOx2eVNFVs0eVkRHi01Sen/U+RVTuzWWemNITJupykVGd+hRdrzyBnU9LsdYCSkjp6K1P/jK/YOsXGo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768220629; c=relaxed/simple; bh=5XYh3qU0E6CACzIL6ur84P4Eb7KOe1uwmZ2EdqKXJ0k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Fz2ML8n9z8TxHXVvVPU/OTbkbXf1lCOYQUiPChcWMg99ulwTdG5JUiw1z1rFnc28gKeMaF0v7bYrJ6J40B1Z7dXMo53Yaj112jDUjvqAsjBTU9TH3Mg7jaZp1jNh/a/Ku3iHZX4lBgpD/bihZb+dfRdRApsSJzDTK5gR5clk2g4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=BwyKAzEs; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=WZRYGa1i; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="BwyKAzEs"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="WZRYGa1i" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 60C9FQLQ1093212 for ; Mon, 12 Jan 2026 12:23:47 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= dN57cYibaoaFKgsFPtXDx4dUJbZGPEN4ih36VR6HU6E=; b=BwyKAzEsEsMx5DRU pq2la7mSDXSsg1AeM9pomiuMp3VqfCQrpVkEDMSR4PloYHVjFgH3exs1PMApg0ER Hwu3K0wT4T4n1ioLtfWL2JwkvqVHhWNJjWiGS63P+cWjN2qxg2vzzDyRkCySj8W3 SO0UkAtt1xc1lRwMvY9jC+3XZXPUtObNXCCO/lija4e4+N73JAp8UpQ+ga0mS7Gx FMM6RlqT2V0gHBpwutTD/xaa41go74VZ/ADxs+pycxVxPxJs3bR/LqENFJsejxjl zBK+eU7K4wBUroVW4cQ3v+PHT6Xh26jQ4zkSCrJXMFXFPr7LGmFWnEClWMQB5gRU B8rJZg== Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bmx5mghwc-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 12 Jan 2026 12:23:46 +0000 (GMT) Received: by mail-pl1-f199.google.com with SMTP id d9443c01a7336-2a0d59f0198so69337755ad.1 for ; Mon, 12 Jan 2026 04:23:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1768220626; x=1768825426; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=dN57cYibaoaFKgsFPtXDx4dUJbZGPEN4ih36VR6HU6E=; b=WZRYGa1ivBF25k8PyR7DiyZrekN0CpZQqLIfJff2dObQGhpeAS+xUvMwqUXGNl0UWB UScc/OVk2PubVhypskNTvjB+ZQftU+SZtdGOYDYVMI0UXiOOh0hZsGVU/EnB2IdsfiE+ ff1nCDYAqb67iF43wbwPGLvpNb7y3aTdpwbxBZvUeGxj9LNbaTHPJXbYVTvCV4Sv/lJE CNF52VoTlGzGxm74rUBwr2y71jek4ShRbj8CGfYA/XIFxwVjWIhEa/WNlGDDlpeaFD5q QS4YNuxYDL/rTrijugoyBwt8T5GDQtuUcWimszkYiVs/psFgXomMpJZvIdUJGAV8rAS2 Sv2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768220626; x=1768825426; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=dN57cYibaoaFKgsFPtXDx4dUJbZGPEN4ih36VR6HU6E=; b=CEVD8nkxLGCXVkX/zTN2AtVyJXBEfyD3k2cgGWENodJhv1HR50m6nwH5idY4O16P7l TbefK+pCdRkYpNQ1z2LI5VbECmiyAQvtrhcUTkG4gOI0QRr4X4Pbvw/NR9lUlpkGwwsV wxHauMPN+YJsm8+Xv6BV3YwBfJw+A2nxVa0PCWTgScSnlwFRkaX20bW5WF4wzq75TXqk S+00VUBv9a0gATPN4VXgPw7Ddon3VUbVCKDmCRjywkJu0wAQi5WGibPr+WZewdAc75FP nlKkY8iU5X29ukmEGEt12qUOoLZugNbIVAVQmS+v+Mw/s/wfGmZJVBawUG0bA8YvvfMJ v+UA== X-Forwarded-Encrypted: i=1; AJvYcCWCeNFp7U/B4gMeeDmXblvYiB6rMpGsXGxqwvrOI5SXWpSWj0Hf9eqxmSu4DxoDBmEno6hYYI8Av+7Zw3w=@vger.kernel.org X-Gm-Message-State: AOJu0Yyr3AdUQAMKEOPvPpaF62iqWNH0sTHYvTRFCjna/Z2rGk+H+ONY nGdtIK+UW4srbzgTyXrkN44PTSbYPf4BDGVpYB49MiwezpHcJ8hPJ1j3cU30kbecRH3ov7/buDh r0Lr6saax7w1b+dKyFHP+gcLRobZvZ9GHY1dtv1qteW+BBxUGW+i0kZkaDapyRccarpE= X-Gm-Gg: AY/fxX7pCRNeo0QxEF5QMM6otcEoIEGmwL1kt79useLm6YW89O79DzRl8GkKJfdk2j8 10RrJ3SEC+l3ME22emU9PUrw+qpu6QvNQfv+6QKdzc3Dn1RiKmf1jafvtGPirnsxzh4ksJLJE9g 9JFPdZIxKR/2maDavOJ13OyxoFIDK7hp10722nvoKxny0rqZzT15Yqssq4cXD58xau6Fe3awVkH /ZPGWjfeeWvGQEju0WKYSd5RzkcXAxyIxQNeAgaz1UqYuNO31R2JvFNI6dNNPvSOJHk3901tNdC mz288lFiknQ69Tx79KU/d2bJ2njiJ6SHpMZ20h0R83w5SKh9KHXEvmBQnu3E/Thjg3Fn0Fyu1PH 1p+I7NsZQ095qAvaUz+KxWY4hZL9wtm+ZS8sa2i01QsYRXP/KmqYWc7t0eo7QhWWCTaRh6FHiDM ex8SYcpcGUmRm4T/i0AND/4tVcAArgMw== X-Received: by 2002:a17:903:2307:b0:29d:f739:ff5f with SMTP id d9443c01a7336-2a3ee4efd44mr179089115ad.61.1768220625717; Mon, 12 Jan 2026 04:23:45 -0800 (PST) X-Google-Smtp-Source: AGHT+IEj99nPNRsSZ+/Q/r2sWZI116qMlTfVmnjKyKnGFVabbAWpIpKY1k/7HnDAjWUJuIr+ZzfyyQ== X-Received: by 2002:a17:903:2307:b0:29d:f739:ff5f with SMTP id d9443c01a7336-2a3ee4efd44mr179088655ad.61.1768220625004; Mon, 12 Jan 2026 04:23:45 -0800 (PST) Received: from hu-pankpati-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a3e3c47147sm170875665ad.22.2026.01.12.04.23.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jan 2026 04:23:44 -0800 (PST) From: Pankaj Patil Date: Mon, 12 Jan 2026 17:52:37 +0530 Subject: [PATCH v4 4/4] arm64: dts: qcom: glymur: Enable Glymur CRD board support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260112-upstream_v3_glymur_introduction-v4-4-8a0366210e02@oss.qualcomm.com> References: <20260112-upstream_v3_glymur_introduction-v4-0-8a0366210e02@oss.qualcomm.com> In-Reply-To: <20260112-upstream_v3_glymur_introduction-v4-0-8a0366210e02@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pankaj Patil , Kamal Wadhwa , Qiang Yu , Sibi Sankar , Jyothi Kumar Seerapu , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768220604; l=16614; i=pankaj.patil@oss.qualcomm.com; s=20251121; h=from:subject:message-id; bh=5XYh3qU0E6CACzIL6ur84P4Eb7KOe1uwmZ2EdqKXJ0k=; b=/o+XqZ14WL53Wnrpnq73FVKlpySSb4pNqmiac/NSi0RhLwa8X22NtLQB9hn/aQsm6Zd9NmzgK /gaf0kG+YUKDt/zWfi9A2OsilbHuBVJS1O+m+3sVc8EDg5g1+O2xdIR X-Developer-Key: i=pankaj.patil@oss.qualcomm.com; a=ed25519; pk=pWpEq/tlX6TaKH1UQolvxjRD+Vdib/sEkb8bH8AL6gc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTEyMDA5OSBTYWx0ZWRfX8LQ+JWCjNLRY 3rpjZign1nAukpvuzNiieCi44Lee/BT2ix0v51VBU2KMw6RUARTjzimyCk1x2oHe2VR3iZX7TUz DwL/3Abb63ItolCfhxup9HEliIH0bnkgYB4s+wNlM3IJ7qtJoCIft9LdRL/7xzFZHp4xPpFsMYN 57gStSxQgFnGh3nB4y8Y/wCJmQ4jUhHjzispo6cntRuDvTBpnXErXm9nbDY7KQ5FZzu9pch/FYc ggWc4R5nbM+dWYsxwyXtXnNW7/6bKkgqHA/b5yGIi7RpaHMWcPighbGssirgfizzZlUkY1a2Zsy OEoAETcCoiL7yVKL7dtNw/BYz6tTtzQpDMUZLFbu+ibGKrwTBW8AjKrFVZLhn+meGRHlTlfKysP RdR7goCx4TGZV2mNjlUu0+X8JMi8TK6GGFxdKMPQjt/kwJjytRlqGRDLuNwLR6ZeW60rzT/pOCO 5MSIJC7OweDYCsO8+Ig== X-Proofpoint-ORIG-GUID: lOH-y-p-VJMt8MM7KrnPRENUSyKw8T98 X-Proofpoint-GUID: lOH-y-p-VJMt8MM7KrnPRENUSyKw8T98 X-Authority-Analysis: v=2.4 cv=Q8zfIo2a c=1 sm=1 tr=0 ts=6964e7d2 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=G2EWvzJwtjNzoYok74wA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-12_03,2026-01-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 spamscore=0 priorityscore=1501 phishscore=0 malwarescore=0 adultscore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601120099 Add initial device tree support for the Glymur Compute Reference Device(CRD) board, with this board dts glymur crd can boot to shell with rootfs on nvme and uart21 as serial console Features enabled are: - Board and sleep clocks - Volume up/down keys - Regulators 0 - 4 - Power supplies and sideband signals (PERST, WAKE, CLKREQ) for PCIe3b/4/5/6 controllers and PHYs Co-developed-by: Kamal Wadhwa Signed-off-by: Kamal Wadhwa Co-developed-by: Qiang Yu Signed-off-by: Qiang Yu Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Co-developed-by: Jyothi Kumar Seerapu Signed-off-by: Jyothi Kumar Seerapu Reviewed-by: Dmitry Baryshkov Signed-off-by: Pankaj Patil Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/glymur-crd.dts | 601 ++++++++++++++++++++++++++++= ++++ 2 files changed, 602 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 0ccd6ec16dfb..84579b86ef39 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D apq8039-t2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D apq8096-ifc6640.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D glymur-crd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D hamoa-iot-evk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5018-rdp432-c2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5018-tplink-archer-ax55-v1.dtb diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/= qcom/glymur-crd.dts new file mode 100644 index 000000000000..e9c606c413dd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -0,0 +1,601 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "glymur.dtsi" +#include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */ +#include "pmh0101.dtsi" /* SPMI0: SID-1 */ +#include "pmh0110-glymur.dtsi" /* SPMI0: SID-5/7 SPMI1: SID-5 */ +#include "pmh0104-glymur.dtsi" /* SPMI0: SID-8/9 SPMI1: SID-11 */ +#include "pmk8850.dtsi" /* SPMI0: SID-0 */ +#include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */ + +/ { + model =3D "Qualcomm Technologies, Inc. Glymur CRD"; + compatible =3D "qcom,glymur-crd", "qcom,glymur"; + + aliases { + serial0 =3D &uart21; + serial1 =3D &uart14; + i2c0 =3D &i2c0; + i2c1 =3D &i2c4; + i2c2 =3D &i2c5; + spi0 =3D &spi18; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + clock-frequency =3D <38400000>; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32000>; + #clock-cells =3D <0>; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&key_vol_up_default>; + pinctrl-names =3D "default"; + + key-volume-up { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&pmh0101_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval =3D <15>; + linux,can-disable; + wakeup-source; + }; + }; + + vreg_nvme: regulator-nvme { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_NVME_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&nvme_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_nvmesec: regulator-nvmesec { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_NVME_SEC_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pmh0110_f_e1_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&nvme_sec_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_wlan: regulator-wlan { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_WLAN_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 94 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&wlan_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_wwan: regulator-wwan { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_WWAN_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 246 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&wwan_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pmh0101-rpmh-regulators"; + qcom,pmic-id =3D "B_E0"; + + vreg_bob1_e0: bob1 { + regulator-name =3D "vreg_bob1_e0"; + regulator-min-microvolt =3D <2200000>; + regulator-max-microvolt =3D <4224000>; + regulator-initial-mode =3D ; + }; + + vreg_bob2_e0: bob2 { + regulator-name =3D "vreg_bob2_e0"; + regulator-min-microvolt =3D <2540000>; + regulator-max-microvolt =3D <3600000>; + regulator-initial-mode =3D ; + }; + + vreg_l1b_e0_1p8: ldo1 { + regulator-name =3D "vreg_l1b_e0_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l2b_e0_2p9: ldo2 { + regulator-name =3D "vreg_l2b_e0_2p9"; + regulator-min-microvolt =3D <2904000>; + regulator-max-microvolt =3D <2904000>; + regulator-initial-mode =3D ; + }; + + vreg_l7b_e0_2p79: ldo7 { + regulator-name =3D "vreg_l7b_e0_2p79"; + regulator-min-microvolt =3D <2790000>; + regulator-max-microvolt =3D <2792000>; + regulator-initial-mode =3D ; + }; + + vreg_l8b_e0_1p50: ldo8 { + regulator-name =3D "vreg_l8b_e0_1p50"; + regulator-min-microvolt =3D <1504000>; + regulator-max-microvolt =3D <1504000>; + regulator-initial-mode =3D ; + }; + + vreg_l9b_e0_2p7: ldo9 { + regulator-name =3D "vreg_l9b_e0_2p7"; + regulator-min-microvolt =3D <2704000>; + regulator-max-microvolt =3D <2704000>; + regulator-initial-mode =3D ; + }; + + vreg_l10b_e0_1p8: ldo10 { + regulator-name =3D "vreg_l10b_e0_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l11b_e0_1p2: ldo11 { + regulator-name =3D "vreg_l11b_e0_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l12b_e0_1p14: ldo12 { + regulator-name =3D "vreg_l12b_e0_1p14"; + regulator-min-microvolt =3D <1144000>; + regulator-max-microvolt =3D <1144000>; + regulator-initial-mode =3D ; + }; + + vreg_l15b_e0_1p8: ldo15 { + regulator-name =3D "vreg_l15b_e0_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l17b_e0_2p4: ldo17 { + regulator-name =3D "vreg_l17b_e0_2p4"; + regulator-min-microvolt =3D <2400000>; + regulator-max-microvolt =3D <2700000>; + regulator-initial-mode =3D ; + }; + + vreg_l18b_e0_1p2: ldo18 { + regulator-name =3D "vreg_l18b_e0_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pmcx0102-rpmh-regulators"; + qcom,pmic-id =3D "C_E1"; + + vreg_l1c_e1_0p82: ldo1 { + regulator-name =3D "vreg_l1c_e1_0p82"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l2c_e1_1p14: ldo2 { + regulator-name =3D "vreg_l2c_e1_1p14"; + regulator-min-microvolt =3D <1144000>; + regulator-max-microvolt =3D <1144000>; + regulator-initial-mode =3D ; + }; + + vreg_l3c_e1_0p89: ldo3 { + regulator-name =3D "vreg_l3c_e1_0p89"; + regulator-min-microvolt =3D <890000>; + regulator-max-microvolt =3D <980000>; + regulator-initial-mode =3D ; + }; + + vreg_l4c_e1_0p72: ldo4 { + regulator-name =3D "vreg_l4c_e1_0p72"; + regulator-min-microvolt =3D <720000>; + regulator-max-microvolt =3D <720000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "F_E0"; + + vreg_s7f_e0_1p32: smps7 { + regulator-name =3D "vreg_s7f_e0_1p32"; + regulator-min-microvolt =3D <1320000>; + regulator-max-microvolt =3D <1352000>; + regulator-initial-mode =3D ; + }; + + vreg_s8f_e0_0p95: smps8 { + regulator-name =3D "vreg_s8f_e0_0p95"; + regulator-min-microvolt =3D <952000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_s9f_e0_1p9: smps9 { + regulator-name =3D "vreg_s9f_e0_1p9"; + regulator-min-microvolt =3D <1900000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l2f_e0_0p82: ldo2 { + regulator-name =3D "vreg_l2f_e0_0p82"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l3f_e0_0p72: ldo3 { + regulator-name =3D "vreg_l3f_e0_0p72"; + regulator-min-microvolt =3D <720000>; + regulator-max-microvolt =3D <720000>; + regulator-initial-mode =3D ; + }; + + vreg_l4f_e0_0p3: ldo4 { + regulator-name =3D "vreg_l4f_e0_0p3"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-3 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "F_E1"; + + vreg_s7f_e1_0p3: smps7 { + regulator-name =3D "vreg_s7f_e1_0p3"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l1f_e1_0p82: ldo1 { + regulator-name =3D "vreg_l1f_e1_0p82"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l2f_e1_0p83: ldo2 { + regulator-name =3D "vreg_l2f_e1_0p83"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l4f_e1_1p08: ldo4 { + regulator-name =3D "vreg_l4f_e1_1p08"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1320000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-4 { + compatible =3D "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id =3D "H_E0"; + + vreg_l1h_e0_0p89: ldo1 { + regulator-name =3D "vreg_l1h_e0_0p89"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l2h_e0_0p72: ldo2 { + regulator-name =3D "vreg_l2h_e0_0p72"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <832000>; + regulator-initial-mode =3D ; + }; + + vreg_l3h_e0_0p32: ldo3 { + regulator-name =3D "vreg_l3h_e0_0p32"; + regulator-min-microvolt =3D <320000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l4h_e0_1p2: ldo4 { + regulator-name =3D "vreg_l4h_e0_1p2"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1320000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&pcie3b { + vddpe-3v3-supply =3D <&vreg_nvmesec>; + + pinctrl-0 =3D <&pcie3b_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie3b_phy { + vdda-phy-supply =3D <&vreg_l3c_e1_0p89>; + vdda-pll-supply =3D <&vreg_l2c_e1_1p14>; + + status =3D "okay"; +}; + +&pcie3b_port0 { + reset-gpios =3D <&tlmm 155 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 157 GPIO_ACTIVE_LOW>; +}; + +&pcie4 { + vddpe-3v3-supply =3D <&vreg_wlan>; + + pinctrl-0 =3D <&pcie4_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie4_phy { + vdda-phy-supply =3D <&vreg_l1c_e1_0p82>; + vdda-pll-supply =3D <&vreg_l4f_e1_1p08>; + + status =3D "okay"; +}; + +&pcie4_port0 { + reset-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + +&pcie5 { + vddpe-3v3-supply =3D <&vreg_nvme>; + + pinctrl-0 =3D <&pcie5_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie5_phy { + vdda-phy-supply =3D <&vreg_l2f_e0_0p82>; + vdda-pll-supply =3D <&vreg_l4h_e0_1p2>; + + status =3D "okay"; +}; + +&pcie5_port0 { + reset-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pcie6 { + vddpe-3v3-supply =3D <&vreg_wwan>; + + pinctrl-0 =3D <&pcie6_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie6_phy { + vdda-phy-supply =3D <&vreg_l1c_e1_0p82>; + vdda-pll-supply =3D <&vreg_l4f_e1_1p08>; + + status =3D "okay"; +}; + +&pcie6_port0 { + reset-gpios =3D <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 151 GPIO_ACTIVE_LOW>; +}; + +&pmh0101_gpios { + nvme_reg_en: nvme-reg-en-state { + pins =3D "gpio14"; + function =3D "normal"; + bias-disable; + }; +}; + +&pmh0110_f_e1_gpios { + nvme_sec_reg_en: nvme-reg-en-state { + pins =3D "gpio14"; + function =3D "normal"; + bias-disable; + }; +}; + +&pmh0101_gpios { + key_vol_up_default: key-vol-up-default-state { + pins =3D "gpio6"; + function =3D "normal"; + output-disable; + bias-pull-up; + }; +}; + +&pmk8850_rtc { + qcom,no-alarm; +}; + +&pon_resin { + linux,code =3D ; + status =3D "okay"; +}; + +&tlmm { + gpio-reserved-ranges =3D <4 4>, /* EC TZ Secure I3C */ + <10 2>, /* OOB UART */ + <44 4>; /* Security SPI (TPM) */ + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins =3D "gpio147"; + function =3D "pcie4_clk_req_n"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio146"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio148"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins =3D "gpio153"; + function =3D "pcie5_clk_req_n"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio152"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio154"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie6_default: pcie6-default-state { + clkreq-n-pins { + pins =3D "gpio150"; + function =3D "pcie6_clk_req_n"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio149"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio151"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie3b_default: pcie3b-default-state { + clkreq-n-pins { + pins =3D "gpio156"; + function =3D "pcie3b_clk"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio155"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio157"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + wlan_reg_en: wlan-reg-en-state { + pins =3D "gpio94"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wwan_reg_en: wwan-reg-en-state { + pins =3D "gpio246"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; +}; + --=20 2.34.1