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Mon, 12 Jan 2026 09:46:30 -0800 (PST) From: David Lechner Date: Mon, 12 Jan 2026 11:45:20 -0600 Subject: [PATCH v5 2/9] spi: dt-bindings: add spi-{tx,rx}-lane-map properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260112-spi-add-multi-bus-support-v5-2-295f4f09f6ba@baylibre.com> References: <20260112-spi-add-multi-bus-support-v5-0-295f4f09f6ba@baylibre.com> In-Reply-To: <20260112-spi-add-multi-bus-support-v5-0-295f4f09f6ba@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2408; i=dlechner@baylibre.com; h=from:subject:message-id; bh=tZ1gVB3H8yXnnq8oO3CvMZarToXPlUChHiU/VJKv9/w=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBpZTM+DIYL1xcg6jfE74/jpkdtlp+q7+GbQ9JbK h/EWhyK2BGJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaWUzPgAKCRDCzCAB/wGP wPlECACIbVDWCUcNaRQdTeo2VIG+zSuMX2p5ZPUyVmKqKtRzNyrrmuFHmX55JxoHewW1I9Hp4tm dPHi8bsFSkSE2SZ8JV/iVdMFvaJOzUH6rF4I17lF2OP++VTwQsb79zfu5jDyZaeZWPHpAxioHeY aLb9sOlHnqZc5pPjp6wbFAXHkeea4dHAaaPCI1+8yXi6XSxfKnL+DC5TQAPM20BzleTz/39t4+r lp0jBXCBdXBGmNPNowvuiJPo//BGMPGTQvvPRIzkbkdoQlbWKHAfc+io2BOFg5QH8cGZA1ECK50 emKQp7nga6j1SJYRlLuwnylqXhnG4srXdf/ctV9glydZf9KX X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Add spi-tx-lane-map and spi-rx-lane-map properties to the SPI peripheral device tree binding. These properties allow specifying the mapping of peripheral data lanes to controller data lanes. This is needed e.g. when some lanes are skipped on the controller side so that the controller can correctly route data to/from the peripheral. Reviewed-by: Rob Herring (Arm) Signed-off-by: David Lechner Reviewed-by: Jonathan Cameron --- v5 changes: - Use SDI/SDO terminology in descriptions. (Fixes incorrect use of TX/RX when describing the peripheral lanes.) v4 changes: - This replaces the data-lanes property from the previous revision. Now there are separate properties for tx and rx lane maps. And instead of being the primary property for determining the number of lanes, this is only needed in special cases where the mapping is non-trivial. --- .../devicetree/bindings/spi/spi-peripheral-props.yaml | 14 ++++++++++= ++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yam= l b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 59ddead7da14..880a9f624566 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -75,6 +75,13 @@ properties: enum: [0, 1, 2, 4, 8] default: [1] =20 + spi-rx-lane-map: + description: Mapping of peripheral SDO lanes to controller SDI lanes. + Each index in the array represents a peripheral SDO lane, and the va= lue + at that index represents the corresponding controller SDI lane. + $ref: /schemas/types.yaml#/definitions/uint32-array + default: [0, 1, 2, 3, 4, 5, 6, 7] + spi-rx-delay-us: description: Delay, in microseconds, after a read transfer. @@ -99,6 +106,13 @@ properties: enum: [0, 1, 2, 4, 8] default: [1] =20 + spi-tx-lane-map: + description: Mapping of peripheral SDI lanes to controller SDO lanes. + Each index in the array represents a peripheral SDI lane, and the va= lue + at that index represents the corresponding controller SDO lane. + $ref: /schemas/types.yaml#/definitions/uint32-array + default: [0, 1, 2, 3, 4, 5, 6, 7] + spi-tx-delay-us: description: Delay, in microseconds, after a write transfer. --=20 2.43.0