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Mon, 12 Jan 2026 09:46:28 -0800 (PST) From: David Lechner Date: Mon, 12 Jan 2026 11:45:19 -0600 Subject: [PATCH v5 1/9] spi: dt-bindings: change spi-{rx,tx}-bus-width to arrays Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260112-spi-add-multi-bus-support-v5-1-295f4f09f6ba@baylibre.com> References: <20260112-spi-add-multi-bus-support-v5-0-295f4f09f6ba@baylibre.com> In-Reply-To: <20260112-spi-add-multi-bus-support-v5-0-295f4f09f6ba@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner , Jonathan Cameron X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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This allows describing SPI peripherals connected to controllers that have multiple data lanes for receiving or transmitting two or more words in parallel. Each index in the array corresponds to a physical data lane (one or more wires depending on the bus width). Additional mapping properties will be needed in cases where a lane on the controller or peripheral is skipped. Bindings that make use of this property are updated in the same commit to avoid validation errors. The adi,ad4030 binding can now better describe the chips multi-lane capabilities, so that binding is refined and gets a new example. Converting from single uint32 to array of uint32 does not break .dts/ .dtb files since there is no difference between specifying a single uint32 value and an array with a single uint32 value in devicetree. Reviewed-by: Rob Herring (Arm) Reviewed-by: Marcelo Schmitt Reviewed-by: Jonathan Cameron Signed-off-by: David Lechner --- v5 changes: - Added change for andestech,ae350-spi.yaml (recently new file). v4 changes: - New patch to replace data-lanes property patch. In v3, Rob suggested possibly splitting the spi-controller.yaml file to have a way to make most SPI controllers have maxItems: 1 for these properties. I would like to avoid that because it doesn't seem scalable, e.g. if we need another similar split in the future, the number of combinations would grow exponentially (factorially?). I have an idea to instead do this using $dynamicAnchor and $dynamicRef, but dt-schema doesn't currently support that. So I propose we do the best we can for now with the current dt-schema and make further improvements later. Also, in v3, I suggested that we could have leading 0s in the arrays to indicate unused lanes. But after further consideration, I think it's better to have separate lane-mapping properties for that purpose. It will be easier to explain and parse and be a bit more flexible that way. --- .../bindings/display/panel/sitronix,st7789v.yaml | 5 +-- .../devicetree/bindings/iio/adc/adi,ad4030.yaml | 42 ++++++++++++++++++= +++- .../devicetree/bindings/iio/adc/adi,ad4695.yaml | 5 +-- .../bindings/spi/allwinner,sun4i-a10-spi.yaml | 6 ++-- .../bindings/spi/allwinner,sun6i-a31-spi.yaml | 6 ++-- .../bindings/spi/andestech,ae350-spi.yaml | 6 ++-- .../bindings/spi/nvidia,tegra210-quad.yaml | 6 ++-- .../bindings/spi/spi-peripheral-props.yaml | 26 ++++++++++---- 8 files changed, 83 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/display/panel/sitronix,st778= 9v.yaml b/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.= yaml index 0ce2ea13583d..c35d4f2ab9a4 100644 --- a/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml +++ b/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml @@ -34,8 +34,9 @@ properties: spi-cpol: true =20 spi-rx-bus-width: - minimum: 0 - maximum: 1 + items: + minimum: 0 + maximum: 1 =20 dc-gpios: maxItems: 1 diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4030.yaml index 54e7349317b7..e22d518135f2 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml @@ -37,7 +37,15 @@ properties: maximum: 102040816 =20 spi-rx-bus-width: - enum: [1, 2, 4] + maxItems: 2 + # all lanes must have the same width + oneOf: + - contains: + const: 1 + - contains: + const: 2 + - contains: + const: 4 =20 vdd-5v-supply: true vdd-1v8-supply: true @@ -88,6 +96,18 @@ oneOf: =20 unevaluatedProperties: false =20 +allOf: + - if: + properties: + compatible: + enum: + - adi,ad4030-24 + - adi,ad4032-24 + then: + properties: + spi-rx-bus-width: + maxItems: 1 + examples: - | #include @@ -108,3 +128,23 @@ examples: reset-gpios =3D <&gpio0 1 GPIO_ACTIVE_LOW>; }; }; + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad4630-24"; + reg =3D <0>; + spi-max-frequency =3D <80000000>; + spi-rx-bus-width =3D <4>, <4>; + vdd-5v-supply =3D <&supply_5V>; + vdd-1v8-supply =3D <&supply_1_8V>; + vio-supply =3D <&supply_1_8V>; + ref-supply =3D <&supply_5V>; + cnv-gpios =3D <&gpio0 0 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4695.yaml index cbde7a0505d2..ae8d0b5f328b 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4695.yaml @@ -38,8 +38,9 @@ properties: spi-cpha: true =20 spi-rx-bus-width: - minimum: 1 - maximum: 4 + items: + minimum: 1 + maximum: 4 =20 avdd-supply: description: Analog power supply. diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.= yaml b/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml index e1ab3f523ad6..a34e6471dbe8 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml @@ -55,10 +55,12 @@ patternProperties: maximum: 4 =20 spi-rx-bus-width: - const: 1 + items: + - const: 1 =20 spi-tx-bus-width: - const: 1 + items: + - const: 1 =20 required: - compatible diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.= yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml index 1b91d1566c95..a6067030c5ed 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml @@ -81,10 +81,12 @@ patternProperties: maximum: 4 =20 spi-rx-bus-width: - const: 1 + items: + - const: 1 =20 spi-tx-bus-width: - const: 1 + items: + - const: 1 =20 required: - compatible diff --git a/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml= b/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml index 78093468dd5e..8e441742cee6 100644 --- a/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml +++ b/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml @@ -45,10 +45,12 @@ patternProperties: =20 properties: spi-rx-bus-width: - enum: [1, 4] + items: + - enum: [1, 4] =20 spi-tx-bus-width: - enum: [1, 4] + items: + - enum: [1, 4] =20 allOf: - $ref: spi-controller.yaml# diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yam= l b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml index 8b3640280559..909c204b8adf 100644 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml @@ -54,10 +54,12 @@ patternProperties: =20 properties: spi-rx-bus-width: - enum: [1, 2, 4] + items: + - enum: [1, 2, 4] =20 spi-tx-bus-width: - enum: [1, 2, 4] + items: + - enum: [1, 2, 4] =20 required: - compatible diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yam= l b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 8b6e8fc009db..59ddead7da14 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -64,9 +64,16 @@ properties: description: Bus width to the SPI bus used for read transfers. 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These properties allow specifying the mapping of peripheral data lanes to controller data lanes. This is needed e.g. when some lanes are skipped on the controller side so that the controller can correctly route data to/from the peripheral. Reviewed-by: Rob Herring (Arm) Signed-off-by: David Lechner Reviewed-by: Jonathan Cameron --- v5 changes: - Use SDI/SDO terminology in descriptions. (Fixes incorrect use of TX/RX when describing the peripheral lanes.) v4 changes: - This replaces the data-lanes property from the previous revision. Now there are separate properties for tx and rx lane maps. And instead of being the primary property for determining the number of lanes, this is only needed in special cases where the mapping is non-trivial. --- .../devicetree/bindings/spi/spi-peripheral-props.yaml | 14 ++++++++++= ++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yam= l b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 59ddead7da14..880a9f624566 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -75,6 +75,13 @@ properties: enum: [0, 1, 2, 4, 8] default: [1] =20 + spi-rx-lane-map: + description: Mapping of peripheral SDO lanes to controller SDI lanes. + Each index in the array represents a peripheral SDO lane, and the va= lue + at that index represents the corresponding controller SDI lane. + $ref: /schemas/types.yaml#/definitions/uint32-array + default: [0, 1, 2, 3, 4, 5, 6, 7] + spi-rx-delay-us: description: Delay, in microseconds, after a read transfer. @@ -99,6 +106,13 @@ properties: enum: [0, 1, 2, 4, 8] default: [1] =20 + spi-tx-lane-map: + description: Mapping of peripheral SDI lanes to controller SDO lanes. + Each index in the array represents a peripheral SDI lane, and the va= lue + at that index represents the corresponding controller SDO lane. + $ref: /schemas/types.yaml#/definitions/uint32-array + default: [0, 1, 2, 3, 4, 5, 6, 7] + spi-tx-delay-us: description: Delay, in microseconds, after a write transfer. --=20 2.43.0 From nobody Sun Feb 8 18:31:44 2026 Received: from mail-ot1-f41.google.com (mail-ot1-f41.google.com [209.85.210.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B353B37F0E8 for ; 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Mon, 12 Jan 2026 09:46:31 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:6b4b:49b3:cce5:b58f]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-3ffa4de40bfsm12126941fac.5.2026.01.12.09.46.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jan 2026 09:46:31 -0800 (PST) From: David Lechner Date: Mon, 12 Jan 2026 11:45:21 -0600 Subject: [PATCH v5 3/9] spi: support controllers with multiple data lanes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260112-spi-add-multi-bus-support-v5-3-295f4f09f6ba@baylibre.com> References: <20260112-spi-add-multi-bus-support-v5-0-295f4f09f6ba@baylibre.com> In-Reply-To: <20260112-spi-add-multi-bus-support-v5-0-295f4f09f6ba@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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(A data lane in this context means lines connected to a serializer, so a controller with two data lanes would have two serializers in a single controller). This is common in the type of controller that can be used with parallel flash memories, but can be used for general purpose SPI as well. To indicate support, a controller just needs to set ctlr->num_data_lanes to something greater than 1. Peripherals indicate which lane they are connected to via device tree (ACPI support can be added if needed). The spi-{tx,rx}-bus-width DT properties can now be arrays. The length of the array indicates the number of data lanes, and each element indicates the bus width of that lane. For now, we restrict all lanes to have the same bus width to keep things simple. Support for an optional controller lane mapping property is also implemented. Signed-off-by: David Lechner --- v5 changes: - Use of_property_read_variable_u32_array() for lane maps. v4 changes: - Update for changes in devicetree bindings. - Don't put new fields in the middle of CS fields. - Dropped acks since this was a significant rework. v3 changes: * Renamed "buses" to "lanes" to reflect devicetree property name change. This patch has been seen in a different series [1] by Sean before: [1]: https://lore.kernel.org/linux-spi/20250616220054.3968946-4-sean.anders= on@linux.dev/ Changes: * Use u8 array instead of bitfield so that the order of the mapping is preserved. (Now looks very much like chip select mapping.) * Added doc strings for added fields. * Tweaked the comments. --- drivers/spi/spi.c | 116 ++++++++++++++++++++++++++++++++++++++++++++= +++- include/linux/spi/spi.h | 22 +++++++++ 2 files changed, 136 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index e25df9990f82..5c3f9ba3f606 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -2370,7 +2370,53 @@ static int of_spi_parse_dt(struct spi_controller *ct= lr, struct spi_device *spi, spi->mode |=3D SPI_CS_HIGH; =20 /* Device DUAL/QUAD mode */ - if (!of_property_read_u32(nc, "spi-tx-bus-width", &value)) { + + rc =3D of_property_read_variable_u32_array(nc, "spi-tx-lane-map", + spi->tx_lane_map, 1, + ARRAY_SIZE(spi->tx_lane_map)); + if (rc =3D=3D -EINVAL) { + /* Default lane map */ + for (idx =3D 0; idx < ARRAY_SIZE(spi->tx_lane_map); idx++) + spi->tx_lane_map[idx] =3D idx; + } else if (rc < 0) { + dev_err(&ctlr->dev, + "failed to read spi-tx-lane-map property: %d\n", rc); + return rc; + } + + rc =3D of_property_count_u32_elems(nc, "spi-tx-bus-width"); + if (rc < 0 && rc !=3D -EINVAL) { + dev_err(&ctlr->dev, + "failed to read spi-tx-bus-width property: %d\n", rc); + return rc; + } + + if (rc =3D=3D -EINVAL) { + /* Default when property is not present. */ + spi->num_tx_lanes =3D 1; + } else { + u32 first_value; + + spi->num_tx_lanes =3D rc; + + for (idx =3D 0; idx < spi->num_tx_lanes; idx++) { + of_property_read_u32_index(nc, "spi-tx-bus-width", idx, + &value); + + /* + * For now, we only support all lanes having the same + * width so we can keep using the existing mode flags. + */ + if (!idx) + first_value =3D value; + else if (first_value !=3D value) { + dev_err(&ctlr->dev, + "spi-tx-bus-width has inconsistent values: first %d vs later %d\n", + first_value, value); + return -EINVAL; + } + } + switch (value) { case 0: spi->mode |=3D SPI_NO_TX; @@ -2394,7 +2440,62 @@ static int of_spi_parse_dt(struct spi_controller *ct= lr, struct spi_device *spi, } } =20 - if (!of_property_read_u32(nc, "spi-rx-bus-width", &value)) { + for (idx =3D 0; idx < spi->num_tx_lanes; idx++) { + if (spi->tx_lane_map[idx] >=3D spi->controller->num_data_lanes) { + dev_err(&ctlr->dev, + "spi-tx-lane-map has invalid value %d (num_data_lanes=3D%d)\n", + spi->tx_lane_map[idx], + spi->controller->num_data_lanes); + return -EINVAL; + } + } + + rc =3D of_property_read_variable_u32_array(nc, "spi-rx-lane-map", + spi->rx_lane_map, 1, + ARRAY_SIZE(spi->rx_lane_map)); + if (rc =3D=3D -EINVAL) { + /* Default lane map */ + for (idx =3D 0; idx < ARRAY_SIZE(spi->rx_lane_map); idx++) + spi->rx_lane_map[idx] =3D idx; + } else if (rc < 0) { + dev_err(&ctlr->dev, + "failed to read spi-rx-lane-map property: %d\n", rc); + return rc; + } + + rc =3D of_property_count_u32_elems(nc, "spi-rx-bus-width"); + if (rc < 0 && rc !=3D -EINVAL) { + dev_err(&ctlr->dev, + "failed to read spi-rx-bus-width property: %d\n", rc); + return rc; + } + + if (rc =3D=3D -EINVAL) { + /* Default when property is not present. */ + spi->num_rx_lanes =3D 1; + } else { + u32 first_value; + + spi->num_rx_lanes =3D rc; + + for (idx =3D 0; idx < spi->num_rx_lanes; idx++) { + of_property_read_u32_index(nc, "spi-rx-bus-width", idx, + &value); + + /* + * For now, we only support all lanes having the same + * width so we can keep using the existing mode flags. + */ + if (!idx) + first_value =3D value; + else if (first_value !=3D value) { + dev_err(&ctlr->dev, + "spi-rx-bus-width has inconsistent values: first %d vs later %d\n", + first_value, value); + return -EINVAL; + } + } + switch (value) { case 0: spi->mode |=3D SPI_NO_RX; @@ -2418,6 +2519,16 @@ static int of_spi_parse_dt(struct spi_controller *ct= lr, struct spi_device *spi, } } =20 + for (idx =3D 0; idx < spi->num_rx_lanes; idx++) { + if (spi->rx_lane_map[idx] >=3D spi->controller->num_data_lanes) { + dev_err(&ctlr->dev, + "spi-rx-lane-map has invalid value %d (num_data_lanes=3D%d)\n", + spi->rx_lane_map[idx], + spi->controller->num_data_lanes); + return -EINVAL; + } + } + if (spi_controller_is_target(ctlr)) { if (!of_node_name_eq(nc, "slave")) { dev_err(&ctlr->dev, "%pOF is not called 'slave'\n", @@ -3066,6 +3177,7 @@ struct spi_controller *__spi_alloc_controller(struct = device *dev, mutex_init(&ctlr->add_lock); ctlr->bus_num =3D -1; ctlr->num_chipselect =3D 1; + ctlr->num_data_lanes =3D 1; ctlr->target =3D target; if (IS_ENABLED(CONFIG_SPI_SLAVE) && target) ctlr->dev.class =3D &spi_target_class; diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index cb2c2df31089..7aff60ab257e 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -23,6 +23,9 @@ /* Max no. of CS supported per spi device */ #define SPI_DEVICE_CS_CNT_MAX 4 =20 +/* Max no. of data lanes supported per spi device */ +#define SPI_DEVICE_DATA_LANE_CNT_MAX 8 + struct dma_chan; struct software_node; struct ptp_system_timestamp; @@ -174,6 +177,10 @@ extern void spi_transfer_cs_change_delay_exec(struct s= pi_message *msg, * @cs_index_mask: Bit mask of the active chipselect(s) in the chipselect = array * @cs_gpiod: Array of GPIO descriptors of the corresponding chipselect li= nes * (optional, NULL when not using a GPIO line) + * @tx_lane_map: Map of peripheral lanes (index) to controller lanes (valu= e). + * @num_tx_lanes: Number of transmit lanes wired up. + * @rx_lane_map: Map of peripheral lanes (index) to controller lanes (valu= e). + * @num_rx_lanes: Number of receive lanes wired up. * * A @spi_device is used to interchange data between an SPI target device * (usually a discrete chip) and CPU memory. @@ -242,6 +249,12 @@ struct spi_device { =20 struct gpio_desc *cs_gpiod[SPI_DEVICE_CS_CNT_MAX]; /* Chip select gpio de= sc */ =20 + /* Multi-lane SPI controller support. */ + u32 tx_lane_map[SPI_DEVICE_DATA_LANE_CNT_MAX]; + u32 num_tx_lanes; + u32 rx_lane_map[SPI_DEVICE_DATA_LANE_CNT_MAX]; + u32 num_rx_lanes; + /* * Likely need more hooks for more protocol options affecting how * the controller talks to each chip, like: @@ -401,6 +414,7 @@ extern struct spi_device *spi_new_ancillary_device(stru= ct spi_device *spi, u8 ch * SPI targets, and are numbered from zero to num_chipselects. * each target has a chipselect signal, but it's common that not * every chipselect is connected to a target. + * @num_data_lanes: Number of data lanes supported by this controller. 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Mon, 12 Jan 2026 09:46:34 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:6b4b:49b3:cce5:b58f]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-3ffa4de40bfsm12126941fac.5.2026.01.12.09.46.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jan 2026 09:46:33 -0800 (PST) From: David Lechner Date: Mon, 12 Jan 2026 11:45:22 -0600 Subject: [PATCH v5 4/9] spi: add multi_lane_mode field to struct spi_transfer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260112-spi-add-multi-bus-support-v5-4-295f4f09f6ba@baylibre.com> References: <20260112-spi-add-multi-bus-support-v5-0-295f4f09f6ba@baylibre.com> In-Reply-To: <20260112-spi-add-multi-bus-support-v5-0-295f4f09f6ba@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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This requires both the peripheral and the controller to have multiple serializers connected to separate data lanes. It could also be used with a single controller and multiple peripherals that are functioning as a single logical device (similar to parallel memories). Acked-by: Nuno S=C3=A1 Acked-by: Marcelo Schmitt Signed-off-by: David Lechner Reviewed-by: Jonathan Cameron --- v4 changes: * Shortened commit message (useful info will be in docs instead). * Added whitespace to create clear grouping of macros and the field. v3 changes: * Renamed "buses" to "lanes" to reflect devicetree property name change. --- include/linux/spi/spi.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 7aff60ab257e..eba7ae8466ac 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -981,6 +981,8 @@ struct spi_res { * (SPI_NBITS_SINGLE) is used. * @rx_nbits: number of bits used for reading. If 0 the default * (SPI_NBITS_SINGLE) is used. + * @multi_lane_mode: How to serialize data on multiple lanes. One of the + * SPI_MULTI_LANE_MODE_* values. * @len: size of rx and tx buffers (in bytes) * @speed_hz: Select a speed other than the device default for this * transfer. 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Mon, 12 Jan 2026 09:46:35 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:6b4b:49b3:cce5:b58f]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-3ffa4de40bfsm12126941fac.5.2026.01.12.09.46.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jan 2026 09:46:35 -0800 (PST) From: David Lechner Date: Mon, 12 Jan 2026 11:45:23 -0600 Subject: [PATCH v5 5/9] spi: Documentation: add page on multi-lane support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260112-spi-add-multi-bus-support-v5-5-295f4f09f6ba@baylibre.com> References: <20260112-spi-add-multi-bus-support-v5-0-295f4f09f6ba@baylibre.com> In-Reply-To: <20260112-spi-add-multi-bus-support-v5-0-295f4f09f6ba@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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This is uncommon functionality so it deserves its own documentation page. Reviewed-by: Marcelo Schmitt Signed-off-by: David Lechner --- v5 changes: * Fix tx/rx typo in stripe mode example. v4 changes: * New patch in v4. --- Documentation/spi/index.rst | 1 + Documentation/spi/multiple-data-lanes.rst | 217 ++++++++++++++++++++++++++= ++++ 2 files changed, 218 insertions(+) diff --git a/Documentation/spi/index.rst b/Documentation/spi/index.rst index 824ce42ed4f0..2c89b1ee39e2 100644 --- a/Documentation/spi/index.rst +++ b/Documentation/spi/index.rst @@ -9,6 +9,7 @@ Serial Peripheral Interface (SPI) =20 spi-summary spidev + multiple-data-lanes butterfly spi-lm70llp spi-sc18is602 diff --git a/Documentation/spi/multiple-data-lanes.rst b/Documentation/spi/= multiple-data-lanes.rst new file mode 100644 index 000000000000..96d6997ecf77 --- /dev/null +++ b/Documentation/spi/multiple-data-lanes.rst @@ -0,0 +1,217 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +SPI devices with multiple data lanes +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Some specialized SPI controllers and peripherals support multiple data lan= es +that allow reading more than one word at a time in parallel. This is diffe= rent +from dual/quad/octal SPI where multiple bits of a single word are transfer= red +simultaneously. + +For example, controllers that support parallel flash memories have this fe= ature +as do some simultaneous-sampling ADCs where each channel has its own data = lane. + +--------------------- +Describing the wiring +--------------------- + +The ``spi-tx-bus-width`` and ``spi-rx-bus-width`` properties in the device= tree +are used to describe how many data lanes are connected between the control= ler +and how wide each lane is. The number of items in the array indicates how = many +lanes there are, and the value of each item indicates how many bits wide t= hat +lane is. + +For example, a dual-simultaneous-sampling ADC with two 4-bit lanes might be +wired up like this:: + + +--------------+ +----------+ + | SPI | | AD4630 | + | Controller | | ADC | + | | | | + | CS0 |--->| CS | + | SCK |--->| SCK | + | SDO |--->| SDI | + | | | | + | SDIA0 |<---| SDOA0 | + | SDIA1 |<---| SDOA1 | + | SDIA2 |<---| SDOA2 | + | SDIA3 |<---| SDOA3 | + | | | | + | SDIB0 |<---| SDOB0 | + | SDIB1 |<---| SDOB1 | + | SDIB2 |<---| SDOB2 | + | SDIB3 |<---| SDOB3 | + | | | | + +--------------+ +----------+ + +It is described in a devicetree like this:: + + spi { + compatible =3D "my,spi-controller"; + + ... + + adc@0 { + compatible =3D "adi,ad4630"; + reg =3D <0>; + ... + spi-rx-bus-width =3D <4>, <4>; /* 2 lanes of 4 bits each */ + ... + }; + }; + +In most cases, lanes will be wired up symmetrically (A to A, B to B, etc).= If +this isn't the case, extra ``spi-rx-bus-width`` and ``spi-tx-bus-width`` +properties are needed to provide a mapping between controller lanes and the +physical lane wires. + +Here is an example where a multi-lane SPI controller has each lane wired to +separate single-lane peripherals:: + + +--------------+ +----------+ + | SPI | | Thing 1 | + | Controller | | | + | | | | + | CS0 |--->| CS | + | SDO0 |--->| SDI | + | SDI0 |<---| SDO | + | SCLK0 |--->| SCLK | + | | | | + | | +----------+ + | | + | | +----------+ + | | | Thing 2 | + | | | | + | CS1 |--->| CS | + | SDO1 |--->| SDI | + | SDI1 |<---| SDO | + | SCLK1 |--->| SCLK | + | | | | + +--------------+ +----------+ + +This is described in a devicetree like this:: + + spi { + compatible =3D "my,spi-controller"; + + ... + + thing1@0 { + compatible =3D "my,thing1"; + reg =3D <0>; + ... + }; + + thing2@1 { + compatible =3D "my,thing2"; + reg =3D <1>; + ... + spi-tx-lane-map =3D <1>; /* lane 0 is not used, lane 1 is used= for tx wire */ + spi-rx-lane-map =3D <1>; /* lane 0 is not used, lane 1 is used= for rx wire */ + ... + }; + }; + + +The default values of ``spi-rx-bus-width`` and ``spi-tx-bus-width`` are ``= <1>``, +so these properties can still be omitted even when ``spi-rx-lane-map`` and +``spi-tx-lane-map`` are used. + +---------------------------- +Usage in a peripheral driver +---------------------------- + +These types of SPI controllers generally do not support arbitrary use of t= he +multiple lanes. Instead, they operate in one of a few defined modes. Perip= heral +drivers should set the :c:type:`struct spi_transfer.multi_lane_mode ` +field to indicate which mode they want to use for a given transfer. + +The possible values for this field have the following semantics: + +- :c:macro:`SPI_MULTI_BUS_MODE_SINGLE`: Only use the first lane. Other lan= es are + ignored. This means that it is operating just like a conventional SPI + peripheral. This is the default, so it does not need to be explicitly = set. + + Example:: + + tx_buf[0] =3D 0x88; + + struct spi_transfer xfer =3D { + .tx_buf =3D tx_buf, + .len =3D 1, + }; + + spi_sync_transfer(spi, &xfer, 1); + + Assuming the controller is sending the MSB first, the sequence of bits + sent over the tx wire would be (right-most bit is sent first):: + + controller > data bits > peripheral + ---------- ---------------- ---------- + SDO 0 0-0-0-1-0-0-0-1 SDI 0 + +- :c:macro:`SPI_MULTI_BUS_MODE_MIRROR`: Send a single data word over all o= f the + lanes at the same time. This only makes sense for writes and not + for reads. + + Example:: + + tx_buf[0] =3D 0x88; + + struct spi_transfer xfer =3D { + .tx_buf =3D tx_buf, + .len =3D 1, + .multi_lane_mode =3D SPI_MULTI_BUS_MODE_MIRROR, + }; + + spi_sync_transfer(spi, &xfer, 1); + + The data is mirrored on each tx wire:: + + controller > data bits > peripheral + ---------- ---------------- ---------- + SDO 0 0-0-0-1-0-0-0-1 SDI 0 + SDO 1 0-0-0-1-0-0-0-1 SDI 1 + +- :c:macro:`SPI_MULTI_BUS_MODE_STRIPE`: Send or receive two different data= words + at the same time, one on each lane. This means that the buffer needs t= o be + sized to hold data for all lanes. Data is interleaved in the buffer, w= ith + the first word corresponding to lane 0, the second to lane 1, and so o= n. + Once the last lane is used, the next word in the buffer corresponds to= lane + 0 again. Accordingly, the buffer size must be a multiple of the number= of + lanes. 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Mon, 12 Jan 2026 09:46:36 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:6b4b:49b3:cce5:b58f]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-3ffa4de40bfsm12126941fac.5.2026.01.12.09.46.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jan 2026 09:46:36 -0800 (PST) From: David Lechner Date: Mon, 12 Jan 2026 11:45:24 -0600 Subject: [PATCH v5 6/9] spi: dt-bindings: adi,axi-spi-engine: add multi-lane support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260112-spi-add-multi-bus-support-v5-6-295f4f09f6ba@baylibre.com> References: <20260112-spi-add-multi-bus-support-v5-0-295f4f09f6ba@baylibre.com> In-Reply-To: <20260112-spi-add-multi-bus-support-v5-0-295f4f09f6ba@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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This SPI controller has a capability to read multiple data words at the same time (e.g. for use with simultaneous sampling ADCs). The current FPGA implementation can support up to 8 data lanes at a time (depending on a compile-time configuration option). Reviewed-by: Rob Herring (Arm) Signed-off-by: David Lechner Reviewed-by: Jonathan Cameron --- v4 changes: - Update to use spi-{tx,rx}-bus-width properties. --- .../devicetree/bindings/spi/adi,axi-spi-engine.yaml | 15 +++++++++++= ++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml = b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml index 4b3828eda6cb..0f2448371f17 100644 --- a/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml +++ b/Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml @@ -70,6 +70,21 @@ required: =20 unevaluatedProperties: false =20 +patternProperties: + "^.*@[0-9a-f]+": + type: object + + properties: + spi-rx-bus-width: + maxItems: 8 + items: + enum: [0, 1] + + spi-tx-bus-width: + maxItems: 8 + items: + enum: [0, 1] + examples: - | spi@44a00000 { --=20 2.43.0 From nobody Sun Feb 8 18:31:44 2026 Received: from mail-oa1-f52.google.com (mail-oa1-f52.google.com [209.85.160.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D1CB37E318 for ; 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Mon, 12 Jan 2026 09:46:37 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:6b4b:49b3:cce5:b58f]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-3ffa4de40bfsm12126941fac.5.2026.01.12.09.46.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jan 2026 09:46:37 -0800 (PST) From: David Lechner Date: Mon, 12 Jan 2026 11:45:25 -0600 Subject: [PATCH v5 7/9] spi: axi-spi-engine: support SPI_MULTI_LANE_MODE_STRIPE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260112-spi-add-multi-bus-support-v5-7-295f4f09f6ba@baylibre.com> References: <20260112-spi-add-multi-bus-support-v5-0-295f4f09f6ba@baylibre.com> In-Reply-To: <20260112-spi-add-multi-bus-support-v5-0-295f4f09f6ba@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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The v2.0.0 version of the AXI SPI Engine IP core supports multiple lanes. This can be used with SPI_MULTI_LANE_MODE_STRIPE to support reading from simultaneous sampling ADCs that have a separate SDO line for each analog channel. This allows reading all channels at the same time to increase throughput. Reviewed-by: Marcelo Schmitt Signed-off-by: David Lechner Reviewed-by: Jonathan Cameron --- v4 changes: * Update for core SPI API changes. v3 changes: * Renamed "buses" to "lanes" to reflect devicetree property name change. v2 changes: * Fixed off-by-one in SPI_ENGINE_REG_DATA_WIDTH_NUM_OF_SDIO_MASK GENMASK --- drivers/spi/spi-axi-spi-engine.c | 145 +++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 141 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-axi-spi-engine.c b/drivers/spi/spi-axi-spi-eng= ine.c index e06f412190fd..3028e6112909 100644 --- a/drivers/spi/spi-axi-spi-engine.c +++ b/drivers/spi/spi-axi-spi-engine.c @@ -23,6 +23,9 @@ #include #include =20 +#define SPI_ENGINE_REG_DATA_WIDTH 0x0C +#define SPI_ENGINE_REG_DATA_WIDTH_NUM_OF_SDIO_MASK GENMASK(23, 16) +#define SPI_ENGINE_REG_DATA_WIDTH_MASK GENMASK(15, 0) #define SPI_ENGINE_REG_OFFLOAD_MEM_ADDR_WIDTH 0x10 #define SPI_ENGINE_REG_RESET 0x40 =20 @@ -75,6 +78,8 @@ #define SPI_ENGINE_CMD_REG_CLK_DIV 0x0 #define SPI_ENGINE_CMD_REG_CONFIG 0x1 #define SPI_ENGINE_CMD_REG_XFER_BITS 0x2 +#define SPI_ENGINE_CMD_REG_SDI_MASK 0x3 +#define SPI_ENGINE_CMD_REG_SDO_MASK 0x4 =20 #define SPI_ENGINE_MISC_SYNC 0x0 #define SPI_ENGINE_MISC_SLEEP 0x1 @@ -105,6 +110,10 @@ #define SPI_ENGINE_OFFLOAD_CMD_FIFO_SIZE 16 #define SPI_ENGINE_OFFLOAD_SDO_FIFO_SIZE 16 =20 +/* Extending SPI_MULTI_LANE_MODE values for optimizing messages. */ +#define SPI_ENGINE_MULTI_BUS_MODE_UNKNOWN -1 +#define SPI_ENGINE_MULTI_BUS_MODE_CONFLICTING -2 + struct spi_engine_program { unsigned int length; uint16_t instructions[] __counted_by(length); @@ -142,6 +151,11 @@ struct spi_engine_offload { unsigned long flags; unsigned int offload_num; unsigned int spi_mode_config; + unsigned int multi_lane_mode; + u8 rx_primary_lane_mask; + u8 tx_primary_lane_mask; + u8 rx_all_lanes_mask; + u8 tx_all_lanes_mask; u8 bits_per_word; }; =20 @@ -165,6 +179,25 @@ struct spi_engine { bool offload_requires_sync; }; =20 +static void spi_engine_primary_lane_flag(struct spi_device *spi, + u8 *rx_lane_flags, u8 *tx_lane_flags) +{ + *rx_lane_flags =3D BIT(spi->rx_lane_map[0]); + *tx_lane_flags =3D BIT(spi->tx_lane_map[0]); +} + +static void spi_engine_all_lanes_flags(struct spi_device *spi, + u8 *rx_lane_flags, u8 *tx_lane_flags) +{ + int i; + + for (i =3D 0; i < spi->num_rx_lanes; i++) + *rx_lane_flags |=3D BIT(spi->rx_lane_map[i]); + + for (i =3D 0; i < spi->num_tx_lanes; i++) + *tx_lane_flags |=3D BIT(spi->tx_lane_map[i]); +} + static void spi_engine_program_add_cmd(struct spi_engine_program *p, bool dry, uint16_t cmd) { @@ -193,7 +226,7 @@ static unsigned int spi_engine_get_config(struct spi_de= vice *spi) } =20 static void spi_engine_gen_xfer(struct spi_engine_program *p, bool dry, - struct spi_transfer *xfer) + struct spi_transfer *xfer, u32 num_lanes) { unsigned int len; =20 @@ -204,6 +237,9 @@ static void spi_engine_gen_xfer(struct spi_engine_progr= am *p, bool dry, else len =3D xfer->len / 4; =20 + if (xfer->multi_lane_mode =3D=3D SPI_MULTI_LANE_MODE_STRIPE) + len /=3D num_lanes; + while (len) { unsigned int n =3D min(len, 256U); unsigned int flags =3D 0; @@ -269,6 +305,7 @@ static int spi_engine_precompile_message(struct spi_mes= sage *msg) { unsigned int clk_div, max_hz =3D msg->spi->controller->max_speed_hz; struct spi_transfer *xfer; + int multi_lane_mode =3D SPI_ENGINE_MULTI_BUS_MODE_UNKNOWN; u8 min_bits_per_word =3D U8_MAX; u8 max_bits_per_word =3D 0; =20 @@ -284,6 +321,24 @@ static int spi_engine_precompile_message(struct spi_me= ssage *msg) min_bits_per_word =3D min(min_bits_per_word, xfer->bits_per_word); max_bits_per_word =3D max(max_bits_per_word, xfer->bits_per_word); } + + if (xfer->rx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_RX_STREAM || + xfer->tx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_TX_STREAM) { + switch (xfer->multi_lane_mode) { + case SPI_MULTI_LANE_MODE_SINGLE: + case SPI_MULTI_LANE_MODE_STRIPE: + break; + default: + /* Other modes, like mirror not supported */ + return -EINVAL; + } + + /* If all xfers have the same multi-lane mode, we can optimize. */ + if (multi_lane_mode =3D=3D SPI_ENGINE_MULTI_BUS_MODE_UNKNOWN) + multi_lane_mode =3D xfer->multi_lane_mode; + else if (multi_lane_mode !=3D xfer->multi_lane_mode) + multi_lane_mode =3D SPI_ENGINE_MULTI_BUS_MODE_CONFLICTING; + } } =20 /* @@ -297,6 +352,14 @@ static int spi_engine_precompile_message(struct spi_me= ssage *msg) priv->bits_per_word =3D min_bits_per_word; else priv->bits_per_word =3D 0; + + priv->multi_lane_mode =3D multi_lane_mode; + spi_engine_primary_lane_flag(msg->spi, + &priv->rx_primary_lane_mask, + &priv->tx_primary_lane_mask); + spi_engine_all_lanes_flags(msg->spi, + &priv->rx_all_lanes_mask, + &priv->tx_all_lanes_mask); } =20 return 0; @@ -310,6 +373,7 @@ static void spi_engine_compile_message(struct spi_messa= ge *msg, bool dry, struct spi_engine_offload *priv; struct spi_transfer *xfer; int clk_div, new_clk_div, inst_ns; + int prev_multi_lane_mode =3D SPI_MULTI_LANE_MODE_SINGLE; bool keep_cs =3D false; u8 bits_per_word =3D 0; =20 @@ -334,6 +398,7 @@ static void spi_engine_compile_message(struct spi_messa= ge *msg, bool dry, * in the same way. */ bits_per_word =3D priv->bits_per_word; + prev_multi_lane_mode =3D priv->multi_lane_mode; } else { spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CONFIG, @@ -344,6 +409,28 @@ static void spi_engine_compile_message(struct spi_mess= age *msg, bool dry, spi_engine_gen_cs(p, dry, spi, !xfer->cs_off); =20 list_for_each_entry(xfer, &msg->transfers, transfer_list) { + if (xfer->rx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_RX_STREAM || + xfer->tx_buf || xfer->offload_flags & SPI_OFFLOAD_XFER_TX_STREAM) { + if (xfer->multi_lane_mode !=3D prev_multi_lane_mode) { + u8 tx_lane_flags, rx_lane_flags; + + if (xfer->multi_lane_mode =3D=3D SPI_MULTI_LANE_MODE_STRIPE) + spi_engine_all_lanes_flags(spi, &rx_lane_flags, + &tx_lane_flags); + else + spi_engine_primary_lane_flag(spi, &rx_lane_flags, + &tx_lane_flags); + + spi_engine_program_add_cmd(p, dry, + SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, + rx_lane_flags)); + spi_engine_program_add_cmd(p, dry, + SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, + tx_lane_flags)); + } + prev_multi_lane_mode =3D xfer->multi_lane_mode; + } + new_clk_div =3D host->max_speed_hz / xfer->effective_speed_hz; if (new_clk_div !=3D clk_div) { clk_div =3D new_clk_div; @@ -360,7 +447,7 @@ static void spi_engine_compile_message(struct spi_messa= ge *msg, bool dry, bits_per_word)); } =20 - spi_engine_gen_xfer(p, dry, xfer); + spi_engine_gen_xfer(p, dry, xfer, spi->num_rx_lanes); spi_engine_gen_sleep(p, dry, spi_delay_to_ns(&xfer->delay, xfer), inst_ns, xfer->effective_speed_hz); =20 @@ -394,6 +481,19 @@ static void spi_engine_compile_message(struct spi_mess= age *msg, bool dry, if (clk_div !=3D 1) spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CLK_DIV, 0)); + + /* Restore single lane mode unless offload disable will restore it later.= */ + if (prev_multi_lane_mode =3D=3D SPI_MULTI_LANE_MODE_STRIPE && + (!msg->offload || priv->multi_lane_mode !=3D SPI_MULTI_LANE_MODE_STRI= PE)) { + u8 rx_lane_flags, tx_lane_flags; + + spi_engine_primary_lane_flag(spi, &rx_lane_flags, &tx_lane_flags); + + spi_engine_program_add_cmd(p, dry, + SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, rx_lane_flags)); + spi_engine_program_add_cmd(p, dry, + SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, tx_lane_flags)); + } } =20 static void spi_engine_xfer_next(struct spi_message *msg, @@ -799,6 +899,19 @@ static int spi_engine_setup(struct spi_device *device) writel_relaxed(SPI_ENGINE_CMD_CS_INV(spi_engine->cs_inv), spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); =20 + if (host->num_data_lanes > 1) { + u8 rx_lane_flags, tx_lane_flags; + + spi_engine_primary_lane_flag(device, &rx_lane_flags, &tx_lane_flags); + + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, + rx_lane_flags), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, + tx_lane_flags), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + } + /* * In addition to setting the flags, we have to do a CS assert command * to make the new setting actually take effect. @@ -902,6 +1015,15 @@ static int spi_engine_trigger_enable(struct spi_offlo= ad *offload) priv->bits_per_word), spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); =20 + if (priv->multi_lane_mode =3D=3D SPI_MULTI_LANE_MODE_STRIPE) { + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, + priv->rx_all_lanes_mask), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, + priv->tx_all_lanes_mask), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + } + writel_relaxed(SPI_ENGINE_CMD_SYNC(1), spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); =20 @@ -929,6 +1051,16 @@ static void spi_engine_trigger_disable(struct spi_off= load *offload) reg &=3D ~SPI_ENGINE_OFFLOAD_CTRL_ENABLE; writel_relaxed(reg, spi_engine->base + SPI_ENGINE_REG_OFFLOAD_CTRL(priv->offload_num)); + + /* Restore single-lane mode. */ + if (priv->multi_lane_mode =3D=3D SPI_MULTI_LANE_MODE_STRIPE) { + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDI_MASK, + priv->rx_primary_lane_mask), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + writel_relaxed(SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_SDO_MASK, + priv->tx_primary_lane_mask), + spi_engine->base + SPI_ENGINE_REG_CMD_FIFO); + } } =20 static struct dma_chan @@ -973,7 +1105,7 @@ static int spi_engine_probe(struct platform_device *pd= ev) { struct spi_engine *spi_engine; struct spi_controller *host; - unsigned int version; + unsigned int version, data_width_reg_val; int irq, ret; =20 irq =3D platform_get_irq(pdev, 0); @@ -1042,7 +1174,7 @@ static int spi_engine_probe(struct platform_device *p= dev) return PTR_ERR(spi_engine->base); =20 version =3D readl(spi_engine->base + ADI_AXI_REG_VERSION); - if (ADI_AXI_PCORE_VER_MAJOR(version) !=3D 1) { + if (ADI_AXI_PCORE_VER_MAJOR(version) > 2) { dev_err(&pdev->dev, "Unsupported peripheral version %u.%u.%u\n", ADI_AXI_PCORE_VER_MAJOR(version), ADI_AXI_PCORE_VER_MINOR(version), @@ -1050,6 +1182,8 @@ static int spi_engine_probe(struct platform_device *p= dev) return -ENODEV; } =20 + data_width_reg_val =3D readl(spi_engine->base + SPI_ENGINE_REG_DATA_WIDTH= ); + if (adi_axi_pcore_ver_gteq(version, 1, 1)) { unsigned int sizes =3D readl(spi_engine->base + SPI_ENGINE_REG_OFFLOAD_MEM_ADDR_WIDTH); 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These chips are simultaneous sampling ADCs and have one SDO line per channel, either 2 or 4 total depending on the part number. Reviewed-by: Rob Herring (Arm) Signed-off-by: David Lechner --- v4 changes: * Change to use spi-rx-bus-width property instead of spi-lanes. v3 changes: * Renamed "buses" to "lanes" to reflect devicetree property name change. --- .../devicetree/bindings/iio/adc/adi,ad7380.yaml | 23 ++++++++++++++++++= ++++ 1 file changed, 23 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7380.yaml index b91bfb16ed6b..396e1a1aa805 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7380.yaml @@ -62,6 +62,11 @@ properties: spi-cpol: true spi-cpha: true =20 + spi-rx-bus-width: + maxItems: 4 + items: + maximum: 1 + vcc-supply: description: A 3V to 3.6V supply that powers the chip. =20 @@ -160,6 +165,23 @@ patternProperties: unevaluatedProperties: false =20 allOf: + # 2-channel chips only have two SDO lines + - if: + properties: + compatible: + enum: + - adi,ad7380 + - adi,ad7381 + - adi,ad7383 + - adi,ad7384 + - adi,ad7386 + - adi,ad7387 + - adi,ad7388 + then: + properties: + spi-rx-bus-width: + maxItems: 2 + # pseudo-differential chips require common mode voltage supplies, # true differential chips don't use them - if: @@ -284,6 +306,7 @@ examples: spi-cpol; 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Mon, 12 Jan 2026 09:46:41 -0800 (PST) Received: from [127.0.1.1] ([2600:8803:e7e4:500:6b4b:49b3:cce5:b58f]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-3ffa4de40bfsm12126941fac.5.2026.01.12.09.46.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jan 2026 09:46:40 -0800 (PST) From: David Lechner Date: Mon, 12 Jan 2026 11:45:27 -0600 Subject: [PATCH v5 9/9] iio: adc: ad7380: add support for multiple SPI lanes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260112-spi-add-multi-bus-support-v5-9-295f4f09f6ba@baylibre.com> References: <20260112-spi-add-multi-bus-support-v5-0-295f4f09f6ba@baylibre.com> In-Reply-To: <20260112-spi-add-multi-bus-support-v5-0-295f4f09f6ba@baylibre.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko Cc: Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, David Lechner X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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The AD7380 family of ADCs have multiple SDO lines on the chip that can be used to read each channel on a separate SPI lane. If wired up to a SPI controller that supports it, the driver will now take advantage of this feature. This allows reaching the maximum sample rate advertised in the datasheet when combined with SPI offloading. Reviewed-by: Nuno S=C3=A1 Reviewed-by: Marcelo Schmitt Signed-off-by: David Lechner --- v5 changes: * Include the number of SDO lines in the error message. v4 changes: * Update for core SPI API changes. v3 changes: * Renamed "buses" to "lanes" to reflect devicetree property name change. v2 changes: * Move st->seq_xfer[3].multi_lane_mode =3D SPI_MULTI_BUS_MODE_STRIPE; to probe(). --- drivers/iio/adc/ad7380.c | 51 ++++++++++++++++++++++++++++++++++++--------= ---- 1 file changed, 38 insertions(+), 13 deletions(-) diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c index bfd908deefc0..ca411371816f 100644 --- a/drivers/iio/adc/ad7380.c +++ b/drivers/iio/adc/ad7380.c @@ -77,8 +77,7 @@ #define AD7380_CONFIG1_REFSEL BIT(1) #define AD7380_CONFIG1_PMODE BIT(0) =20 -#define AD7380_CONFIG2_SDO2 GENMASK(9, 8) -#define AD7380_CONFIG2_SDO BIT(8) +#define AD7380_CONFIG2_SDO GENMASK(9, 8) #define AD7380_CONFIG2_RESET GENMASK(7, 0) =20 #define AD7380_CONFIG2_RESET_SOFT 0x3C @@ -92,11 +91,6 @@ #define T_CONVERT_X_NS 500 /* xth conversion start time (oversampling) */ #define T_POWERUP_US 5000 /* Power up */ =20 -/* - * AD738x support several SDO lines to increase throughput, but driver cur= rently - * supports only 1 SDO line (standard SPI transaction) - */ -#define AD7380_NUM_SDO_LINES 1 #define AD7380_DEFAULT_GAIN_MILLI 1000 =20 /* @@ -888,6 +882,8 @@ struct ad7380_state { bool resolution_boost_enabled; unsigned int ch; bool seq; + /* How many SDO lines are wired up. */ + u8 num_sdo_lines; unsigned int vref_mv; unsigned int vcm_mv[MAX_NUM_CHANNELS]; unsigned int gain_milli[MAX_NUM_CHANNELS]; @@ -1084,7 +1080,7 @@ static int ad7380_set_ch(struct ad7380_state *st, uns= igned int ch) if (oversampling_ratio > 1) xfer.delay.value =3D T_CONVERT_0_NS + T_CONVERT_X_NS * (oversampling_ratio - 1) * - st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES; + st->chip_info->num_simult_channels / st->num_sdo_lines; =20 return spi_sync_transfer(st->spi, &xfer, 1); } @@ -1113,7 +1109,7 @@ static int ad7380_update_xfers(struct ad7380_state *s= t, if (oversampling_ratio > 1) t_convert =3D T_CONVERT_0_NS + T_CONVERT_X_NS * (oversampling_ratio - 1) * - st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES; + st->chip_info->num_simult_channels / st->num_sdo_lines; =20 if (st->seq) { xfer[0].delay.value =3D xfer[1].delay.value =3D t_convert; @@ -1198,6 +1194,8 @@ static int ad7380_init_offload_msg(struct ad7380_stat= e *st, xfer->bits_per_word =3D scan_type->realbits; xfer->offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; xfer->len =3D AD7380_SPI_BYTES(scan_type) * st->chip_info->num_simult_cha= nnels; + if (st->num_sdo_lines > 1) + xfer->multi_lane_mode =3D SPI_MULTI_LANE_MODE_STRIPE; =20 spi_message_init_with_transfers(&st->offload_msg, xfer, 1); st->offload_msg.offload =3D st->offload; @@ -1793,6 +1791,7 @@ static const struct iio_info ad7380_info =3D { =20 static int ad7380_init(struct ad7380_state *st, bool external_ref_en) { + u32 sdo; int ret; =20 /* perform hard reset */ @@ -1815,11 +1814,24 @@ static int ad7380_init(struct ad7380_state *st, boo= l external_ref_en) st->ch =3D 0; st->seq =3D false; =20 - /* SPI 1-wire mode */ + /* SDO field has an irregular mapping. */ + switch (st->num_sdo_lines) { + case 1: + sdo =3D 1; + break; + case 2: + sdo =3D 0; + break; + case 4: + sdo =3D 2; + break; + default: + return -EINVAL; + } + return regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, AD7380_CONFIG2_SDO, - FIELD_PREP(AD7380_CONFIG2_SDO, - AD7380_NUM_SDO_LINES)); + FIELD_PREP(AD7380_CONFIG2_SDO, sdo)); } =20 static int ad7380_probe_spi_offload(struct iio_dev *indio_dev, @@ -1842,7 +1854,7 @@ static int ad7380_probe_spi_offload(struct iio_dev *i= ndio_dev, "failed to get offload trigger\n"); =20 sample_rate =3D st->chip_info->max_conversion_rate_hz * - AD7380_NUM_SDO_LINES / st->chip_info->num_simult_channels; + st->num_sdo_lines / st->chip_info->num_simult_channels; =20 st->sample_freq_range[0] =3D 1; /* min */ st->sample_freq_range[1] =3D 1; /* step */ @@ -1887,6 +1899,13 @@ static int ad7380_probe(struct spi_device *spi) if (!st->chip_info) return dev_err_probe(dev, -EINVAL, "missing match data\n"); =20 + st->num_sdo_lines =3D spi->num_rx_lanes; + + if (st->num_sdo_lines < 1 || st->num_sdo_lines > st->chip_info->num_simul= t_channels) + return dev_err_probe(dev, -EINVAL, + "invalid number of SDO lines (%d)\n", + st->num_sdo_lines); + ret =3D devm_regulator_bulk_get_enable(dev, st->chip_info->num_supplies, st->chip_info->supplies); =20 @@ -2010,6 +2029,8 @@ static int ad7380_probe(struct spi_device *spi) st->normal_xfer[0].cs_change_delay.value =3D st->chip_info->timing_specs-= >t_csh_ns; st->normal_xfer[0].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; st->normal_xfer[1].rx_buf =3D st->scan_data; + if (st->num_sdo_lines > 1) + st->normal_xfer[1].multi_lane_mode =3D SPI_MULTI_LANE_MODE_STRIPE; =20 spi_message_init_with_transfers(&st->normal_msg, st->normal_xfer, ARRAY_SIZE(st->normal_xfer)); @@ -2031,6 +2052,10 @@ static int ad7380_probe(struct spi_device *spi) st->seq_xfer[2].cs_change =3D 1; st->seq_xfer[2].cs_change_delay.value =3D st->chip_info->timing_specs->t_= csh_ns; st->seq_xfer[2].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; + if (st->num_sdo_lines > 1) { + st->seq_xfer[2].multi_lane_mode =3D SPI_MULTI_LANE_MODE_STRIPE; + st->seq_xfer[3].multi_lane_mode =3D SPI_MULTI_LANE_MODE_STRIPE; + } =20 spi_message_init_with_transfers(&st->seq_msg, st->seq_xfer, ARRAY_SIZE(st->seq_xfer)); --=20 2.43.0