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Mon, 12 Jan 2026 02:16:41 -0800 (PST) Received: from brgl-qcom.local ([2a01:cb1d:dc:7e00:eb74:bf66:83a8:4e98]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47d865f0cf2sm126530355e9.3.2026.01.12.02.16.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jan 2026 02:16:41 -0800 (PST) From: Bartosz Golaszewski Date: Mon, 12 Jan 2026 11:15:46 +0100 Subject: [PATCH RESEND net-next v6 7/7] net: stmmac: qcom-ethqos: add support for sa8255p Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260112-qcom-sa8255p-emac-v6-7-86a3d4b2ad83@oss.qualcomm.com> References: <20260112-qcom-sa8255p-emac-v6-0-86a3d4b2ad83@oss.qualcomm.com> In-Reply-To: <20260112-qcom-sa8255p-emac-v6-0-86a3d4b2ad83@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Andrew Lunn , "David S. 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Jaya Kumaran" , Clark Wang , Linux Team , Frank Li , David Wu , Samin Guo , Christophe Roullier , Swathi K S , Bartosz Golaszewski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Drew Fustini , linux-sunxi@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-renesas-soc@vger.kernel.org, linux-rockchip@lists.infradead.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, Bartosz Golaszewski , Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11165; i=bartosz.golaszewski@oss.qualcomm.com; h=from:subject:message-id; bh=Q4SqwaEAy0IJuUoTx5Bp8FCAYjHMaOkZg5PDcibPFy8=; b=owEBbQKS/ZANAwAKAQWdLsv/NoTDAcsmYgBpZMntsWlm4Apuxv8jvFWEjs4JamoLfF23vK94x EWQucytZNqJAjMEAAEKAB0WIQSR5RMt5bVGHXuiZfwFnS7L/zaEwwUCaWTJ7QAKCRAFnS7L/zaE w1oVD/92r422DsOUyqEO0JTWxjhBhRUCUsiAse4D5wRHEp7uEYWB/k+LtgscpIwiiPb4xTXG83y 3ChBZUvT8j6cj51KWa8kNgjyUu3fSFz1lcn/+tngDc1PHIDEGMMNDYSPP7UjQCtfi+6zjm3BCJz m7npoS+M15kAN02TpEhg0uwpJyIR8OTXwiIAoYxIdxm7l1J2mghP4NHSjQ2THaiLQtQkog1DONl gtAQ6WNTU+QoX8tRr6PU/vTDcu50X0n15BYpUWlRl2JiQQ7j6oo4aTBwECq+pStwKJHS6Aol0FU Vag1UfGNNbtQgPcMWS/sOHMitiYNRrXww5orrwBB+NOFW/8JrNmMrXQNJHLiDpkHs4lCrMmLs6b oIWHJxLQof12Yu/HFLoXxOb2g4bi7m+fFObMZPLqN61ar9Sd5ii1s6qsFoBvKsB7DRlOHksv4sL ZTUfnkUm/X/trorKTBT3rd1z22VSk0Rzi3QpIoeGMeMOBT62ZoceMMdhpCqxWYROMNTfwBXlQYq PoodmiAzQUEz+ACjO2SlzBKbZBOiO99cvgDyLWClwb1krNOTxWjEDTvsqofdilKMWXUxbPoZNXX z8ffcKG4dxW52ef2qoT+IP+T/XsHuCYL0lqRT8jm4MpPpWN4OerC/fRHr4lW1plgo2LetgXGqzx moKId7VMtPY2i8g== X-Developer-Key: i=bartosz.golaszewski@oss.qualcomm.com; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTEyMDA4MSBTYWx0ZWRfX5/mr1n+zdR88 RTI+msdxwMXzkni54j0m0OZt+34fKZJQfcmgDWhbqofBWRmfwwkk6XVENf9c9/EaAhfPZ5kzq3b JWQha2SM2bxZCKBqYFVmKBCppsMuawtPZOoxD1oKtOocBfypD1FQ0QV5CHHbyMb7NJIS7hlQGsF yP7Ct0BaQ6FU9LOSZ/w+8dncIbIiCOSv8ffi0wIuMcb/gQpFkYgJ3U3yvYGj1ex9QBJzMqhATBP KvB5kB8RczRtamZitqDFWUBIvMSY/suxKhqtl+Vo4qKoe0xQktHvjGh9f++S1gcqEE654yxfhWY q3rkvgsw4Lnpahx80oACZZZb7+td2dkJQzRf1V1P46IrzpfbMTvirszCpPm3OoIayqgG5zMX+S0 sCpQXlNS5yZuItM7lRMFDc4bgeLrBV3O+rMaahocPoBgzcOJxtSvdvPPfVez/QiloQCTZSOC2Io zu1nhqBJEA9g8L6WO0g== X-Authority-Analysis: v=2.4 cv=R6AO2NRX c=1 sm=1 tr=0 ts=6964ca0b cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=gYhETRYomtM5McKHAMIA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: 0H9ceot8t1vbjwSnIKzKVPcdM4FTDxjD X-Proofpoint-GUID: 0H9ceot8t1vbjwSnIKzKVPcdM4FTDxjD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-12_03,2026-01-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 spamscore=0 clxscore=1015 priorityscore=1501 adultscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601120081 From: Bartosz Golaszewski Extend the driver to support a new model - sa8255p. Unlike the previously supported variants, this one's power management is done in the firmware using SCMI. This is modeled in linux using power domains so add support for them. Signed-off-by: Bartosz Golaszewski Signed-off-by: Bartosz Golaszewski --- .../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 234 +++++++++++++++++= +--- 1 file changed, 209 insertions(+), 25 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/driv= ers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c index 8ba57bba3f2eebe9e44964f9e6c7c67e46ccb02d..54f8ef3cfd7d55a89920c94d4ba= 13c331d51d26c 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 #include "stmmac.h" #include "stmmac_platform.h" @@ -81,6 +83,13 @@ =20 #define SGMII_10M_RX_CLK_DVDR 0x31 =20 +enum ethqos_pd_selector { + ETHQOS_PD_CORE =3D 0, + ETHQOS_PD_MDIO, + ETHQOS_PD_SERDES, + ETHQOS_NUM_PDS, +}; + struct ethqos_emac_por { unsigned int offset; unsigned int value; @@ -98,6 +107,9 @@ struct ethqos_emac_driver_data { =20 struct ethqos_emac_pm_data { const char *link_clk_name; + bool use_domains; + struct dev_pm_domain_attach_data pd; + unsigned int clk_ptp_rate; }; =20 struct ethqos_emac_match_data { @@ -111,13 +123,20 @@ struct ethqos_emac_pm_ctx { struct phy *serdes_phy; }; =20 +struct ethqos_emac_pd_ctx { + struct dev_pm_domain_list *pd_list; +}; + struct qcom_ethqos { struct platform_device *pdev; void __iomem *rgmii_base; void __iomem *mac_base; int (*configure_func)(struct qcom_ethqos *ethqos, int speed); =20 - struct ethqos_emac_pm_ctx pm; + union { + struct ethqos_emac_pm_ctx pm; + struct ethqos_emac_pd_ctx pd; + }; phy_interface_t phy_mode; int serdes_speed; int (*set_serdes_speed)(struct qcom_ethqos *ethqos); @@ -341,6 +360,25 @@ static const struct ethqos_emac_match_data emac_sa8775= p_data =3D { .pm_data =3D &emac_sa8775p_pm_data, }; =20 +static const char * const emac_sa8255p_pd_names[] =3D { + "core", "mdio", "serdes" +}; + +static const struct ethqos_emac_pm_data emac_sa8255p_pm_data =3D { + .pd =3D { + .pd_flags =3D PD_FLAG_NO_DEV_LINK, + .pd_names =3D emac_sa8255p_pd_names, + .num_pd_names =3D ETHQOS_NUM_PDS, + }, + .use_domains =3D true, + .clk_ptp_rate =3D 230400000, +}; + +static const struct ethqos_emac_match_data emac_sa8255p_data =3D { + .drv_data =3D &emac_v4_0_0_data, + .pm_data =3D &emac_sa8255p_pm_data, +}; + static int ethqos_dll_configure(struct qcom_ethqos *ethqos) { struct device *dev =3D ðqos->pdev->dev; @@ -407,6 +445,28 @@ static int ethqos_dll_configure(struct qcom_ethqos *et= hqos) return 0; } =20 +static int qcom_ethqos_domain_on(struct qcom_ethqos *ethqos, + enum ethqos_pd_selector sel) +{ + struct device *dev =3D ethqos->pd.pd_list->pd_devs[sel]; + int ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + dev_err(ðqos->pdev->dev, + "Failed to enable the power domain for %s\n", + dev_name(dev)); + return ret; +} + +static void qcom_ethqos_domain_off(struct qcom_ethqos *ethqos, + enum ethqos_pd_selector sel) +{ + struct device *dev =3D ethqos->pd.pd_list->pd_devs[sel]; + + pm_runtime_put_sync(dev); +} + static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed) { struct device *dev =3D ðqos->pdev->dev; @@ -623,6 +683,13 @@ static int ethqos_set_serdes_speed_phy(struct qcom_eth= qos *ethqos) return phy_set_speed(ethqos->pm.serdes_phy, ethqos->serdes_speed); } =20 +static int ethqos_set_serdes_speed_pd(struct qcom_ethqos *ethqos) +{ + struct device *dev =3D ethqos->pd.pd_list->pd_devs[ETHQOS_PD_SERDES]; + + return dev_pm_opp_set_level(dev, ethqos->serdes_speed); +} + static void ethqos_set_serdes_speed(struct qcom_ethqos *ethqos, int speed) { if (ethqos->serdes_speed !=3D speed) { @@ -712,6 +779,28 @@ static void qcom_ethqos_serdes_powerdown(struct net_de= vice *ndev, void *priv) phy_exit(ethqos->pm.serdes_phy); } =20 +static int qcom_ethqos_pd_serdes_powerup(struct net_device *ndev, void *pr= iv) +{ + struct qcom_ethqos *ethqos =3D priv; + struct device *dev =3D ethqos->pd.pd_list->pd_devs[ETHQOS_PD_SERDES]; + int ret; + + ret =3D qcom_ethqos_domain_on(ethqos, ETHQOS_PD_SERDES); + if (ret < 0) + return ret; + + return dev_pm_opp_set_level(dev, ethqos->serdes_speed); +} + +static void qcom_ethqos_pd_serdes_powerdown(struct net_device *ndev, void = *priv) +{ + struct qcom_ethqos *ethqos =3D priv; + struct device *dev =3D ethqos->pd.pd_list->pd_devs[ETHQOS_PD_SERDES]; + + dev_pm_opp_set_level(dev, 0); + qcom_ethqos_domain_off(ethqos, ETHQOS_PD_SERDES); +} + static int ethqos_clks_config(void *priv, bool enabled) { struct qcom_ethqos *ethqos =3D priv; @@ -742,6 +831,68 @@ static void ethqos_clks_disable(void *data) ethqos_clks_config(data, false); } =20 +static void ethqos_disable_serdes(void *data) +{ + struct qcom_ethqos *ethqos =3D data; + + qcom_ethqos_domain_on(ethqos, ETHQOS_PD_SERDES); +} + +static int ethqos_pd_clks_config(void *priv, bool enabled) +{ + struct qcom_ethqos *ethqos =3D priv; + int ret =3D 0; + + if (enabled) { + ret =3D qcom_ethqos_domain_on(ethqos, ETHQOS_PD_MDIO); + if (ret < 0) { + dev_err(ðqos->pdev->dev, + "Failed to enable the MDIO power domain\n"); + return ret; + } + + ethqos_set_func_clk_en(ethqos); + } else { + qcom_ethqos_domain_off(ethqos, ETHQOS_PD_MDIO); + } + + return ret; +} + +static int qcom_ethqos_pd_init(struct device *dev, void *priv) +{ + struct qcom_ethqos *ethqos =3D priv; + int ret; + + /* + * Enable functional clock to prevent DMA reset after timeout due + * to no PHY clock being enabled after the hardware block has been + * power cycled. The actual configuration will be adjusted once + * ethqos_fix_mac_speed() is called. + */ + ethqos_set_func_clk_en(ethqos); + + ret =3D qcom_ethqos_domain_on(ethqos, ETHQOS_PD_CORE); + if (ret) + return ret; + + ret =3D qcom_ethqos_domain_on(ethqos, ETHQOS_PD_MDIO); + if (ret) { + qcom_ethqos_domain_off(ethqos, ETHQOS_PD_CORE); + return ret; + } + + return 0; +} + +static void qcom_ethqos_pd_exit(struct device *dev, void *data) +{ + struct qcom_ethqos *ethqos =3D data; + + qcom_ethqos_domain_off(ethqos, ETHQOS_PD_MDIO); + qcom_ethqos_domain_off(ethqos, ETHQOS_PD_CORE); +} + static void ethqos_ptp_clk_freq_config(struct stmmac_priv *priv) { struct plat_stmmacenet_data *plat_dat =3D priv->plat; @@ -782,8 +933,6 @@ static int qcom_ethqos_probe(struct platform_device *pd= ev) "dt configuration failed\n"); } =20 - plat_dat->clks_config =3D ethqos_clks_config; - ethqos =3D devm_kzalloc(dev, sizeof(*ethqos), GFP_KERNEL); if (!ethqos) return -ENOMEM; @@ -825,28 +974,67 @@ static int qcom_ethqos_probe(struct platform_device *= pdev) ethqos->rgmii_config_loopback_en =3D drv_data->rgmii_config_loopback_en; ethqos->has_emac_ge_3 =3D drv_data->has_emac_ge_3; ethqos->needs_sgmii_loopback =3D drv_data->needs_sgmii_loopback; + ethqos->serdes_speed =3D SPEED_1000; =20 - ethqos->pm.link_clk =3D devm_clk_get(dev, clk_name); - if (IS_ERR(ethqos->pm.link_clk)) - return dev_err_probe(dev, PTR_ERR(ethqos->pm.link_clk), - "Failed to get link_clk\n"); + if (pm_data && pm_data->use_domains) { + ethqos->set_serdes_speed =3D ethqos_set_serdes_speed_pd; =20 - ret =3D ethqos_clks_config(ethqos, true); - if (ret) - return ret; + ret =3D devm_pm_domain_attach_list(dev, &pm_data->pd, + ðqos->pd.pd_list); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to attach power domains\n"); =20 - ret =3D devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos); - if (ret) - return ret; + plat_dat->clks_config =3D ethqos_pd_clks_config; + plat_dat->serdes_powerup =3D qcom_ethqos_pd_serdes_powerup; + plat_dat->serdes_powerdown =3D qcom_ethqos_pd_serdes_powerdown; + plat_dat->exit =3D qcom_ethqos_pd_exit; + plat_dat->init =3D qcom_ethqos_pd_init; + plat_dat->clk_ptp_rate =3D pm_data->clk_ptp_rate; =20 - ethqos->pm.serdes_phy =3D devm_phy_optional_get(dev, "serdes"); - if (IS_ERR(ethqos->pm.serdes_phy)) - return dev_err_probe(dev, PTR_ERR(ethqos->pm.serdes_phy), - "Failed to get serdes phy\n"); + ret =3D qcom_ethqos_pd_init(dev, ethqos); + if (ret) + return ret; + + ret =3D qcom_ethqos_domain_on(ethqos, ETHQOS_PD_SERDES); + if (ret) + return dev_err_probe(dev, ret, + "Failed to enable the serdes power domain\n"); + + ret =3D devm_add_action_or_reset(dev, ethqos_disable_serdes, ethqos); + if (ret) + return ret; + } else { + ethqos->set_serdes_speed =3D ethqos_set_serdes_speed_phy; + + ethqos->pm.link_clk =3D devm_clk_get(dev, clk_name); + if (IS_ERR(ethqos->pm.link_clk)) + return dev_err_probe(dev, PTR_ERR(ethqos->pm.link_clk), + "Failed to get link_clk\n"); + + ret =3D ethqos_clks_config(ethqos, true); + if (ret) + return ret; + + ret =3D devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos); + if (ret) + return ret; + + ethqos->pm.serdes_phy =3D devm_phy_optional_get(dev, "serdes"); + if (IS_ERR(ethqos->pm.serdes_phy)) + return dev_err_probe(dev, PTR_ERR(ethqos->pm.serdes_phy), + "Failed to get serdes phy\n"); + + ethqos_update_link_clk(ethqos, SPEED_1000); + + plat_dat->clks_config =3D ethqos_clks_config; + plat_dat->ptp_clk_freq_config =3D ethqos_ptp_clk_freq_config; + + if (ethqos->pm.serdes_phy) { + plat_dat->serdes_powerup =3D qcom_ethqos_serdes_powerup; + plat_dat->serdes_powerdown =3D qcom_ethqos_serdes_powerdown; + } + } =20 - ethqos->set_serdes_speed =3D ethqos_set_serdes_speed_phy; - ethqos->serdes_speed =3D SPEED_1000; - ethqos_update_link_clk(ethqos, SPEED_1000); ethqos_set_func_clk_en(ethqos); =20 plat_dat->bsp_priv =3D ethqos; @@ -864,11 +1052,6 @@ static int qcom_ethqos_probe(struct platform_device *= pdev) if (drv_data->dma_addr_width) plat_dat->host_dma_width =3D drv_data->dma_addr_width; =20 - if (ethqos->pm.serdes_phy) { - plat_dat->serdes_powerup =3D qcom_ethqos_serdes_powerup; - plat_dat->serdes_powerdown =3D qcom_ethqos_serdes_powerdown; - } - /* Enable TSO on queue0 and enable TBS on rest of the queues */ for (i =3D 1; i < plat_dat->tx_queues_to_use; i++) plat_dat->tx_queues_cfg[i].tbs_en =3D 1; @@ -878,6 +1061,7 @@ static int qcom_ethqos_probe(struct platform_device *p= dev) =20 static const struct of_device_id qcom_ethqos_match[] =3D { { .compatible =3D "qcom,qcs404-ethqos", .data =3D &emac_qcs404_data}, + { .compatible =3D "qcom,sa8255p-ethqos", .data =3D &emac_sa8255p_data}, { .compatible =3D "qcom,sa8775p-ethqos", .data =3D &emac_sa8775p_data}, { .compatible =3D "qcom,sc8280xp-ethqos", .data =3D &emac_sc8280xp_data}, { .compatible =3D "qcom,sm8150-ethqos", .data =3D &emac_sm8150_data}, --=20 2.47.3