From nobody Mon Feb 9 08:29:19 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2663D36922B; Mon, 12 Jan 2026 16:28:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768235314; cv=none; b=rl3zd4j+asUUJjfheZR+MOCen3EDHauS8vQ7XGB5g/Mz29MJkDtnf3tCnfeI6KNv/9lGEF37qYD4YACowZrgCoBLS6NZZj61J0Jrj6NQ7FcREIYK3A6UgM8DIV7u7e9o0tk4tR3ThAaGxSoij265ZzE+VBE7iDWubC5lzI7oFyI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768235314; c=relaxed/simple; bh=TY7wS/PnEUr5RA2e8U4YV4dpDVuXbnCrxqd074doQm0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JWEXoKgU8ZxeHYXjzP0M23ol5FqJYaErdJtwG2GAljd10k4tmuvYGe3gOantaH8VCxCqCSw1lIyIFC/afRlGH8T8W2dZKc9WsnsF+xq5Q6naWNURqjnpeeng3Cqj57BvSPuKU2fAJLxhc/ocrd+b6sD1fDOR0n3RQEGxZu4HYNo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GmTfcckp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GmTfcckp" Received: by smtp.kernel.org (Postfix) with ESMTPS id DA3B2C19424; Mon, 12 Jan 2026 16:28:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768235313; bh=TY7wS/PnEUr5RA2e8U4YV4dpDVuXbnCrxqd074doQm0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=GmTfcckpXrM8mX2pvDgNEhldeTuFv2o20cP4iO3XE8HKvp3OEYJneKDwFfEGTBK5N knqzztygcbeMIZc2T1OzplcPPO3IUVlU13qlJ+fiU+tSLgOFY0vC/yr68N8SqgUEqw c4wY9bkAVUI1S4c6ke3itjmU1gmfv1NB5JAAr31KK61eVjXi6fBlkWFhffAkA/fRob sZ8R1WCQIL9XQ7slEKAiL0EVZ5K/IWy3Q6E1/vu4QqRLNQanuabwFx5///wA+NiIvt 9EFXzn2ASujXQYGr4sBmjoYlIjs225B7OtTQt/vyhEyvLcWPJrDItaTCpTApl2DMzh NZi5FItPgei/Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0FB5D26D97; Mon, 12 Jan 2026 16:28:33 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Mon, 12 Jan 2026 21:56:07 +0530 Subject: [PATCH v4 8/9] power: sequencing: pcie-m2: Add support for PCIe M.2 Key E connectors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260112-pci-m2-e-v4-8-eff84d2c6d26@oss.qualcomm.com> References: <20260112-pci-m2-e-v4-0-eff84d2c6d26@oss.qualcomm.com> In-Reply-To: <20260112-pci-m2-e-v4-0-eff84d2c6d26@oss.qualcomm.com> To: Rob Herring , Greg Kroah-Hartman , Jiri Slaby , Nathan Chancellor , Nicolas Schier , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Mark Pearson , "Derek J. Clark" , Manivannan Sadhasivam , Krzysztof Kozlowski , Conor Dooley , Marcel Holtmann , Luiz Augusto von Dentz , Bartosz Golaszewski , Andy Shevchenko , Bartosz Golaszewski Cc: linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kbuild@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-bluetooth@vger.kernel.org, linux-pm@vger.kernel.org, Stephan Gerhold , Dmitry Baryshkov , linux-acpi@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=7599; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=i6i8PHXC7zEwHnq+Aby8WFbHrLt0WziJAFUdslemlFU=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpZSEuwOS4ymgyUnylCHk62VuTbi8H9MV6j0FnB Gg+cAGN8mGJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaWUhLgAKCRBVnxHm/pHO 9d09B/4xNCqjm74pleFKd7aqFZ4vZr5N4njk0LJnjssI5bPldYgbZrhhTWpPQ/ptuhm1UOFlafc ev7f3Kxn0BibYh7ob2zJWqrZcWyEKK3o1Lcy49gxLDQ5sIuWN1v30SOZkBCX7YphsZHkiHVRpk5 GfoBKNPvLm0DQlrXZrt5Mg+gJgCcruf0I3aeqUiCTuI/TW3bGDh10rX4lm57j9yn/BdjqXvo6JG CoSIASo4sUvYTbjUysYArUNakinzBnKMU8fnpY8j2pQdAN9ME7GLxdbV/7wilEO28xRmuDj/qv5 EqfQRMwhDvd5BxePCGfms/27fRs+848HkAWW1b4uCoCZoIIs X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam Add support for handling the power sequence of the PCIe M.2 Key E connectors. These connectors are used to attach the Wireless Connectivity devices to the host machine including combinations of WiFi, BT, NFC using interfaces such as PCIe/SDIO for WiFi, USB/UART for BT and I2C for NFC. Currently, this driver supports only the PCIe interface for WiFi and UART interface for BT. The driver also only supports driving the 3.3v/1.8v power supplies and W_DISABLE{1/2}# GPIOs. The optional signals of the Key E connectors are not currently supported. Signed-off-by: Manivannan Sadhasivam --- drivers/power/sequencing/Kconfig | 1 + drivers/power/sequencing/pwrseq-pcie-m2.c | 110 ++++++++++++++++++++++++++= ++-- 2 files changed, 104 insertions(+), 7 deletions(-) diff --git a/drivers/power/sequencing/Kconfig b/drivers/power/sequencing/Kc= onfig index f5fff84566ba..29bd204319cc 100644 --- a/drivers/power/sequencing/Kconfig +++ b/drivers/power/sequencing/Kconfig @@ -38,6 +38,7 @@ config POWER_SEQUENCING_TH1520_GPU config POWER_SEQUENCING_PCIE_M2 tristate "PCIe M.2 connector power sequencing driver" depends on OF || COMPILE_TEST + depends on PCI help Say Y here to enable the power sequencing driver for PCIe M.2 connectors. This driver handles the power sequencing for the M.2 diff --git a/drivers/power/sequencing/pwrseq-pcie-m2.c b/drivers/power/sequ= encing/pwrseq-pcie-m2.c index e01e19123415..4b85a40d7692 100644 --- a/drivers/power/sequencing/pwrseq-pcie-m2.c +++ b/drivers/power/sequencing/pwrseq-pcie-m2.c @@ -4,12 +4,16 @@ * Author: Manivannan Sadhasivam */ =20 +#include #include +#include +#include #include #include #include #include #include +#include #include #include #include @@ -25,17 +29,19 @@ struct pwrseq_pcie_m2_ctx { const struct pwrseq_pcie_m2_pdata *pdata; struct regulator_bulk_data *regs; size_t num_vregs; - struct notifier_block nb; + struct gpio_desc *w_disable1_gpio; + struct gpio_desc *w_disable2_gpio; + struct device *dev; }; =20 -static int pwrseq_pcie_m2_m_vregs_enable(struct pwrseq_device *pwrseq) +static int pwrseq_pcie_m2_vregs_enable(struct pwrseq_device *pwrseq) { struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); =20 return regulator_bulk_enable(ctx->num_vregs, ctx->regs); } =20 -static int pwrseq_pcie_m2_m_vregs_disable(struct pwrseq_device *pwrseq) +static int pwrseq_pcie_m2_vregs_disable(struct pwrseq_device *pwrseq) { struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); =20 @@ -44,18 +50,84 @@ static int pwrseq_pcie_m2_m_vregs_disable(struct pwrseq= _device *pwrseq) =20 static const struct pwrseq_unit_data pwrseq_pcie_m2_vregs_unit_data =3D { .name =3D "regulators-enable", - .enable =3D pwrseq_pcie_m2_m_vregs_enable, - .disable =3D pwrseq_pcie_m2_m_vregs_disable, + .enable =3D pwrseq_pcie_m2_vregs_enable, + .disable =3D pwrseq_pcie_m2_vregs_disable, }; =20 -static const struct pwrseq_unit_data *pwrseq_pcie_m2_m_unit_deps[] =3D { +static const struct pwrseq_unit_data *pwrseq_pcie_m2_unit_deps[] =3D { &pwrseq_pcie_m2_vregs_unit_data, NULL }; =20 +static int pwrseq_pci_m2_e_uart_enable(struct pwrseq_device *pwrseq) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + + return gpiod_set_value_cansleep(ctx->w_disable2_gpio, 0); +} + +static int pwrseq_pci_m2_e_uart_disable(struct pwrseq_device *pwrseq) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + + return gpiod_set_value_cansleep(ctx->w_disable2_gpio, 1); +} + +static const struct pwrseq_unit_data pwrseq_pcie_m2_e_uart_unit_data =3D { + .name =3D "uart-enable", + .deps =3D pwrseq_pcie_m2_unit_deps, + .enable =3D pwrseq_pci_m2_e_uart_enable, + .disable =3D pwrseq_pci_m2_e_uart_disable, +}; + +static int pwrseq_pci_m2_e_pcie_enable(struct pwrseq_device *pwrseq) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + + return gpiod_set_value_cansleep(ctx->w_disable1_gpio, 0); +} + +static int pwrseq_pci_m2_e_pcie_disable(struct pwrseq_device *pwrseq) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + + return gpiod_set_value_cansleep(ctx->w_disable1_gpio, 1); +} + +static const struct pwrseq_unit_data pwrseq_pcie_m2_e_pcie_unit_data =3D { + .name =3D "pcie-enable", + .deps =3D pwrseq_pcie_m2_unit_deps, + .enable =3D pwrseq_pci_m2_e_pcie_enable, + .disable =3D pwrseq_pci_m2_e_pcie_disable, +}; + static const struct pwrseq_unit_data pwrseq_pcie_m2_m_pcie_unit_data =3D { .name =3D "pcie-enable", - .deps =3D pwrseq_pcie_m2_m_unit_deps, + .deps =3D pwrseq_pcie_m2_unit_deps, +}; + +static int pwrseq_pcie_m2_e_pwup_delay(struct pwrseq_device *pwrseq) +{ + /* + * FIXME: This delay is only required for some Qcom WLAN/BT cards like + * WCN7850 and not for all devices. But currently, there is no way to + * identify the device model before enumeration. + */ + msleep(50); + + return 0; +} + +static const struct pwrseq_target_data pwrseq_pcie_m2_e_uart_target_data = =3D { + .name =3D "uart", + .unit =3D &pwrseq_pcie_m2_e_uart_unit_data, + .post_enable =3D pwrseq_pcie_m2_e_pwup_delay, +}; + +static const struct pwrseq_target_data pwrseq_pcie_m2_e_pcie_target_data = =3D { + .name =3D "pcie", + .unit =3D &pwrseq_pcie_m2_e_pcie_unit_data, + .post_enable =3D pwrseq_pcie_m2_e_pwup_delay, }; =20 static const struct pwrseq_target_data pwrseq_pcie_m2_m_pcie_target_data = =3D { @@ -63,11 +135,21 @@ static const struct pwrseq_target_data pwrseq_pcie_m2_= m_pcie_target_data =3D { .unit =3D &pwrseq_pcie_m2_m_pcie_unit_data, }; =20 +static const struct pwrseq_target_data *pwrseq_pcie_m2_e_targets[] =3D { + &pwrseq_pcie_m2_e_pcie_target_data, + &pwrseq_pcie_m2_e_uart_target_data, + NULL +}; + static const struct pwrseq_target_data *pwrseq_pcie_m2_m_targets[] =3D { &pwrseq_pcie_m2_m_pcie_target_data, NULL }; =20 +static const struct pwrseq_pcie_m2_pdata pwrseq_pcie_m2_e_of_data =3D { + .targets =3D pwrseq_pcie_m2_e_targets, +}; + static const struct pwrseq_pcie_m2_pdata pwrseq_pcie_m2_m_of_data =3D { .targets =3D pwrseq_pcie_m2_m_targets, }; @@ -126,6 +208,16 @@ static int pwrseq_pcie_m2_probe(struct platform_device= *pdev) return dev_err_probe(dev, ret, "Failed to get all regulators\n"); =20 + ctx->w_disable1_gpio =3D devm_gpiod_get_optional(dev, "w-disable1", GPIOD= _OUT_HIGH); + if (IS_ERR(ctx->w_disable1_gpio)) + return dev_err_probe(dev, PTR_ERR(ctx->w_disable1_gpio), + "Failed to get the W_DISABLE_1# GPIO\n"); + + ctx->w_disable2_gpio =3D devm_gpiod_get_optional(dev, "w-disable2", GPIOD= _OUT_HIGH); + if (IS_ERR(ctx->w_disable2_gpio)) + return dev_err_probe(dev, PTR_ERR(ctx->w_disable2_gpio), + "Failed to get the W_DISABLE_2# GPIO\n"); + ctx->num_vregs =3D ret; =20 ret =3D devm_add_action_or_reset(dev, pwrseq_pcie_free_resources, ctx); @@ -151,6 +243,10 @@ static const struct of_device_id pwrseq_pcie_m2_of_mat= ch[] =3D { .compatible =3D "pcie-m2-m-connector", .data =3D &pwrseq_pcie_m2_m_of_data, }, + { + .compatible =3D "pcie-m2-e-connector", + .data =3D &pwrseq_pcie_m2_e_of_data, + }, { } }; MODULE_DEVICE_TABLE(of, pwrseq_pcie_m2_of_match); --=20 2.48.1