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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-59b792cf330sm2758871e87.102.2026.01.11.19.11.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jan 2026 19:11:33 -0800 (PST) From: Dmitry Baryshkov Date: Mon, 12 Jan 2026 05:11:29 +0200 Subject: [PATCH v3 1/3] drm/msm/dpu: check mode against PINGPONG or DSC max width Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260112-max-mixer-width-v3-1-f98063ea21f5@oss.qualcomm.com> References: <20260112-max-mixer-width-v3-0-f98063ea21f5@oss.qualcomm.com> In-Reply-To: <20260112-max-mixer-width-v3-0-f98063ea21f5@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jessica Zhang , Xilin Wu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6614; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=tNjh0r34a+FDv5at3WLQ8j6gBFs5H/9B9gKUXy6BkXI=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBpZGZjQ4t0vSXdcmCQmvZ8orjwRnW6KiBAGxocB lxH0XQHF0qJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaWRmYwAKCRCLPIo+Aiko 1bhHB/9ufpYx4wztso8sYPbJ5aV2yBHBJYRO+kfc8RUEiYcYnjXW581UUlT575IYxZbXE8bDojM 5PGOLun8kz9qr6axBytVKUCAr5YXoi14SVCKTc+AMWM/roDnL5010Y3bCIudvY1BOP6Nb3YzpJQ 7CLjQyhIwVIrvLOPvXDKqriE3JhWWaGa0ny0J0C/H4cELfeMzzuQkL+lKiFQXUm4o9yoTPy5kXD 5mI/CXNWzMwqTFxWDznR09w+50hL46X+kN66kHOR9XSIBVanLSzN/ZY2LEQhwQhk/B3iWDVOCOt z+VDRyp7gOwZ/wlyuMDDEU6/jLT0AUWZIquqPpFckmVP72/T X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: jFfjtmTj6ttLYfoHpVtF3IWWlKukZlnO X-Authority-Analysis: v=2.4 cv=GNMF0+NK c=1 sm=1 tr=0 ts=69646668 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=ksxQWNrZAAAA:8 a=LLqVbBr0KbdSWhQ7gwEA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 a=l7WU34MJF0Z5EO9KEJC3:22 X-Proofpoint-GUID: jFfjtmTj6ttLYfoHpVtF3IWWlKukZlnO X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTEyMDAyNCBTYWx0ZWRfX4nAoXBi47cPV 2GhhMTMzXRGJ8SCHwQ/9VlEfblPzmOygjVkfKTPaFlQJpfZylZmgtO0WleqVAhoqSZQYFlKIW8O wP5wTf5MvWZ+CG3iB7b1DFN4yEMxGn6V6WAYs+Zu9rdVfKef6fPCHFv8RBsZBdg2yTv3LEsDVux Dc6zLB+sjXPSZrnO8QCTRMODc7LzS2jSiwk9jKz8OQ6jsEcP6PSyhK51kQ/gvySblR4SrRxsnOo s8C9jwf9Z+D9iiYn3bZbzNI0ImMIaIlvr/wyDsFFSmaw2lp8HX39iQysFmG8xWUxt9z+G4QNjvD hC/OIj+fRyaL/e8OmIZHyUDHu+Lm9Fr9wWH33uZ0rTjQqmeIF199KonaogDAk9Q56elwB7LWuYD SbrIW9MXcQbevUvWg/70fKJN28kN1ylcE+zKPhCdIN21nq6C6NpGOpp1ktVI4mCTT2ZfYtZBgq2 kpxjMuOjYGo2ANLBdBw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-11_09,2026-01-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 bulkscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601120024 From: Jessica Zhang LM block doesn't have a hardware buffer (unlike PINGPONG and DSC encoders). As such, don't use ephemeral max_mixer_width and MAX_HDISPLAY_SPLIT to validate requested modes. Instead use PP and DSC buffer widths. While on the DPU 8.x+ supports a max linewidth of 8960 for PINGPONG_0, there is some additional logic that needs to be added to the resource manager to specifically try and reserve PINGPONG_0 for modes that are greater than 5k. Signed-off-by: Jessica Zhang Tested-by: Xilin Wu # qcs6490-radxa-dragon-q6a [DB: reworked to drop catalog changes, updated commit message] Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 44 ++++++++++++++++++++++= ---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 7 ++++ 2 files changed, 44 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 2d06c950e814..c0eca911ff11 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -762,6 +762,22 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc) _dpu_crtc_complete_flip(crtc); } =20 +static int msm_display_get_max_pingpong_width(struct dpu_kms *dpu_kms) +{ + /* + * Note: While, for DPU 8.x+, PINGPONG_0 can technically support up to + * 8k resolutions, this requires reworking the RM to try to reserve + * PINGPONG_0 for modes greater than 5k. + * + * Once this additional logic is implemented, we can probably drop this + * helper and use the reserved PINGPONG's max_linewidth + */ + if (dpu_kms->catalog->mdss_ver->core_major_ver < 6) + return DPU_1_x_MAX_PINGPONG_WIDTH; + else + return DPU_6_x_MAX_PINGPONG_WIDTH; +} + static int _dpu_crtc_check_and_setup_lm_bounds(struct drm_crtc *crtc, struct drm_crtc_state *state) { @@ -769,13 +785,14 @@ static int _dpu_crtc_check_and_setup_lm_bounds(struct= drm_crtc *crtc, struct drm_display_mode *adj_mode =3D &state->adjusted_mode; u32 crtc_split_width =3D adj_mode->hdisplay / cstate->num_mixers; struct dpu_kms *dpu_kms =3D _dpu_crtc_get_kms(crtc); + int max_pingpong_width =3D msm_display_get_max_pingpong_width(dpu_kms); int i; =20 /* if we cannot merge 2 LMs (no 3d mux) better to fail earlier * before even checking the width after the split */ if (!dpu_kms->catalog->caps->has_3d_merge && - adj_mode->hdisplay > dpu_kms->catalog->caps->max_mixer_width) + adj_mode->hdisplay > max_pingpong_width) return -E2BIG; =20 for (i =3D 0; i < cstate->num_mixers; i++) { @@ -787,7 +804,7 @@ static int _dpu_crtc_check_and_setup_lm_bounds(struct d= rm_crtc *crtc, =20 trace_dpu_crtc_setup_lm_bounds(DRMID(crtc), i, r); =20 - if (drm_rect_width(r) > dpu_kms->catalog->caps->max_mixer_width) + if (drm_rect_width(r) > max_pingpong_width) return -E2BIG; } =20 @@ -1318,7 +1335,6 @@ static int dpu_crtc_reassign_planes(struct drm_crtc *= crtc, struct drm_crtc_state } =20 #define MAX_CHANNELS_PER_CRTC PIPES_PER_PLANE -#define MAX_HDISPLAY_SPLIT 1080 =20 static struct msm_display_topology dpu_crtc_get_topology( struct drm_crtc *crtc, @@ -1328,12 +1344,25 @@ static struct msm_display_topology dpu_crtc_get_top= ology( struct drm_display_mode *mode =3D &crtc_state->adjusted_mode; struct msm_display_topology topology =3D {0}; struct drm_encoder *drm_enc; + u32 max_hdisplay_split; =20 drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask) dpu_encoder_update_topology(drm_enc, &topology, crtc_state->state, &crtc_state->adjusted_mode); =20 topology.cwb_enabled =3D drm_crtc_in_clone_mode(crtc_state); + max_hdisplay_split =3D msm_display_get_max_pingpong_width(dpu_kms); + + if (topology.num_dsc > 0) { + u32 max_dsc_encoder_width; + + if (dpu_kms->catalog->mdss_ver->core_major_ver < 6) + max_dsc_encoder_width =3D DPU_1_x_MAX_DSC_ENCODER_WIDTH; + else + max_dsc_encoder_width =3D DPU_8_x_MAX_DSC_ENCODER_WIDTH; + + max_hdisplay_split =3D min(max_hdisplay_split, max_dsc_encoder_width); + } =20 /* * Datapath topology selection @@ -1354,7 +1383,7 @@ static struct msm_display_topology dpu_crtc_get_topol= ogy( * count both the WB and real-time phys encoders. * * For non-DSC CWB usecases, have the num_lm be decided by the - * (mode->hdisplay > MAX_HDISPLAY_SPLIT) check. + * (mode->hdisplay > max_hdisplay_split) check. */ =20 if (topology.num_intf =3D=3D 2 && !topology.cwb_enabled) @@ -1362,7 +1391,7 @@ static struct msm_display_topology dpu_crtc_get_topol= ogy( else if (topology.num_dsc =3D=3D 2) topology.num_lm =3D 2; else if (dpu_kms->catalog->caps->has_3d_merge) - topology.num_lm =3D (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; + topology.num_lm =3D (mode->hdisplay > max_hdisplay_split) ? 2 : 1; else topology.num_lm =3D 1; =20 @@ -1540,13 +1569,14 @@ static enum drm_mode_status dpu_crtc_mode_valid(str= uct drm_crtc *crtc, const struct drm_display_mode *mode) { struct dpu_kms *dpu_kms =3D _dpu_crtc_get_kms(crtc); + int max_pingpong_width =3D msm_display_get_max_pingpong_width(dpu_kms); u64 adjusted_mode_clk; =20 /* if there is no 3d_mux block we cannot merge LMs so we cannot * split the large layer into 2 LMs, filter out such modes */ if (!dpu_kms->catalog->caps->has_3d_merge && - mode->hdisplay > dpu_kms->catalog->caps->max_mixer_width) + mode->hdisplay > max_pingpong_width) return MODE_BAD_HVALUE; =20 adjusted_mode_clk =3D dpu_core_perf_adjusted_mode_clk(mode->clock, @@ -1566,7 +1596,7 @@ static enum drm_mode_status dpu_crtc_mode_valid(struc= t drm_crtc *crtc, * max crtc width is equal to the max mixer width * 2 and max height is 4K */ return drm_mode_validate_size(mode, - 2 * dpu_kms->catalog->caps->max_mixer_width, + 2 * max_pingpong_width, 4096); } =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 4964e70610d1..3d979e856b7c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -24,6 +24,13 @@ #define DPU_MAX_IMG_WIDTH 0x3fff #define DPU_MAX_IMG_HEIGHT 0x3fff =20 +#define DPU_1_x_MAX_PINGPONG_WIDTH 4096 +#define DPU_6_x_MAX_PINGPONG_WIDTH 5120 +#define DPU_8_x_MAX_PINGPONG_0_WIDTH 8960 + +#define DPU_1_x_MAX_DSC_ENCODER_WIDTH 2048 +#define DPU_8_x_MAX_DSC_ENCODER_WIDTH 2560 + #define CRTC_DUAL_MIXERS 2 =20 #define MAX_XIN_COUNT 16 --=20 2.47.3 From nobody Sat Feb 7 09:30:03 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 283B425524C for ; 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Use the actual hardware limit (the writeback maxlinewidth) to filter modes. Signed-off-by: Jessica Zhang [DB: fixed commit message] Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c b/drivers/gpu/dr= m/msm/disp/dpu1/dpu_writeback.c index 7545c0293efb..209b1e27a84b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c @@ -14,14 +14,7 @@ static int dpu_wb_conn_get_modes(struct drm_connector *c= onnector) struct msm_drm_private *priv =3D dev->dev_private; struct dpu_kms *dpu_kms =3D to_dpu_kms(priv->kms); =20 - /* - * We should ideally be limiting the modes only to the maxlinewidth but - * on some chipsets this will allow even 4k modes to be added which will - * fail the per SSPP bandwidth checks. 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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-59b792cf330sm2758871e87.102.2026.01.11.19.11.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jan 2026 19:11:41 -0800 (PST) From: Dmitry Baryshkov Date: Mon, 12 Jan 2026 05:11:31 +0200 Subject: [PATCH v3 3/3] drm/msm/dpu: remove max_mixer_width from catalog Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260112-max-mixer-width-v3-3-f98063ea21f5@oss.qualcomm.com> References: <20260112-max-mixer-width-v3-0-f98063ea21f5@oss.qualcomm.com> In-Reply-To: <20260112-max-mixer-width-v3-0-f98063ea21f5@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jessica Zhang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=19211; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=OeIeX85m68KtKpaL4CxfY88JJs2W1shJKLbOI0vfmPo=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBpZGZjMMaIjKXPKvc1XHS1pulHpq31TrGuPxNCW 2eI+YwwaEiJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaWRmYwAKCRCLPIo+Aiko 1SAeB/4kF0tZOVzq1CgHJtcBno5YSpf8Gx3uDQa4t8w7Bo2a8WHb0P7niAKTI2mZMnocfHyB5J2 h//O5OICEEwR6oEgm3RhxVVwBmbgB2tZcpmaf2q/GUYBIbgelyqRoq2KOVgULH2DvvphkFHQdeh qpKd1e/9/okApma+F05oABLLYCn7qj6kpDf+uxkuUebkestxwY4eTXrhSJfzlUSABg/OMj81iii StYAHc4Hy6Xzvb5LnJbRxfO+G4ryEFg+bx8LqpcY8lENw8w2VfIVvgMiRJMia98ZlVptmxMgW6T g4CgSbW/O+PR3mSFmRdEvL9AGa5a0JW1J7v7n8yR2Y1hkwUJ X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: lSINXF-z-k90KUcbi9iSQOos9S0ujPfU X-Proofpoint-ORIG-GUID: lSINXF-z-k90KUcbi9iSQOos9S0ujPfU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTEyMDAyNCBTYWx0ZWRfX0gytlHUwR5e/ XZmoLmQ9F8Cce4uumD+11YHiGizkBTWOgdRjmPegfgYJ9nI8UrxlgarsueiCrSRaipJlfuzBv0S gI4iwandcl7hujhNZxuDX8G2qUL+r1g6YdY7oBtnLvnfCp2bimfk3dEJCY4BSclkng1OauOrZco 1XKb+fna0Z/41S/WIGu5jRuFRgGu7l3i1/s8YjrQWIRdfAedLLjZnA1xqTTtG8UJY2eU9GHIu1B Dg3UmHmerBIh7TGQtLaLFg9Asx0gijMGMN/85UW8IGYfB7seAVSxX8UzaRZRGFuLKk0hxVPlW97 mkpLpHNFSOXwG9qqfpXULR/ktkcMtUZzCVvuSz6zJ3/wH3W4H5fQ1+SZB2oO473Lsv36aag68+9 CT24QXO+bgEGj682qN1KxDg+5TO2u5rmgGOuXuZZ+z6Vj7HT/1ZKWG8hTzAii1w6DhgbWWLdkpT 6rPYEJFAqLuck3xqzOg== X-Authority-Analysis: v=2.4 cv=Dckaa/tW c=1 sm=1 tr=0 ts=6964666f cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=XwF-NPJyeaUn0DJ09rAA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-11_09,2026-01-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 bulkscore=0 impostorscore=0 spamscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601120024 From: Jessica Zhang Remove the now-unused max_mixer_width field from the HW catalog. It doesn't represent an actual hardware constraint. Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- 31 files changed, 32 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index 56d3c38c8778..18866ca279df 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -8,7 +8,6 @@ #define _DPU_10_0_SM8650_H =20 static const struct dpu_caps sm8650_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0xb, .has_src_split =3D true, .has_dim_layer =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h index db8cc2d0112c..13cc84b28058 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h @@ -9,7 +9,6 @@ #define _DPU_12_0_SM8750_H =20 static const struct dpu_caps sm8750_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0xb, .has_src_split =3D true, .has_dim_layer =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h index 13bb43ba67d3..59a4859ce67a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h @@ -7,7 +7,6 @@ #define _DPU_12_2_GLYMUR_H =20 static const struct dpu_caps glymur_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0xb, .has_src_split =3D true, .has_dim_layer =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h index 29e0eba91930..c6923e0093cd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h @@ -7,7 +7,6 @@ #define _DPU_1_14_MSM8937_H =20 static const struct dpu_caps msm8937_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages =3D 0x4, .max_linewidth =3D DEFAULT_DPU_LINE_WIDTH, .pixel_ram_size =3D 40 * 1024, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h index cb1ee4b63f9f..14d0619c1479 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h @@ -7,7 +7,6 @@ #define _DPU_1_14_MSM8917_H =20 static const struct dpu_caps msm8917_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages =3D 0x4, .max_linewidth =3D DEFAULT_DPU_LINE_WIDTH, .pixel_ram_size =3D 16 * 1024, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h index b44d02b48418..17f6d1ee90aa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h @@ -7,7 +7,6 @@ #define _DPU_1_16_MSM8953_H =20 static const struct dpu_caps msm8953_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages =3D 0x4, .max_linewidth =3D DEFAULT_DPU_LINE_WIDTH, .pixel_ram_size =3D 40 * 1024, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h index 8af63db315b4..1885ea92a808 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h @@ -9,7 +9,6 @@ #define _DPU_1_7_MSM8996_H =20 static const struct dpu_caps msm8996_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0x7, .has_src_split =3D true, .max_linewidth =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index f91220496082..3fafb10661cf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -8,7 +8,6 @@ #define _DPU_3_0_MSM8998_H =20 static const struct dpu_caps msm8998_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0x7, .has_src_split =3D true, .has_dim_layer =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h index 8f9a097147c0..b2bd87f4af43 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h @@ -7,7 +7,6 @@ #define _DPU_3_2_SDM660_H =20 static const struct dpu_caps sdm660_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0x7, .has_src_split =3D true, .has_dim_layer =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h index 0ad18bd273ff..e4304ace8eb9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h @@ -7,7 +7,6 @@ #define _DPU_3_3_SDM630_H =20 static const struct dpu_caps sdm630_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages =3D 0x7, .has_src_split =3D true, .has_dim_layer =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 5cc9f55d542b..ee3b78ce6bd1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -8,7 +8,6 @@ #define _DPU_4_0_SDM845_H =20 static const struct dpu_caps sdm845_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0xb, .has_src_split =3D true, .has_dim_layer =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index ae1b2ed96e9f..02621def12b2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -8,7 +8,6 @@ #define _DPU_5_0_SM8150_H =20 static const struct dpu_caps sm8150_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0xb, .has_src_split =3D true, .has_dim_layer =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index b572cfa7ed35..04afc22d9fad 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -8,7 +8,6 @@ #define _DPU_5_1_SC8180X_H =20 static const struct dpu_caps sc8180x_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0xb, .has_src_split =3D true, .has_dim_layer =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h index a56c288ac10c..371fcb7f7bef 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h @@ -8,7 +8,6 @@ #define _DPU_5_2_SM7150_H =20 static const struct dpu_caps sm7150_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0xb, .has_src_split =3D true, .has_dim_layer =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h index 26883f6b66b3..a5a3944a5601 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h @@ -7,7 +7,6 @@ #define _DPU_5_3_SM6150_H =20 static const struct dpu_caps sm6150_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0x9, .has_dim_layer =3D true, .has_idle_pc =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h index fbf50f279e66..42d6d1a6cce4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h @@ -9,7 +9,6 @@ #define _DPU_5_4_SM6125_H =20 static const struct dpu_caps sm6125_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0x6, .has_dim_layer =3D true, .has_idle_pc =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 7b8b7a1c2d76..d39ca9b287d4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -8,7 +8,6 @@ #define _DPU_6_0_SM8250_H =20 static const struct dpu_caps sm8250_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0xb, .has_src_split =3D true, .has_dim_layer =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index c990ba3b5db0..afe83f5e4349 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -8,7 +8,6 @@ #define _DPU_6_2_SC7180_H =20 static const struct dpu_caps sc7180_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0x9, .has_dim_layer =3D true, .has_idle_pc =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index 343ff5482382..90d696707227 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -8,7 +8,6 @@ #define _DPU_6_3_SM6115_H =20 static const struct dpu_caps sm6115_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages =3D 0x4, .has_dim_layer =3D true, .has_idle_pc =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index 093d16bdc450..d7a94b7c69f1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -9,7 +9,6 @@ #define _DPU_6_4_SM6350_H =20 static const struct dpu_caps sm6350_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0x7, .has_src_split =3D true, .has_dim_layer =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index 47053bf9b0a2..fadbfd4f9f95 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -8,7 +8,6 @@ #define _DPU_6_5_QCM2290_H =20 static const struct dpu_caps qcm2290_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages =3D 0x4, .has_dim_layer =3D true, .has_idle_pc =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index 98190ee7ec7a..9427ec024d60 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -9,7 +9,6 @@ #define _DPU_6_9_SM6375_H =20 static const struct dpu_caps sm6375_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages =3D 0x4, .has_dim_layer =3D true, .has_idle_pc =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 85aae40c210f..5fe2673fa8d3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -8,7 +8,6 @@ #define _DPU_7_0_SM8350_H =20 static const struct dpu_caps sm8350_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0xb, .has_src_split =3D true, .has_dim_layer =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 2f8688224f34..223ba5b0e8b3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -8,7 +8,6 @@ #define _DPU_7_2_SC7280_H =20 static const struct dpu_caps sc7280_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0x7, .has_dim_layer =3D true, .has_idle_pc =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 303d33dc7783..37a539a195df 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -8,7 +8,6 @@ #define _DPU_8_0_SC8280XP_H =20 static const struct dpu_caps sc8280xp_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 11, .has_src_split =3D true, .has_dim_layer =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index b09a6af4c474..bda58b5c48df 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -8,7 +8,6 @@ #define _DPU_8_1_SM8450_H =20 static const struct dpu_caps sm8450_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0xb, .has_src_split =3D true, .has_dim_layer =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index 0f7b4a224e4c..c5affbb42ecb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -7,7 +7,6 @@ #define _DPU_8_4_SA8775P_H =20 static const struct dpu_caps sa8775p_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0xb, .has_src_split =3D true, .has_dim_layer =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 465b6460f875..a34d85a82e99 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -8,7 +8,6 @@ #define _DPU_9_0_SM8550_H =20 static const struct dpu_caps sm8550_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0xb, .has_src_split =3D true, .has_dim_layer =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h index 6caa7d40f368..21e40f098d6e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h @@ -8,7 +8,6 @@ #define _DPU_9_1_SAR2130P_H =20 static const struct dpu_caps sar2130p_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0xb, .has_src_split =3D true, .has_dim_layer =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index 7243eebb85f3..6906fb060c19 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -7,7 +7,6 @@ #define _DPU_9_2_X1E80100_H =20 static const struct dpu_caps x1e80100_dpu_caps =3D { - .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0xb, .has_src_split =3D true, .has_dim_layer =3D true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 3d979e856b7c..c959d59ac129 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -259,7 +259,6 @@ struct dpu_rotation_cfg { =20 /** * struct dpu_caps - define DPU capabilities - * @max_mixer_width max layer mixer line width support. * @max_mixer_blendstages max layer mixer blend stages or * supported z order * @has_src_split source split feature status @@ -272,7 +271,6 @@ struct dpu_rotation_cfg { * @max_vdeci_exp max vertical decimation supported (max is 2^value) */ struct dpu_caps { - u32 max_mixer_width; u32 max_mixer_blendstages; bool has_src_split; bool has_dim_layer; --=20 2.47.3