From nobody Mon Feb 9 16:53:19 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 807D830BF60 for ; Mon, 12 Jan 2026 09:02:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768208563; cv=none; b=YM7kKRzD6VC0UPH/b4cLQP1yrImZLmleyPp76ZmlGKIHTStpAzOTZ9DM8hfwM5AqGyRk5TLQNZgK7hLWxfRU2gXTQS7glLfZvYKSzzuWboiiCsf3Kt5rkE73voi/ZHvmbtEM+94PWsegTH1Jdswg1Y93QQq53Uy8xN3jKzR5pa0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768208563; c=relaxed/simple; bh=3vqQq2w28MIgXEnXZqusZI+1YcBuCkY93K3m3bB0xrA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NYwE4T2mWkAEJl/hrcf/ili6jlc6k3Qx8tIjGsro6D7WqdOPSdNqELuF5Fwj3nPH7LZZbnl+8RQ6HEhFn9d/F3f0MCITR/rPQHyZrejUop77d6lWsczJY8EPx/tWD0hV18TYMqaiLmSkerZSKh78vn7C3GgmOWSSyyyZDmJK3sM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=NAiBf9Xb; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=NkUSigHg; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="NAiBf9Xb"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="NkUSigHg" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 60C85W1W3967618 for ; Mon, 12 Jan 2026 09:02:40 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 1+vQ93PIsR1eb2AEe4cTvxYcAMBeLMJBPOKXVVklj8w=; b=NAiBf9Xb73rQ3ZCw bwyQbp4FHTQDK3BGQqgajvkuDH8sCoNrSdqnTccE44W4gpg9bZZ950KsUlU1tCpF 976p/i4j7TA1W00sILLn40frMWF2zrz2o4KwGv02o9YMbZXv0aNaNqXaKFIXKFB+ uAiPp9xMjW3i8z0JPIY6CmQe6hzu15thPT6pjpZxazN5X1PycTfjggN05pLuUW+i wDlOO7EfvYSVt0NkcGu3B4zvCiffxv5F6F/PYtfRSnQwqF2R1sQUS/ZHxVLDgFBX QuPFeuz0ULyhGcKl7aD/77rdTDoVfbQFAief6C/pJKa2PiJ4y0dlHOR7Gf4GHGux ZXHHvw== Received: from mail-dl1-f72.google.com (mail-dl1-f72.google.com [74.125.82.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bkfham949-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 12 Jan 2026 09:02:40 +0000 (GMT) Received: by mail-dl1-f72.google.com with SMTP id a92af1059eb24-11dd10b03c6so8876473c88.0 for ; Mon, 12 Jan 2026 01:02:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1768208560; x=1768813360; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=1+vQ93PIsR1eb2AEe4cTvxYcAMBeLMJBPOKXVVklj8w=; b=NkUSigHg1ZnkvYcsKgHL8PF67U3EZbcSp0+HZX4QbNrZB/FNWaHMMFpsRFSJVBj4WX g2T18GT1qDPp9AJeEiyEpBjTczgO+i8fRYrCHRAJp2HfxfFv92tdbkDXuJhw6YAgsWcP gG6lf6AVTOTGmkLd7zscGhDguh83vkNoO4536XmuuSNBO7ZwAxXTvu9Vu4J9c0J1HM1t 75H+50hOva4TR6arwiwlWwhmb4BjGD8XwUq6Fxj4xTamBGsCY/Gn+064kLaX3XGynEzo fCmh7omBRZ/yZYoKstdBxAYU6t38A/moXSA005JZadP4/brceAfhkRWbDNE395O9giRT P5MA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768208560; x=1768813360; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=1+vQ93PIsR1eb2AEe4cTvxYcAMBeLMJBPOKXVVklj8w=; b=OWsPdQQYBUTR1IDUH8LGaekrepGMX2eQkDjRTC7DFqehJQ1C7IFUo1fGmEmsSWbzS8 iZni4oTcVnFhQFon2PkB2wepJ082WIPkuRHrjQJ8CB16mOEdG7ZnN0WarG7Xq++Tn4Ty QURvkmP6MoLkHAFecXXFgdkDvzQOE9KmSD6KjeD2A2fLQBuWalt0naMJWpdKfkbYg+kd KMw42p64AlOVcUOZGPfV5mFdWhHS6pTAlr/NcnhUAiM+5ABQf1ndIIhalatHAjXs7wNS pCEvdg8xB0GEDnfefv5Nsg7Az9Bw6FENCWpq++oodDjLwGTVdGB33hytKWZnEwmO+5ho pw0Q== X-Forwarded-Encrypted: i=1; AJvYcCWqbQbSFbKsk3tQaXk5Zx0Y8WII70U3MnPfe5IsGmrEnSLSKUNPnPkc98QSg/wsYaWI7AszDlGwHt1drBc=@vger.kernel.org X-Gm-Message-State: AOJu0Yzh/vg1sEuuGPWGm0vAWWQDgXgKZZIzoyrcN/PCcTnoUHoGrv6w q9vipq/qHzIwRZoeXck57WPWzYE15OhxPGwqXg1LmAP0A9XEgWGfePDz5fshnpMSoLQ/7wb+D+L 9C71rCbYBfzK/7OB08F/ZpUUMzbWRuSFm77hXQnE+fs4wTvIG0glRQxYZ74NR2ZKYr70= X-Gm-Gg: AY/fxX6pe8jJmPxWneyIdCYWqOCfwFJUa8nh1n//aJRhQkzG548QiWkQ9em4Rc+Puee Kfp+YBOCiR3jh9G/dUHR8TYSa5OdLRrtfkgGLYw+PCZXVChtS0+Kx7P5VbE7OBhcelwNNWprwzH wtqtdBMmsk0PdZKnTdQB/TK4yE1M2huENL4iSTNxRXHz3j6r0/EO51C0YjbolNIciJ+WlBFzup+ DxZwYnxNaNWs6sInIpjoK4ftdoKLnTCq6Tm58taRZn8k3HTpqnstPliw2aMIF/KyE3BSKwQS94Y Ow8YwqdpqzGMqwhX0Du/1d/7JJDlvtWScj0C49MY9vKz2LHH++mLgUbLICPncqTt1iMMOeON9Ax dA9oONp1HpnCncYH3APoa9AmXrlzTU6KtthJZwBy9bbeff4R9GiZK0E2tGgAp7ciW X-Received: by 2002:a05:7022:511:b0:11b:9386:8265 with SMTP id a92af1059eb24-121f8b8e182mr17149614c88.42.1768208559597; Mon, 12 Jan 2026 01:02:39 -0800 (PST) X-Google-Smtp-Source: AGHT+IFSq5HnIotYSHU7gtYklM8jwrp+KvMU7vL1ZFwPVhWN7bBucJ3TauHO5N7MB658kLu85MHQtA== X-Received: by 2002:a05:7022:511:b0:11b:9386:8265 with SMTP id a92af1059eb24-121f8b8e182mr17149602c88.42.1768208558861; Mon, 12 Jan 2026 01:02:38 -0800 (PST) Received: from hu-hangxian-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-121f23b798asm18888500c88.0.2026.01.12.01.02.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jan 2026 01:02:38 -0800 (PST) From: Hangxiang Ma Date: Mon, 12 Jan 2026 01:02:26 -0800 Subject: [PATCH v11 1/5] media: dt-bindings: Add CAMSS device for Kaanapali Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260112-kaanapali-camss-v11-1-81e4f59a5d08@oss.qualcomm.com> References: <20260112-kaanapali-camss-v11-0-81e4f59a5d08@oss.qualcomm.com> In-Reply-To: <20260112-kaanapali-camss-v11-0-81e4f59a5d08@oss.qualcomm.com> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hangxiang Ma , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Proofpoint-ORIG-GUID: oC6XoI-z7w3jj6i1nbpXg7arLwfg7Xy3 X-Authority-Analysis: v=2.4 cv=bOEb4f+Z c=1 sm=1 tr=0 ts=6964b8b0 cx=c_pps a=bS7HVuBVfinNPG3f6cIo3Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gEfo2CItAAAA:8 a=KKAkSRfTAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=78032wgmgAfrEkmTq9UA:9 a=QEXdDO2ut3YA:10 a=vBUdepa8ALXHeOFLBtFW:22 a=sptkURWiP4Gy88Gu7hUp:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: oC6XoI-z7w3jj6i1nbpXg7arLwfg7Xy3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTEyMDA3MCBTYWx0ZWRfX+bNwWBjne/Ex hswVN5KWTBpbwvjH1wN5XR+9r5sY8B43MZt51ZfakfQDJPabExB9vYN5v34H1q9jzw8vl0l2K52 F9TurnDm3JRVj4xl5Vh6gbOxwxxxNx1wJIcqnCQ8mM/o0+Lqh5/lxv/m2r8bbJIcN6gubXg1IXx jrtB3+d2qfLZOU5R5KVpoq/uxiCcuegw31YxMP3EnalXudJ3rSDMb+iAquoP+2F09urVe8/RT/N FVz0hKe6pvXRcP6L26iJJvxtqZGJin00P//8tHf/Sm3M4Wek9Bo0aZrXY5l6MN/ahBxyVFfWt3x Yv014MsBnlaZdP9nr1AJZyEK8zdXVYdWJUNORhZY0rDNgUON52wvUzbhRLZOQp+UhpqOVcRDhxJ NVguWK5Kl54GKXjVAWYWr5dpU1koiUTTSouY5cCeITz0R0X25rSOKWUGxpazpkM5lbv4jyCY2Fb hgw1eVyRf9ln2/P8h9g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-12_02,2026-01-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 impostorscore=0 adultscore=0 suspectscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601120070 Add bindings for Camera Subsystem (CAMSS) on the Qualcomm Kaanapali platform. The Kaanapali platform provides: - 3 x VFE (Video Front End), 5 RDI per VFE - 2 x VFE Lite, 4 RDI per VFE Lite - 3 x CSID (CSI Decoder) - 2 x CSID Lite - 6 x CSIPHY (CSI Physical Layer) - 2 x ICP (Image Control Processor) - 1 x IPE (Image Processing Engine) - 2 x JPEG DMA & Downscaler - 2 x JPEG Encoder - 1 x OFE (Offline Front End) - 5 x RT CDM (Camera Data Mover) - 3 x TPG (Test Pattern Generator) Reviewed-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski Signed-off-by: Hangxiang Ma --- .../bindings/media/qcom,kaanapali-camss.yaml | 646 +++++++++++++++++= ++++ 1 file changed, 646 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.y= aml b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml new file mode 100644 index 000000000000..7108a4f12f58 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml @@ -0,0 +1,646 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,kaanapali-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Kaanapali Camera Subsystem (CAMSS) + +maintainers: + - Hangxiang Ma + +description: + Kaanapali camera subsystem includes submodules such as CSIPHY (CSI Physi= cal Layer) + and CSID (CSI Decoder), which comply with the MIPI CSI2 protocol. + + The subsystem also integrates a set of real-time image processing engine= s and + their associated configuration modules, as well as non-real-time engines. + + Additionally, it encompasses a test pattern generator (TPG) submodule. + +properties: + compatible: + const: qcom,kaanapali-camss + + reg: + items: + - description: Registers for CSID 0 + - description: Registers for CSID 1 + - description: Registers for CSID 2 + - description: Registers for CSID Lite 0 + - description: Registers for CSID Lite 1 + - description: Registers for CSIPHY 0 + - description: Registers for CSIPHY 1 + - description: Registers for CSIPHY 2 + - description: Registers for CSIPHY 3 + - description: Registers for CSIPHY 4 + - description: Registers for CSIPHY 5 + - description: Registers for VFE (Video Front End) 0 + - description: Registers for VFE 1 + - description: Registers for VFE 2 + - description: Registers for VFE Lite 0 + - description: Registers for VFE Lite 1 + - description: Registers for ICP (Imaging Control Processor) 0 + - description: Registers for ICP 0 SYS + - description: Registers for ICP 1 + - description: Registers for ICP 1 SYS + - description: Registers for IPE (Image Processing Engine) + - description: Registers for JPEG DMA & Downscaler + - description: Registers for JPEG Encoder + - description: Registers for OFE (Offline Front End) + - description: Registers for RT CDM (Camera Data Mover) 0 + - description: Registers for RT CDM 1 + - description: Registers for RT CDM 2 + - description: Registers for RT CDM 3 + - description: Registers for RT CDM 4 + - description: Registers for TPG 0 + - description: Registers for TPG 1 + - description: Registers for TPG 2 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + - const: icp0 + - const: icp0_sys + - const: icp1 + - const: icp1_sys + - const: ipe + - const: jpeg_dma + - const: jpeg_enc + - const: ofe + - const: rt_cdm0 + - const: rt_cdm1 + - const: rt_cdm2 + - const: rt_cdm3 + - const: rt_cdm4 + - const: tpg0 + - const: tpg1 + - const: tpg2 + + clocks: + maxItems: 60 + + clock-names: + items: + - const: camnoc_nrt_axi + - const: camnoc_rt_axi + - const: camnoc_rt_vfe0 + - const: camnoc_rt_vfe1 + - const: camnoc_rt_vfe2 + - const: camnoc_rt_vfe_lite + - const: cpas_ahb + - const: cpas_fast_ahb + - const: csid + - const: csid_csiphy_rx + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: csiphy4 + - const: csiphy4_timer + - const: csiphy5 + - const: csiphy5_timer + - const: gcc_axi_hf + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe2 + - const: vfe2_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + - const: qdss_debug_xo + - const: camnoc_ipe_nps + - const: camnoc_ofe + - const: gcc_axi_sf + - const: icp0 + - const: icp0_ahb + - const: icp1 + - const: icp1_ahb + - const: ipe_nps + - const: ipe_nps_ahb + - const: ipe_nps_fast_ahb + - const: ipe_pps + - const: ipe_pps_fast_ahb + - const: jpeg + - const: ofe_ahb + - const: ofe_anchor + - const: ofe_anchor_fast_ahb + - const: ofe_hdr + - const: ofe_hdr_fast_ahb + - const: ofe_main + - const: ofe_main_fast_ahb + - const: vfe0_bayer + - const: vfe0_bayer_fast_ahb + - const: vfe1_bayer + - const: vfe1_bayer_fast_ahb + - const: vfe2_bayer + - const: vfe2_bayer_fast_ahb + + interrupts: + maxItems: 30 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + - const: camnoc_nrt + - const: camnoc_rt + - const: icp0 + - const: icp1 + - const: jpeg_dma + - const: jpeg_enc + - const: rt_cdm0 + - const: rt_cdm1 + - const: rt_cdm2 + - const: rt_cdm3 + - const: rt_cdm4 + - const: tpg0 + - const: tpg1 + - const: tpg2 + + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: cam_ahb + - const: cam_hf_mnoc + - const: cam_sf_icp_mnoc + - const: cam_sf_mnoc + + iommus: + items: + - description: VFE non-protected stream + - description: ICP0 shared stream + - description: ICP1 shared stream + - description: IPE CDM non-protected stream + - description: IPE non-protected stream + - description: JPEG non-protected stream + - description: OFE CDM non-protected stream + - description: OFE non-protected stream + - description: VFE / VFE Lite CDM non-protected stream + + power-domains: + items: + - description: + IFE0 GDSC - Global Distributed Switch Controller for IFE0. + - description: + IFE1 GDSC - Global Distributed Switch Controller for IFE1. + - description: + IFE2 GDSC - Global Distributed Switch Controller for IFE2. + - description: + Titan GDSC - Global Distributed Switch Controller for the entire= camss. + - description: + IPE GDSC - Global Distributed Switch Controller for IPE. + - description: + OFE GDSC - Block Global Distributed Switch Controller for OFE. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: ife2 + - const: top + - const: ipe + - const: ofe + + vdd-csiphy0-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY0 core block. + + vdd-csiphy0-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY0 pll block. + + vdd-csiphy1-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY1 core block. + + vdd-csiphy1-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY1 pll block. + + vdd-csiphy2-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY2 core block. + + vdd-csiphy2-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY2 pll block. + + vdd-csiphy3-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY3 core block. + + vdd-csiphy3-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY3 pll block. + + vdd-csiphy4-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY4 core block. + + vdd-csiphy4-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY4 pll block. + + vdd-csiphy5-0p8-supply: + description: + Phandle to a 0.8V regulator supply to CSIPHY5 core block. + + vdd-csiphy5-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSIPHY5 pll block. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + +patternProperties: + "^port@[0-5]$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input ports for receiving CSI data on CSIPHY 0-5. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + isp@9253000 { + compatible =3D "qcom,kaanapali-camss"; + + reg =3D <0x0 0x09253000 0x0 0x5e80>, + <0x0 0x09263000 0x0 0x5e80>, + <0x0 0x09273000 0x0 0x5e80>, + <0x0 0x092d3000 0x0 0x3880>, + <0x0 0x092e7000 0x0 0x3880>, + <0x0 0x09523000 0x0 0x2000>, + <0x0 0x09525000 0x0 0x2000>, + <0x0 0x09527000 0x0 0x2000>, + <0x0 0x09529000 0x0 0x2000>, + <0x0 0x0952b000 0x0 0x2000>, + <0x0 0x0952d000 0x0 0x2000>, + <0x0 0x09151000 0x0 0x20000>, + <0x0 0x09171000 0x0 0x20000>, + <0x0 0x09191000 0x0 0x20000>, + <0x0 0x092dc000 0x0 0x1300>, + <0x0 0x092f0000 0x0 0x1300>, + <0x0 0x0900e000 0x0 0x1000>, + <0x0 0x0900d000 0x0 0x1000>, + <0x0 0x0902e000 0x0 0x1000>, + <0x0 0x0902d000 0x0 0x1000>, + <0x0 0x090d7000 0x0 0x20000>, + <0x0 0x0904e000 0x0 0x1000>, + <0x0 0x0904d000 0x0 0x1000>, + <0x0 0x09057000 0x0 0x40000>, + <0x0 0x09147000 0x0 0x580>, + <0x0 0x09148000 0x0 0x580>, + <0x0 0x09149000 0x0 0x580>, + <0x0 0x0914a000 0x0 0x580>, + <0x0 0x0914b000 0x0 0x580>, + <0x0 0x093fd000 0x0 0x400>, + <0x0 0x093fe000 0x0 0x400>, + <0x0 0x093ff000 0x0 0x400>; + reg-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1", + "icp0", + "icp0_sys", + "icp1", + "icp1_sys", + "ipe", + "jpeg_dma", + "jpeg_enc", + "ofe", + "rt_cdm0", + "rt_cdm1", + "rt_cdm2", + "rt_cdm3", + "rt_cdm4", + "tpg0", + "tpg1", + "tpg2"; + + clocks =3D <&camcc_cam_cc_camnoc_nrt_axi_clk>, + <&camcc_cam_cc_camnoc_rt_axi_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_0_main_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_1_main_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_2_main_clk>, + <&camcc_cam_cc_camnoc_rt_vfe_lite_clk>, + <&camcc_cam_cc_cam_top_ahb_clk>, + <&camcc_cam_cc_cam_top_fast_ahb_clk>, + <&camcc_cam_cc_csid_clk>, + <&camcc_cam_cc_csid_csiphy_rx_clk>, + <&camcc_cam_cc_csiphy0_clk>, + <&camcc_cam_cc_csi0phytimer_clk>, + <&camcc_cam_cc_csiphy1_clk>, + <&camcc_cam_cc_csi1phytimer_clk>, + <&camcc_cam_cc_csiphy2_clk>, + <&camcc_cam_cc_csi2phytimer_clk>, + <&camcc_cam_cc_csiphy3_clk>, + <&camcc_cam_cc_csi3phytimer_clk>, + <&camcc_cam_cc_csiphy4_clk>, + <&camcc_cam_cc_csi4phytimer_clk>, + <&camcc_cam_cc_csiphy5_clk>, + <&camcc_cam_cc_csi5phytimer_clk>, + <&gcc_gcc_camera_hf_axi_clk>, + <&camcc_cam_cc_vfe_0_main_clk>, + <&camcc_cam_cc_vfe_0_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_1_main_clk>, + <&camcc_cam_cc_vfe_1_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_2_main_clk>, + <&camcc_cam_cc_vfe_2_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_lite_clk>, + <&camcc_cam_cc_vfe_lite_ahb_clk>, + <&camcc_cam_cc_vfe_lite_cphy_rx_clk>, + <&camcc_cam_cc_vfe_lite_csid_clk>, + <&camcc_cam_cc_qdss_debug_xo_clk>, + <&camcc_cam_cc_camnoc_nrt_ipe_nps_clk>, + <&camcc_cam_cc_camnoc_nrt_ofe_main_clk>, + <&gcc_gcc_camera_sf_axi_clk>, + <&camcc_cam_cc_icp_0_clk>, + <&camcc_cam_cc_icp_0_ahb_clk>, + <&camcc_cam_cc_icp_1_clk>, + <&camcc_cam_cc_icp_1_ahb_clk>, + <&camcc_cam_cc_ipe_nps_clk>, + <&camcc_cam_cc_ipe_nps_ahb_clk>, + <&camcc_cam_cc_ipe_nps_fast_ahb_clk>, + <&camcc_cam_cc_ipe_pps_clk>, + <&camcc_cam_cc_ipe_pps_fast_ahb_clk>, + <&camcc_cam_cc_jpeg_clk>, + <&camcc_cam_cc_ofe_ahb_clk>, + <&camcc_cam_cc_ofe_anchor_clk>, + <&camcc_cam_cc_ofe_anchor_fast_ahb_clk>, + <&camcc_cam_cc_ofe_hdr_clk>, + <&camcc_cam_cc_ofe_hdr_fast_ahb_clk>, + <&camcc_cam_cc_ofe_main_clk>, + <&camcc_cam_cc_ofe_main_fast_ahb_clk>, + <&camcc_cam_cc_vfe_0_bayer_clk>, + <&camcc_cam_cc_vfe_0_bayer_fast_ahb_clk>, + <&camcc_cam_cc_vfe_1_bayer_clk>, + <&camcc_cam_cc_vfe_1_bayer_fast_ahb_clk>, + <&camcc_cam_cc_vfe_2_bayer_clk>, + <&camcc_cam_cc_vfe_2_bayer_fast_ahb_clk>; + clock-names =3D "camnoc_nrt_axi", + "camnoc_rt_axi", + "camnoc_rt_vfe0", + "camnoc_rt_vfe1", + "camnoc_rt_vfe2", + "camnoc_rt_vfe_lite", + "cpas_ahb", + "cpas_fast_ahb", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "gcc_axi_hf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe2", + "vfe2_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid", + "qdss_debug_xo", + "camnoc_ipe_nps", + "camnoc_ofe", + "gcc_axi_sf", + "icp0", + "icp0_ahb", + "icp1", + "icp1_ahb", + "ipe_nps", + "ipe_nps_ahb", + "ipe_nps_fast_ahb", + "ipe_pps", + "ipe_pps_fast_ahb", + "jpeg", + "ofe_ahb", + "ofe_anchor", + "ofe_anchor_fast_ahb", + "ofe_hdr", + "ofe_hdr_fast_ahb", + "ofe_main", + "ofe_main_fast_ahb", + "vfe0_bayer", + "vfe0_bayer_fast_ahb", + "vfe1_bayer", + "vfe1_bayer_fast_ahb", + "vfe2_bayer", + "vfe2_bayer_fast_ahb"; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1", + "camnoc_nrt", + "camnoc_rt", + "icp0", + "icp1", + "jpeg_dma", + "jpeg_enc", + "rt_cdm0", + "rt_cdm1", + "rt_cdm2", + "rt_cdm3", + "rt_cdm4", + "tpg0", + "tpg1", + "tpg2"; + + interconnects =3D <&gem_noc_master_appss_proc QCOM_ICC_TAG_ACT= IVE_ONLY + &config_noc_slave_camera_cfg QCOM_ICC_TAG_ACT= IVE_ONLY>, + <&mmss_noc_master_camnoc_hf QCOM_ICC_TAG_ALWAYS + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc_master_camnoc_sf_icp QCOM_ICC_TAG_A= LWAYS + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc_master_camnoc_sf QCOM_ICC_TAG_ALWAYS + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "cam_ahb", + "cam_hf_mnoc", + "cam_sf_icp_mnoc", + "cam_sf_mnoc"; + + iommus =3D <&apps_smmu 0x1c00 0x00>, + <&apps_smmu 0x18c0 0x00>, + <&apps_smmu 0x1980 0x00>, + <&apps_smmu 0x1840 0x00>, + <&apps_smmu 0x1800 0x00>, + <&apps_smmu 0x18a0 0x00>, + <&apps_smmu 0x1880 0x00>, + <&apps_smmu 0x1820 0x00>, + <&apps_smmu 0x1860 0x00>; + + power-domains =3D <&camcc_cam_cc_ife_0_gdsc>, + <&camcc_cam_cc_ife_1_gdsc>, + <&camcc_cam_cc_ife_2_gdsc>, + <&camcc_cam_cc_titan_top_gdsc>, + <&camcc_cam_cc_ipe_gdsc>, + <&camcc_cam_cc_ofe_gdsc>; + power-domain-names =3D "ife0", + "ife1", + "ife2", + "top", + "ipe", + "ofe"; + + vdd-csiphy0-0p8-supply =3D <&vreg_0p8_supply>; + vdd-csiphy0-1p2-supply =3D <&vreg_1p2_supply>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + csiphy_ep0: endpoint { + data-lanes =3D <0 1>; + remote-endpoint =3D <&sensor_ep>; + }; + }; + }; + }; + }; --=20 2.34.1 From nobody Mon Feb 9 16:53:19 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58266346AEC for ; Mon, 12 Jan 2026 09:02:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768208564; cv=none; b=XAlwFTKCa3JROkXi4xRzwZFhzfPWUjbIbxIBViEu/hUCGeK27Iw5+xx3+seRfCJXCD18txKEATirYr4GgiMr6HlFHHQuR04/MPTr8guywxeVdzPYpNzyJQxqvmJ7TVNUs3S19+qgyOLbKVlP+DLtGFq5hCVQaamNtKDJtyw+Vbw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768208564; c=relaxed/simple; bh=qAYVIyfc7e3rEE0r6gSKyylxaDF2Xe2iZmOVEFkuC+M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Fm/wi7GzM4k9nBU1ZjpUFoiE2PG0wUAccqpeyxy5Ruf944JRg7EAxfgefjgctAWiSgXheiO+BjSBEcgV7WeCdYIgZCa9/ccBWkZrs55A+24j0tlPykPzaP2ReztsfKfVA+xIjeZDB+bE3hLQhmQX45HuSKhPDCJfW4jfOSLbfbA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=GPkE4Y5k; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=OmVzPgUm; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="GPkE4Y5k"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="OmVzPgUm" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 60C834SZ083949 for ; Mon, 12 Jan 2026 09:02:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Pq8b7EgAUNsAtM6Fas5RMbp7EvPKne1LghzApOUHTvg=; b=GPkE4Y5kn9V2Sa5j 2Bp/lAkfIVJZSBpdddh8bcER5aKeepScDq8x5RU9l4BzBOujsBW4W9UA1VHADP5c zEtg688godMvhib4m4Kpvmmu/lCEgmDwlmxYSXiOsRH8C5Mt8dk01PkuS780V315 DQBQt8ZPm07sg/ziGnJBALWcmdgxYc4q1pD8IbfYkQJ1PwzjPeMudfUkSwm/xLHx Xp4Rjdfgib8BNypXwglC6U4gpuYD6DhfMMMKN1TL1LWTqiZGriGC583S2Tw+02G/ vZIWPkMUYt6gfnscq1T26Ih3YED+U6pjTr00Q6cmQipKh7msyMT57H3XqBl2SQOC MiFu+Q== Received: from mail-dl1-f69.google.com (mail-dl1-f69.google.com [74.125.82.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bm8kytbrf-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 12 Jan 2026 09:02:41 +0000 (GMT) Received: by mail-dl1-f69.google.com with SMTP id a92af1059eb24-11f4617e256so35234451c88.0 for ; Mon, 12 Jan 2026 01:02:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1768208560; x=1768813360; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Pq8b7EgAUNsAtM6Fas5RMbp7EvPKne1LghzApOUHTvg=; b=OmVzPgUmg3jdI2siRFkFY2v5oGZ6YVKfL6rV9w9Uau3bcgIaVbDQKXh9cly2+o66XA CCjXNLPy3ZfxMzskbtTury8m872HSx+AhCfiSnAXCPNYRBNpRwvQYio0ITvTGYBl0yZ9 Fq84ToKRh0xaX151K7bHmI2UrLRMJdy97u4BigDk408J41WRgoi5a8xG6rgPX3PR4NJe ycsAOt5d0WxMHqbhhpLkX+HEaGmAH141v0e7QSXLN31kX/sNPV7m0NOBkk0I6hgl2DoE tBUyQQd4gkF1OUN541EbAdGx9SNFmm9jSUKVDV8dYoID0xZf/cQR1Rxgsu5NKuMeTwAb tcjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768208560; x=1768813360; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Pq8b7EgAUNsAtM6Fas5RMbp7EvPKne1LghzApOUHTvg=; b=GXUGF1biAhprwFRrwGNwhpboqAoWih1Rme4/MbzhRgHrlWOy9l1Et7eQz+Pv1cCgYE 6U4X0h4QJ6pDjd9BvzRBwwEpuwT5RMOuGuqq2/iyJlczrtz0Y24SAn1A/QRmsXFA8FCO 28KeI3Vi0XYpQd7/7yjQ+P9G67j1fb3AUJjfTy29fgAFVxPwDHBxm37dJEdVQc5wpymF DGisvStrS1PXaRdV61/P2JxtPREXd0ya4GGv/c8qB2UI0bdcx4wPsmSJXSfpU+8UwSaH hsdeIVpRsm1djX8jDWabBzs9k0g1ptuAy5w1KYeIxrmxGRinQUEZmS4ohbnmnlvobWrt cqEg== X-Forwarded-Encrypted: i=1; AJvYcCXtI6kK4O7cI3qD0NqEgEXWsBW3HbI0TcKZa+kQF6Pz/fGkt88+7XZuhYBNlRJeHm4CzuksK7VN/Fz2ylA=@vger.kernel.org X-Gm-Message-State: AOJu0YzABpd3afZSdSIpLDeRtLLgpkUiKvpH4HuahqhXiUzQk01gHPSO y53a6lDdiS3si9KqAhCUHNAgHqqbRlZiw1C1YSQ50lWYu/Hcn6iacG43UoX8ThKTwye7A7aQ4Op /hDx0mLb9BccP33YFuzLAEmx8yqKyDVtwO2TaUTbevalPOwKa4PS1+tgFO4hH7rz4zDg= X-Gm-Gg: AY/fxX6Scjo0XkhmWTwa8QU5nrrAhHAiBY0fCuwszHBhH0CN8CWOIWYHgfuOTejDNEc vQK+DsXCB3OKn3vsx8DjMrc28y3Q+X1eFV4P/9EPZ1ZS1daU8urJNJmLdL+RJTtC5eZGzfMufs8 hy0faQvOv8duFCFKa7225eFf0KKFsaKg4VoNN7gaMVF+X4A8mqUag9pFxbrMncXukiLNN5Q3DBn H7PJOfUEGSnE0NG1AsyvedjKBupqBXydO7CWI5wUJhrP7A32xWqdlc12w1Wd9SkpftwJR3FrNsL WXd6WUxRszINNXQ1ogPIYY+WVlS3gGXGTUiJaw1XLnVMo3c8YXFfBRgoQM7EGnVh3WzBUHsj76M cfVnO/1sX73MkJAc6viYkQ4XoBtqEeQILGPUy9/5opcCruBYhk+0QAjnroq9CP8Bo X-Received: by 2002:a05:7022:d93:b0:119:e569:f27f with SMTP id a92af1059eb24-121f8b608b4mr12937575c88.40.1768208560177; Mon, 12 Jan 2026 01:02:40 -0800 (PST) X-Google-Smtp-Source: AGHT+IGv5Osxs4SohIS/nHhwxKn5i0JKCKDk0dqbFAHZdlKg/51clHLDRxH4WYi9XO8YXLYbySCrpQ== X-Received: by 2002:a05:7022:d93:b0:119:e569:f27f with SMTP id a92af1059eb24-121f8b608b4mr12937555c88.40.1768208559618; Mon, 12 Jan 2026 01:02:39 -0800 (PST) Received: from hu-hangxian-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-121f23b798asm18888500c88.0.2026.01.12.01.02.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jan 2026 01:02:39 -0800 (PST) From: Hangxiang Ma Date: Mon, 12 Jan 2026 01:02:27 -0800 Subject: [PATCH v11 2/5] media: qcom: camss: Add Kaanapali compatible camss driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260112-kaanapali-camss-v11-2-81e4f59a5d08@oss.qualcomm.com> References: <20260112-kaanapali-camss-v11-0-81e4f59a5d08@oss.qualcomm.com> In-Reply-To: <20260112-kaanapali-camss-v11-0-81e4f59a5d08@oss.qualcomm.com> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hangxiang Ma X-Mailer: b4 0.14.3 X-Proofpoint-GUID: lsIhdhpClDlUWZvLCRfYBK7Lk4W3DUqq X-Authority-Analysis: v=2.4 cv=ZuDg6t7G c=1 sm=1 tr=0 ts=6964b8b1 cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=Eph36bqoL6-XvbZcx_wA:9 a=QEXdDO2ut3YA:10 a=vr4QvYf-bLy2KjpDp97w:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: lsIhdhpClDlUWZvLCRfYBK7Lk4W3DUqq X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTEyMDA3MCBTYWx0ZWRfXxqfhGkG/Ayy9 k4zmHs1cxIcOeoEkD8gPrY5/UQhQm6cqK4XsoJuwKKPkI4x/Kl4uXJ44fnlJH8Qp6Muf45Hj39p Smj67Go0Tc82s+vBTys3CrkG4wZwuFf4OP/Jny0JhfJ7L/wXzUl6HKVtstehJGO9iDDKTKJ+a64 J+YEH8HMhPBKzsr6/MOoJln0G7wbvG7T44TArbQxWr0AjAAfUsD6OIv8vzjIJ/4lHcqLmHWHj7Z 9pEKoUv2zkmftFBxCGKKizo7Y3p5smFTpyc0GdTE8JGuDYmqvRDT/f6I6Du2EqMf0SYNT2eOVtP E5Xrh7r9v4jRh1C0q7z2IabiUlyxBx24JMXo839KDJSADi56WQmE86ZwQx2NjlSP4NIHCkaFEq+ EkKB01EDHhmi5jR4L2SGbWXb2eaf8YyvXYPGay3pzvDQFe4T1EqcqOKhj7d+V+Aby8NZQszq3E6 Wj1aEaXdUP29+KnX/AQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-12_02,2026-01-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 bulkscore=0 spamscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601120070 Add support for Kaanapali in the camss driver. Add high level resource information along with the bus bandwidth votes. Module level detailed resource information will be enumerated in the following patches of the series. Reviewed-by: Bryan O'Donoghue Signed-off-by: Hangxiang Ma --- drivers/media/platform/qcom/camss/camss.c | 22 ++++++++++++++++++++++ drivers/media/platform/qcom/camss/camss.h | 1 + 2 files changed, 23 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index fcc2b2c3cba0..d07bde60b3a8 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -34,6 +34,20 @@ =20 static const struct parent_dev_ops vfe_parent_dev_ops; =20 +static const struct resources_icc icc_res_kaanapali[] =3D { + { + .name =3D "cam_ahb", + .icc_bw_tbl.avg =3D 150000, + .icc_bw_tbl.peak =3D 300000, + }, + /* Based on 4096 x 3072 30 FPS 2496 Mbps mode */ + { + .name =3D "cam_hf_mnoc", + .icc_bw_tbl.avg =3D 471860, + .icc_bw_tbl.peak =3D 925857, + }, +}; + static const struct camss_subdev_resources csiphy_res_8x16[] =3D { /* CSIPHY0 */ { @@ -4746,6 +4760,13 @@ static void camss_remove(struct platform_device *pde= v) camss_genpd_cleanup(camss); } =20 +static const struct camss_resources kaanapali_resources =3D { + .version =3D CAMSS_KAANAPALI, + .pd_name =3D "top", + .icc_res =3D icc_res_kaanapali, + .icc_path_num =3D ARRAY_SIZE(icc_res_kaanapali), +}; + static const struct camss_resources msm8916_resources =3D { .version =3D CAMSS_8x16, .csiphy_res =3D csiphy_res_8x16, @@ -4947,6 +4968,7 @@ static const struct camss_resources x1e80100_resource= s =3D { }; =20 static const struct of_device_id camss_dt_match[] =3D { + { .compatible =3D "qcom,kaanapali-camss", .data =3D &kaanapali_resources = }, { .compatible =3D "qcom,msm8916-camss", .data =3D &msm8916_resources }, { .compatible =3D "qcom,msm8939-camss", .data =3D &msm8939_resources }, { .compatible =3D "qcom,msm8953-camss", .data =3D &msm8953_resources }, diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/plat= form/qcom/camss/camss.h index 9d9a62640e25..b1cc4825f027 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -92,6 +92,7 @@ enum camss_version { CAMSS_8550, CAMSS_8650, CAMSS_8775P, + CAMSS_KAANAPALI, CAMSS_X1E80100, }; =20 --=20 2.34.1 From nobody Mon Feb 9 16:53:19 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A06F3346E5F for ; Mon, 12 Jan 2026 09:02:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768208567; cv=none; b=Os0cT0sHBpmr7XX69mM/rEgT9mbmhABnsrH47C5EMXrT3TfaHtEm8PcXRYrHpXb5M/7BdQMDMQdNsBaI8lqjJ421/SyVlg50HUfKbf7eowHNDH97hYzNoCjqHGKY3+yYtBPGURrBpEk8oHhPjYSvYtTiWddi9RBmTFoYVvJi2vs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768208567; c=relaxed/simple; bh=/u+alA/Ff9xskxqSGSzxhZ6DjdyLJhJwHMbTaWSQgLg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=duwKKFFrRWVgbkUeHfBVmaUL9YSL6S9KyNibOal2qR/Hp5i47PlUDiY7qI7OcIPvU+MNs3Z4TcYcv9XK36QVJWGSf8RwtsG8IyZ2TiSOLaNz2ZAeoqvVJAQsV/Do/aJgu1JHCq+EJ9Mk4P2p8GLtMTvXRkqgc2JJiYQafaEwDhw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=ePa4gq05; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=dNeRWcE2; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="ePa4gq05"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="dNeRWcE2" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 60C6SA1d1974535 for ; Mon, 12 Jan 2026 09:02:42 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 2e/jN+bAzZm77pS4j2cXZl+h3tJmq7rl334Zhn0EKCE=; b=ePa4gq05zh/LCDf8 0xHI+dESrVCgHQ9SXz9oU4VFhZ7qC+k5HcCIUS6LpW1p3uQYSfRzCdPdJt+UtoD0 xKV5oGW22SNsBJu5IBM9uEwLAwJcqqi0lTHdz2Dg6uzEqwxTzyXCD4TwFc523ASI yy1ATYR2MEq3NOX85vsYDAcCKTwWJNZZ+5t7gPPMV3AfuD4C3Dnnny0Hq+vkEqjT RJxuan0ROTdgyqJWSb/khuBKYSE8fC0Pwt2CfteKfcfUMpchDw1DpdYiSgNB+xLv 8W2F4bET9pkdqp/45zJNOgruA0vz1mYZUoYUxJWBBmhq5g1AJRsC4zSJ6NJ+krzP +9CBxg== Received: from mail-dy1-f197.google.com (mail-dy1-f197.google.com [74.125.82.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bkf57c9fn-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 12 Jan 2026 09:02:42 +0000 (GMT) Received: by mail-dy1-f197.google.com with SMTP id 5a478bee46e88-2ae51ce0642so5349376eec.0 for ; Mon, 12 Jan 2026 01:02:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1768208561; x=1768813361; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=2e/jN+bAzZm77pS4j2cXZl+h3tJmq7rl334Zhn0EKCE=; b=dNeRWcE2gPfDeCK2hlcAtZZ/OJy8hmtncToPjjz2rHnXTV6QJjsXTmdqEplf0oDL97 7zgq5NROTSQm5MTYZroJckRuFPnwRidxwn2er9f4p4yQkOeR940O2kLz90NV2AAro8Tv cs13A7nn2AiuiI3hP0itFEdL62/SyO/lDS622CuHxRO7Zt688gOPLL3I82b1WZsXZGTc KNob7va1BSx2rNV9EXdzJJqH1B1E+HRdLC/BkrMU4jw3lM3sZv3vUzNB7Q5VuV3SidGt xvto6btvNsYlb9mLBnRRoLftZfgenZ8fvKX4Ml8T4TWUGMmly8KBOImtlLRbTSUrJBGx zBvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768208561; x=1768813361; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=2e/jN+bAzZm77pS4j2cXZl+h3tJmq7rl334Zhn0EKCE=; b=fRmX2hSwbGJ/lpkYJXY+ZwudiXJlVe4gc7r2ZHMmiwBQPMEVcsQho4OviJ4PGMaqhq 9dg4y6Fkm1MKVUCzy5m3+1KYELDBBc1l23zMwQRzgYazk+vmoYortV3o9fe8FKkM0eKF yxs6YHN/GrHUkSsKN2IpG/oHFOq3+3DwVzo2fNHvDJMhE72KH0RCAkxb/pZPcaYGaNf9 5b33VJx0SnYClZnzOB4QzFYrpdWOBwqrrPXaYXzmw3m+M+4gjPYH/N51IQdzr9TovJWI tQE/lOpFrF5nGhcCvfrUyuRtNIBwq85Bz9GX5n5bkYIRKrJpsKh38ZWksrKQpdqq31oL DnIA== X-Forwarded-Encrypted: i=1; AJvYcCUIhDao9aAbb53uoe+WqnEmovm8LW1nFQlAKRLYhChmnojJizMYADlacC35XRPJNmoeKRE+QcXDn+fe7us=@vger.kernel.org X-Gm-Message-State: AOJu0YyJIMoNvjzfWxXxJ5TXe3DHvScsj42ujjktcwIKAv/vUTPd4vS6 pyRGvYjaYzB6iUR8/yxQqya3Vy9J+WUghfIz22jYQ0aWaE437XRX4CoTy3bn4XrTF5w0aXtlsQU qJoMaxPKYDc6N78W7aOsvS0dq3JkNXUhPLwwNFbe1oH0KQIuR0bBh3go9mNOibjuXKVM= X-Gm-Gg: AY/fxX7dY3YXZvL9AtjRJx0/1XjEXuJRpz9fRATk821Ei9fiJiDyvQ+JvLF3vCPsfQe dPh2FTKBH+E9g8ggu8TLKz+g7CUxRbD/pFb3PG1wcq07xb/uFcu7FIAbP2QA8gYSKixw/o4R8d1 7zIo/978vNSghLtxQj0FJo4e7MpOwrS78/Mkcf3BfMMlzBEQjGEA0jg2AH7dWmlf/DJEASJncBD yU5H2W566AS7nezbisPRIHz3cfR6oMbFD4eaKRV9Hm+RJyTeA8TWyxGYV2ID4qLV350SnfKLU6u vw3hKeq0yer2QjB0mTZ5a1jzIcpzUj2J7a8Bja0xaJqI+va3fD15uhSf7KiIekk+th3B6wxtkgl Z4vIElW3S4EQizrw1Exy/3+MBTvrnxMvqNoWmO2Qb2CYltdOsuA64pUaYfN6oo8mq X-Received: by 2002:a05:7022:6b87:b0:119:e56b:91d1 with SMTP id a92af1059eb24-121f8ac007dmr13323958c88.2.1768208560983; Mon, 12 Jan 2026 01:02:40 -0800 (PST) X-Google-Smtp-Source: AGHT+IHxdrM93QxdAgu9c2b5eh3WWC/1BEkhtFFrimlFvnggbmOw4faXejhbDrZxc9KkfkNtUMkScQ== X-Received: by 2002:a05:7022:6b87:b0:119:e56b:91d1 with SMTP id a92af1059eb24-121f8ac007dmr13323934c88.2.1768208560344; Mon, 12 Jan 2026 01:02:40 -0800 (PST) Received: from hu-hangxian-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-121f23b798asm18888500c88.0.2026.01.12.01.02.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jan 2026 01:02:40 -0800 (PST) From: Hangxiang Ma Date: Mon, 12 Jan 2026 01:02:28 -0800 Subject: [PATCH v11 3/5] media: qcom: camss: csiphy: Add support for v2.4.0 two-phase CSIPHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260112-kaanapali-camss-v11-3-81e4f59a5d08@oss.qualcomm.com> References: <20260112-kaanapali-camss-v11-0-81e4f59a5d08@oss.qualcomm.com> In-Reply-To: <20260112-kaanapali-camss-v11-0-81e4f59a5d08@oss.qualcomm.com> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hangxiang Ma X-Mailer: b4 0.14.3 X-Authority-Analysis: v=2.4 cv=K/sv3iWI c=1 sm=1 tr=0 ts=6964b8b2 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=fxCOb-bM6HI3QnfcwHgA:9 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTEyMDA3MCBTYWx0ZWRfX9ZlsoclYhq/x 8WdkVo2/6+qItjkppu2H3D7iK+dB2cdRAn6CguhcVsvK8Bebm3AptiL3nZAGxVd1a+rLIqZeuI1 AnqTkIEqVOnir4qvUMoPSrvva9Wv8kaZNuqXNDDNLvW2qOqCAGd2wrUo8DjscNiwpVxn6wjPsu8 y0+4heBb6ZdJJ6suK1kAFxseIoqycvgQNMx2WyPBwsG1Le3uAbT7GkPtjmeEtplPEK8/PE/up8A 5pcJT4Oh/X9PTS5PLaXBgNMemsK5e2gl1zj/+Gms7kn4AF51KePi3F+SH6DQmiCOvxHZMURBwez 8Wu+7eAKKVggerVWFMUUNCTLwsKd7pVSqeskMt/xK8KjBRsMtaKX05zm/xxi+szhbgtPR8XNAzr at3SZQBe+jpCFH61Ip5F3D+/284KK/6Mh3WBtIwXQPxbumAElYHbVgcIycTJDaBUqkbLvPplPW1 lG2qtWb3g9ecvXpZlFw== X-Proofpoint-GUID: t8tMQuueNn79ZPg9niS3yWpx4wz56tbV X-Proofpoint-ORIG-GUID: t8tMQuueNn79ZPg9niS3yWpx4wz56tbV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-12_02,2026-01-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 suspectscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601120070 Add more detailed resource information for CSIPHY devices in the camss driver along with the support for v2.4.0 in the 2 phase CSIPHY driver that is responsible for the PHY lane register configuration, module reset and interrupt handling. Reviewed-by: Bryan O'Donoghue Signed-off-by: Hangxiang Ma --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 124 +++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss.c | 107 ++++++++++++++++++ 2 files changed, 231 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 619abbf60781..27179af31dfa 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -683,6 +683,123 @@ csiphy_lane_regs lane_regs_sm8650[] =3D { {0x0c10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, }; =20 +/* 3nm 2PH v 2.4.0 2p5Gbps 4 lane DPHY mode */ +static const struct +csiphy_lane_regs lane_regs_2_4_0[] =3D { + /* LN 0 */ + {0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0090, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0094, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0094, 0xD7, 0x00, CSIPHY_SKEW_CAL}, + {0x005C, 0x54, 0x00, CSIPHY_SKEW_CAL}, + {0x0060, 0xFD, 0x00, CSIPHY_SKEW_CAL}, + {0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + + /* LN 2 */ + {0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x04A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0490, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0494, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0494, 0xD7, 0x00, CSIPHY_SKEW_CAL}, + {0x045C, 0x54, 0x00, CSIPHY_SKEW_CAL}, + {0x0460, 0xFD, 0x00, CSIPHY_SKEW_CAL}, + {0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + + /* LN 4 */ + {0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x08A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0890, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0894, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, + {0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0838, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x082C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0834, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x083C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0804, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0808, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0894, 0xD7, 0x00, CSIPHY_SKEW_CAL}, + {0x085C, 0x54, 0x00, CSIPHY_SKEW_CAL}, + {0x0860, 0xFD, 0x00, CSIPHY_SKEW_CAL}, + {0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + + /* LN 6 */ + {0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0CA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, + {0x0C30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C00, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C38, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C94, 0xD7, 0x00, CSIPHY_SKEW_CAL}, + {0x0C5C, 0x54, 0x00, CSIPHY_SKEW_CAL}, + {0x0C60, 0xFD, 0x00, CSIPHY_SKEW_CAL}, + {0x0C64, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + + /* LN CLK */ + {0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0EA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, + {0x0E30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + /* 4nm 2PH v 2.1.2 2p5Gbps 4 lane DPHY mode */ static const struct csiphy_lane_regs lane_regs_x1e80100[] =3D { @@ -1012,6 +1129,7 @@ static bool csiphy_is_gen2(u32 version) case CAMSS_8550: case CAMSS_8650: case CAMSS_8775P: + case CAMSS_KAANAPALI: case CAMSS_X1E80100: ret =3D true; break; @@ -1125,6 +1243,12 @@ static int csiphy_init(struct csiphy_device *csiphy) regs->lane_regs =3D &lane_regs_sa8775p[0]; regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sa8775p); break; + case CAMSS_KAANAPALI: + regs->lane_regs =3D &lane_regs_2_4_0[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_2_4_0); + regs->offset =3D 0x1000; + regs->common_status_offset =3D 0x138; + break; default: break; } diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index d07bde60b3a8..462d509a4a61 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -34,6 +34,111 @@ =20 static const struct parent_dev_ops vfe_parent_dev_ops; =20 +static const struct camss_subdev_resources csiphy_res_kaanapali[] =3D { + /* CSIPHY0 */ + { + .regulators =3D { "vdd-csiphy0-0p8", "vdd-csiphy0-1p2" }, + .clock =3D { "csiphy0", "csiphy0_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy0" }, + .interrupt =3D { "csiphy0" }, + .csiphy =3D { + .id =3D 0, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY1 */ + { + .regulators =3D { "vdd-csiphy1-0p8", "vdd-csiphy1-1p2" }, + .clock =3D { "csiphy1", "csiphy1_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy1" }, + .interrupt =3D { "csiphy1" }, + .csiphy =3D { + .id =3D 1, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY2 */ + { + .regulators =3D { "vdd-csiphy2-0p8", "vdd-csiphy2-1p2" }, + .clock =3D { "csiphy2", "csiphy2_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy2" }, + .interrupt =3D { "csiphy2" }, + .csiphy =3D { + .id =3D 2, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY3 */ + { + .regulators =3D { "vdd-csiphy3-0p8", "vdd-csiphy3-1p2" }, + .clock =3D { "csiphy3", "csiphy3_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy3" }, + .interrupt =3D { "csiphy3" }, + .csiphy =3D { + .id =3D 3, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY4 */ + { + .regulators =3D { "vdd-csiphy4-0p8", "vdd-csiphy4-1p2" }, + .clock =3D { "csiphy4", "csiphy4_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy4" }, + .interrupt =3D { "csiphy4" }, + .csiphy =3D { + .id =3D 4, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY5 */ + { + .regulators =3D { "vdd-csiphy5-0p8", "vdd-csiphy5-1p2" }, + .clock =3D { "csiphy5", "csiphy5_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy5" }, + .interrupt =3D { "csiphy5" }, + .csiphy =3D { + .id =3D 5, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, +}; + static const struct resources_icc icc_res_kaanapali[] =3D { { .name =3D "cam_ahb", @@ -4763,8 +4868,10 @@ static void camss_remove(struct platform_device *pde= v) static const struct camss_resources kaanapali_resources =3D { .version =3D CAMSS_KAANAPALI, .pd_name =3D "top", + .csiphy_res =3D csiphy_res_kaanapali, .icc_res =3D icc_res_kaanapali, .icc_path_num =3D ARRAY_SIZE(icc_res_kaanapali), + .csiphy_num =3D ARRAY_SIZE(csiphy_res_kaanapali), }; =20 static const struct camss_resources msm8916_resources =3D { --=20 2.34.1 From nobody Mon Feb 9 16:53:19 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4692346FBD for ; Mon, 12 Jan 2026 09:02:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768208567; cv=none; b=klnaA6Jo4OJ5U/RgBN/V/eHOKa5FxF3C3gRKhYz5d9L9FTcOimZiflKQIsgvK654J4wVmWA9t6ZtsG63yQXhM3rcUAAbVIDPr78aO4wiZXwMFBGQ5zGGuUUGS7gdeFFkvwe9HOJ+A5kksi4ycvxs9DcphraJjbm07TXS5sSa8vk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768208567; c=relaxed/simple; bh=BThlQv+EbyO7vipa/giQmzCQhcw4g/0HfupdK2owLeE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qmITnWe6YaBj5CHnErU7R0mcLY4wywV6u3gizvgUJ669wA3vJRnO3rQWhU1Zicvrpu71F4bmc0V4/Wiw50259aGs/luMFiNQ1azySvJzH9zQRNCwq63z87LhAFHPIY1MYY/IAw6OfDEhLcmejoaBS1d6wm/Pf9MrLe4QkD5u7yc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=S5dFBUMC; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=J2e88s2i; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="S5dFBUMC"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="J2e88s2i" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 60C83GN82891875 for ; Mon, 12 Jan 2026 09:02:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= aEK5v+b+PfsEXAEYGsNz98aOEqJVbz9OSzZcaS4S2FU=; b=S5dFBUMC6Ua4suUk MjOh1pPxbBqXj1swxB2GWjVu/ZJzk4M8aTPkZ0DBcoiH4TV7aeSJZUOLI759VfNc GC6DpeBg2l+JWDI1Exu1FU6YnIeiWTn+BT1vk7WokcttXRxkeEw1RAYVTDzpKL40 Uz4HbelwqR9FN9px6cDtQqnDc7AYYRb04riwYiMZFbKZufqkXy2EoarH+uVHscW9 eo2af10SFbsnrxZGeMYoFi7+dok00IfUe1Vy3W5NT38d1IIzGgigW8S6Tg4c8dMn KvM0ZYeKdjzlagCjAyyZF8y1YkoJZDbGL5QrKKBLjta06Ukq8/qV0/tUu0a0W2Y7 vmnpAw== Received: from mail-dy1-f199.google.com (mail-dy1-f199.google.com [74.125.82.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bkntukqnv-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 12 Jan 2026 09:02:42 +0000 (GMT) Received: by mail-dy1-f199.google.com with SMTP id 5a478bee46e88-2b04f8c5e84so6476112eec.1 for ; Mon, 12 Jan 2026 01:02:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1768208562; x=1768813362; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=aEK5v+b+PfsEXAEYGsNz98aOEqJVbz9OSzZcaS4S2FU=; b=J2e88s2ifl26pmDNrwsNkCRxH7hoQ1hPK30pDpv6fee4m0+sTBmI4tyDOe6SnwAYnr UWrSOBWQqFvVigTX4GgkMlm8vjedfjjAA/yNG97kLh81SceknfZSI/KeSBtAijlczzlj iedar5kbDB6DK7rFLSzhaSTqvctaF2n/I8SdSTiRdTsBHeiiOA9LOStp2ZoMVvEYXRGk RZOiNmQAuo5z9W0mLLoZ3744RKdt3Y1C0+F/l/Qf2lUhoM2nNtz1ocLCr/HeiPqBB4bi d0cS9I3BQ7izz6FMADiIg5Nr4EI7HfpzXEy47/DcYkHFfik0HriR817A85mF2jZNLNN/ s4vA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768208562; x=1768813362; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=aEK5v+b+PfsEXAEYGsNz98aOEqJVbz9OSzZcaS4S2FU=; b=b7Xy/Fy9pPhvPHgxrHDdVhPiYb6+d5cMsAY4X/1Va0+2YaT6DTP+x5H4ywM4qO0Hs1 uqKiMGp7cPtWrIi5z8JBYjp+MQ+DCpGNcBNI7YGnASxD+J8CpDQc4qT1mcq/iJP6RCVO I+UASJiuoEQucMHOFUeUNs2x1Cu6juRz9oK3vib5b6mYNlT61oIAtcr7PtSiz0YU5SF+ tKs4F238g5esEG6ADIHhAcKcA6yXC3E3VR+BAvENxuNxqn3y1zdO/nMe5CZcZZVfBe8g XdsR/XD8GxL3CJhADjSkcnhF76cVHseifTRSEMeRvCkJRXfB381Qo2uTDI2DfbFEkpwl Synw== X-Forwarded-Encrypted: i=1; AJvYcCW5T7M87jWIjBY2qpQRg+0cxJ9GCmW6NBXnywYxYbS/5ktfROvKVqpVk2ExKU7c3JVXtnb0Gdi+sKZaYkQ=@vger.kernel.org X-Gm-Message-State: AOJu0YwAqXUPU1/jTzSI+/uFIl94tAIcRC6tvkAdBqRGikpadS9xaOuj PJCop3hwIF3upHWa2I4YsVBTqM0qa9bDn5fyJFOdhq8DMepuDygcpRIZ8cXEIZ1ZgD8tIz6eyCv yDQVX+SJ1ZxcpkGw/4i4YbWR1JtYDA3/7DKfEDDuo1oexXEJwl0iGtUzLdd0113pjINc= X-Gm-Gg: AY/fxX5p+uNbGbBPRkg1b1pZcLC3/AsuUAPG6C23lk1FznlIpBMYQqX8yCO07QAxqZ/ lWZo3m7bZQpaigdh40uSD9SVMKt4aEMdrvGZc/rVlKCQ7AMi+vqRI98jwFNReQ5cBy5zeyGKIZ/ okU9LTHoiYneVKGDTn2oxSacttaIT1ygL3bd9wvp5t4lyWTRMZcU2PCxCtlr+71R71FFyutU7OB WioPzEnZ4yakOu0lGNXmT4wyVTsvrV1Wo3bjqU2/Pi2AJsnxKzwEI5m00XlZwiyAXe0Eom+8yWF lwDSqvNzoaq9i5JH2uz9W0XqM9yeSc34nqGd+aDn3PmzFVT38xzRulYW55sL00wKy+hRkeFBbsM Vo1dbPWgpGdP2yQV+yXhMZgxmiQ8AojCL1eLZnInMdCIRwGizAWChs+qxVvJfSqOY X-Received: by 2002:a05:7022:629a:b0:119:e56b:91e6 with SMTP id a92af1059eb24-121f8b461a4mr14226787c88.23.1768208561937; Mon, 12 Jan 2026 01:02:41 -0800 (PST) X-Google-Smtp-Source: AGHT+IFDGI1/QAsJsGYnq80YKD1+opsm1PuvvIN2unZRf9wOlVAe+ZPgsCyBl0B5chJzPN8P9jhiGQ== X-Received: by 2002:a05:7022:629a:b0:119:e56b:91e6 with SMTP id a92af1059eb24-121f8b461a4mr14226776c88.23.1768208561262; Mon, 12 Jan 2026 01:02:41 -0800 (PST) Received: from hu-hangxian-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-121f23b798asm18888500c88.0.2026.01.12.01.02.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jan 2026 01:02:40 -0800 (PST) From: Hangxiang Ma Date: Mon, 12 Jan 2026 01:02:29 -0800 Subject: [PATCH v11 4/5] media: qcom: camss: csid: Add support for CSID gen4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260112-kaanapali-camss-v11-4-81e4f59a5d08@oss.qualcomm.com> References: <20260112-kaanapali-camss-v11-0-81e4f59a5d08@oss.qualcomm.com> In-Reply-To: <20260112-kaanapali-camss-v11-0-81e4f59a5d08@oss.qualcomm.com> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hangxiang Ma , Atiya Kailany X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTEyMDA3MCBTYWx0ZWRfX0FmUkA2cNSwS 7Vp3Dbu2963J/j/ZgBbu9txunvNacyguKkF3qy5/Ars/QfIQ406eucBashHVI9XX++4QVXOOYv7 b31SWvRNUuA7vZRMfyuvMOLJtD006HvCUVhOkyaZijuY40LallafEUNErOEl1eRAEYqv/vtjrKB a5GBTxnwN9pPZu63AvaFLMu+NOhWeIS+W9j4d+x537+PFfEnyYhxc8KIGG9wj7XnKeMXOx12mER 7ZEts0lLODSov0oLfPooFUE+WDQFpWz7SnOcdeuWyf7UNJRs/34ivcFg5eZ1QOHJLVQb0LNa5PQ 0UnDtjfk6To8HDI6lWkZNZk7sXe/6vcC8PsWKYah6+yKz0FBIqqiC/UqOquxEp/Y2W+BiBvB4PC JAgL4QOFbnlM7J7+UzmFNVl2EAmn2BV+vIFNUYurLI51rB3RfE2wT30F/Z9tTba6+S3no/+mwIe CE5m9FfbNjYyq/Iwemw== X-Authority-Analysis: v=2.4 cv=R6AO2NRX c=1 sm=1 tr=0 ts=6964b8b3 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=FsTJpaSC_kWcQGXz8SoA:9 a=4Q4zU7iZy6iiv8wZ:21 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-ORIG-GUID: q3Mj3kToIyKsNi8rRbL4Gj1p17ukITBd X-Proofpoint-GUID: q3Mj3kToIyKsNi8rRbL4Gj1p17ukITBd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-12_02,2026-01-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 spamscore=0 clxscore=1015 priorityscore=1501 adultscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601120070 Add more detailed resource information for CSID devices along with the driver for CSID gen4 that is responsible for CSID register configuration, module reset and IRQ handling for BUF_DONE events. And aggregate a common definition 'CSI2_RX_CFG0_PHY_SEL_BASE_IDX' into csid header file. In this CSID version, RUP and AUP update values are split into two registers along with a SET register. Accordingly, enhance the CSID interface to accommodate both the legacy combined reg_update and the split RUP and AUP updates. Co-developed-by: Atiya Kailany Signed-off-by: Atiya Kailany Signed-off-by: Hangxiang Ma --- drivers/media/platform/qcom/camss/Makefile | 1 + drivers/media/platform/qcom/camss/camss-csid-680.c | 1 - .../media/platform/qcom/camss/camss-csid-gen3.c | 1 - .../media/platform/qcom/camss/camss-csid-gen4.c | 376 +++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss-csid.h | 11 +- drivers/media/platform/qcom/camss/camss.c | 80 +++++ 6 files changed, 467 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/pla= tform/qcom/camss/Makefile index 5e349b491513..ba9faa635bd7 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -10,6 +10,7 @@ qcom-camss-objs +=3D \ camss-csid-680.o \ camss-csid-gen2.o \ camss-csid-gen3.o \ + camss-csid-gen4.o \ camss-csiphy-2ph-1-0.o \ camss-csiphy-3ph-1-0.o \ camss-csiphy.o \ diff --git a/drivers/media/platform/qcom/camss/camss-csid-680.c b/drivers/m= edia/platform/qcom/camss/camss-csid-680.c index 3ad3a174bcfb..86134a23cd4e 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-680.c +++ b/drivers/media/platform/qcom/camss/camss-csid-680.c @@ -101,7 +101,6 @@ #define CSI2_RX_CFG0_DL2_INPUT_SEL 12 #define CSI2_RX_CFG0_DL3_INPUT_SEL 16 #define CSI2_RX_CFG0_PHY_NUM_SEL 20 -#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 #define CSI2_RX_CFG0_PHY_TYPE_SEL 24 =20 #define CSID_CSI2_RX_CFG1 0x204 diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen3.c b/drivers/= media/platform/qcom/camss/camss-csid-gen3.c index 664245cf6eb0..f09b5575572a 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-gen3.c +++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.c @@ -103,7 +103,6 @@ #define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi) (csid_is_lite(csid) && IS_CSID_= 690(csid) ?\ (0x34C + 0x100 * (rdi)) :\ (0x54C + 0x100 * (rdi))) -#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 =20 static void __csid_configure_rx(struct csid_device *csid, struct csid_phy_config *phy, int vc) diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen4.c b/drivers/= media/platform/qcom/camss/camss-csid-gen4.c new file mode 100644 index 000000000000..b000bd3e9c2e --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-csid-gen4.c @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * camss-csid-gen4.c + * + * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include +#include +#include + +#include "camss.h" +#include "camss-csid.h" +#include "camss-csid-gen3.h" + +/* Reset and Command Registers */ +#define CSID_RST_CFG 0x108 +#define RST_MODE BIT(0) +#define RST_LOCATION BIT(4) + +/* Reset and Command Registers */ +#define CSID_RST_CMD 0x10C +#define SELECT_HW_RST BIT(0) +#define SELECT_IRQ_RST BIT(2) +#define CSID_IRQ_CMD 0x110 +#define IRQ_CMD_CLEAR BIT(0) + +/* Register Update Commands, RUP/AUP */ +#define CSID_RUP_CMD 0x114 +#define CSID_AUP_CMD 0x118 +#define CSID_RUP_AUP_RDI(rdi) (BIT(8) << (rdi)) +#define CSID_RUP_AUP_CMD 0x11C +#define RUP_SET BIT(0) +#define MUP BIT(4) + +/* Top level interrupt registers */ +#define CSID_TOP_IRQ_STATUS 0x180 +#define CSID_TOP_IRQ_MASK 0x184 +#define CSID_TOP_IRQ_CLEAR 0x188 +#define INFO_RST_DONE BIT(0) +#define CSI2_RX_IRQ_STATUS BIT(2) +#define BUF_DONE_IRQ_STATUS BIT(3) + +/* Buffer done interrupt registers */ +#define CSID_BUF_DONE_IRQ_STATUS 0x1A0 +#define BUF_DONE_IRQ_STATUS_RDI_OFFSET 16 +#define CSID_BUF_DONE_IRQ_MASK 0x1A4 +#define CSID_BUF_DONE_IRQ_CLEAR 0x1A8 +#define CSID_BUF_DONE_IRQ_SET 0x1AC + +/* CSI2 RX interrupt registers */ +#define CSID_CSI2_RX_IRQ_STATUS 0x1B0 +#define CSID_CSI2_RX_IRQ_MASK 0x1B4 +#define CSID_CSI2_RX_IRQ_CLEAR 0x1B8 +#define CSID_CSI2_RX_IRQ_SET 0x1BC + +/* CSI2 RX Configuration */ +#define CSID_CSI2_RX_CFG0 0x880 +#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0 +#define CSI2_RX_CFG0_DL0_INPUT_SEL 4 +#define CSI2_RX_CFG0_PHY_NUM_SEL 20 +#define CSID_CSI2_RX_CFG1 0x884 +#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0) +#define CSI2_RX_CFG1_VC_MODE BIT(2) + +#define MSM_CSID_MAX_SRC_STREAMS_GEN4 (csid_is_lite(csid) ? 4 : 5) + +/* RDI Configuration */ +#define CSID_RDI_CFG0(rdi) \ + ((csid_is_lite(csid) ? 0x3080 : 0x5480) + 0x200 * (rdi)) +#define RDI_CFG0_RETIME_BS BIT(5) +#define RDI_CFG0_TIMESTAMP_EN BIT(6) +#define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8) +#define RDI_CFG0_DECODE_FORMAT 12 +#define RDI_CFG0_DT 16 +#define RDI_CFG0_VC 22 +#define RDI_CFG0_EN BIT(31) + +/* RDI Control and Configuration */ +#define CSID_RDI_CTRL(rdi) \ + ((csid_is_lite(csid) ? 0x3088 : 0x5488) + 0x200 * (rdi)) +#define RDI_CTRL_START_CMD BIT(0) + +#define CSID_RDI_CFG1(rdi) \ + ((csid_is_lite(csid) ? 0x3094 : 0x5494) + 0x200 * (rdi)) +#define RDI_CFG1_DROP_H_EN BIT(5) +#define RDI_CFG1_DROP_V_EN BIT(6) +#define RDI_CFG1_CROP_H_EN BIT(7) +#define RDI_CFG1_CROP_V_EN BIT(8) +#define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15) + +/* RDI Pixel Store Configuration */ +#define CSID_RDI_PIX_STORE_CFG0(rdi) (0x5498 + 0x200 * (rdi)) +#define RDI_PIX_STORE_CFG0_EN BIT(0) +#define RDI_PIX_STORE_CFG0_MIN_HBI 1 + +/* RDI IRQ Status in wrapper */ +#define CSID_CSI2_RDIN_IRQ_STATUS(rdi) (0x224 + (0x10 * (rdi))) +#define CSID_CSI2_RDIN_IRQ_MASK(rdi) (0x228 + (0x10 * (rdi))) +#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) (0x22C + (0x10 * (rdi))) +#define INFO_RUP_DONE BIT(23) + +static void __csid_aup_rup_trigger(struct csid_device *csid) +{ + /* trigger SET in combined register */ + writel(RUP_SET, csid->base + CSID_RUP_AUP_CMD); +} + +static void __csid_aup_rup_clear(struct csid_device *csid, int port_id) +{ + /* Hardware clears the registers upon consuming the settings */ + csid->aup_update &=3D ~CSID_RUP_AUP_RDI(port_id); + csid->rup_update &=3D ~CSID_RUP_AUP_RDI(port_id); +} + +static void __csid_aup_update(struct csid_device *csid, int port_id) +{ + csid->aup_update |=3D CSID_RUP_AUP_RDI(port_id); + writel(csid->aup_update, csid->base + CSID_AUP_CMD); + + __csid_aup_rup_trigger(csid); +} + +static void __csid_reg_update(struct csid_device *csid, int port_id) +{ + csid->rup_update |=3D CSID_RUP_AUP_RDI(port_id); + writel(csid->rup_update, csid->base + CSID_RUP_CMD); + + __csid_aup_rup_trigger(csid); +} + +static void __csid_configure_rx(struct csid_device *csid, + struct csid_phy_config *phy) +{ + int val; + + val =3D (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; + val |=3D phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; + val |=3D (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) + << CSI2_RX_CFG0_PHY_NUM_SEL; + writel(val, csid->base + CSID_CSI2_RX_CFG0); + + val =3D CSI2_RX_CFG1_ECC_CORRECTION_EN; + writel(val, csid->base + CSID_CSI2_RX_CFG1); +} + +static void __csid_configure_rx_vc(struct csid_device *csid, int vc) +{ + int val; + + if (vc > 3) { + val =3D readl(csid->base + CSID_CSI2_RX_CFG1); + val |=3D CSI2_RX_CFG1_VC_MODE; + writel(val, csid->base + CSID_CSI2_RX_CFG1); + } +} + +static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi) +{ + int val =3D 0; + + if (enable) + val =3D RDI_CTRL_START_CMD; + + writel(val, csid->base + CSID_RDI_CTRL(rdi)); +} + +static void __csid_configure_rdi_pix_store(struct csid_device *csid, u8 rd= i) +{ + u32 val; + + /* Configure pixel store to allow absorption of hblanking or idle time. + * This helps with horizontal crop and prevents line buffer conflicts. + * Reset state is 0x8 which has MIN_HBI=3D4, we keep the default MIN_HBI + * and just enable the pixel store functionality. + */ + val =3D (4 << RDI_PIX_STORE_CFG0_MIN_HBI) | RDI_PIX_STORE_CFG0_EN; + writel(val, csid->base + CSID_RDI_PIX_STORE_CFG0(rdi)); +} + +static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enabl= e, u8 vc) +{ + u32 val; + u8 lane_cnt =3D csid->phy.lane_cnt; + + /* Source pads matching RDI channels on hardware. + * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. + */ + struct v4l2_mbus_framefmt *input_format =3D &csid->fmt[MSM_CSID_PAD_FIRST= _SRC + vc]; + const struct csid_format_info *format =3D csid_get_fmt_entry(csid->res->f= ormats->formats, + csid->res->formats->nformats, + input_format->code); + + if (!lane_cnt) + lane_cnt =3D 4; + + val =3D RDI_CFG0_TIMESTAMP_EN; + val |=3D RDI_CFG0_TIMESTAMP_STB_SEL; + val |=3D RDI_CFG0_RETIME_BS; + + /* note: for non-RDI path, this should be format->decode_format */ + val |=3D DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT; + val |=3D vc << RDI_CFG0_VC; + val |=3D format->data_type << RDI_CFG0_DT; + writel(val, csid->base + CSID_RDI_CFG0(vc)); + + val =3D RDI_CFG1_PACKING_FORMAT_MIPI; + writel(val, csid->base + CSID_RDI_CFG1(vc)); + + /* Configure pixel store using dedicated register in gen4 */ + if (!csid_is_lite(csid)) + __csid_configure_rdi_pix_store(csid, vc); + + val =3D 0; + writel(val, csid->base + CSID_RDI_CTRL(vc)); + + val =3D readl(csid->base + CSID_RDI_CFG0(vc)); + + if (enable) + val |=3D RDI_CFG0_EN; + + writel(val, csid->base + CSID_RDI_CFG0(vc)); +} + +static void csid_configure_stream(struct csid_device *csid, u8 enable) +{ + u8 i; + u8 vc; + + __csid_configure_rx(csid, &csid->phy); + + for (vc =3D 0; vc < MSM_CSID_MAX_SRC_STREAMS_GEN4; vc++) { + if (csid->phy.en_vc & BIT(vc)) { + __csid_configure_rdi_stream(csid, enable, vc); + __csid_configure_rx_vc(csid, vc); + + for (i =3D 0; i < CAMSS_INIT_BUF_COUNT; i++) + __csid_aup_update(csid, vc); + + __csid_reg_update(csid, vc); + + __csid_ctrl_rdi(csid, enable, vc); + } + } +} + +static int csid_configure_testgen_pattern(struct csid_device *csid, s32 va= l) +{ + return 0; +} + +static void csid_subdev_reg_update(struct csid_device *csid, int port_id, + bool clear) +{ + if (clear) + __csid_aup_rup_clear(csid, port_id); + else + __csid_aup_update(csid, port_id); +} + +/** + * csid_isr - CSID module interrupt service routine + * @irq: Interrupt line + * @dev: CSID device + * + * Return IRQ_HANDLED on success + */ +static irqreturn_t csid_isr(int irq, void *dev) +{ + struct csid_device *csid =3D dev; + u32 val, buf_done_val; + u8 reset_done; + int i; + + val =3D readl(csid->base + CSID_TOP_IRQ_STATUS); + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); + + reset_done =3D val & INFO_RST_DONE; + + buf_done_val =3D readl(csid->base + CSID_BUF_DONE_IRQ_STATUS); + writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); + + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_GEN4; i++) { + if (csid->phy.en_vc & BIT(i)) { + val =3D readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i)); + writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i)); + + if (val & INFO_RUP_DONE) + csid_subdev_reg_update(csid, i, true); + + if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i)) + camss_buf_done(csid->camss, csid->id, i); + } + } + + val =3D IRQ_CMD_CLEAR; + writel(val, csid->base + CSID_IRQ_CMD); + + if (reset_done) + complete(&csid->reset_complete); + + return IRQ_HANDLED; +} + +/** + * csid_reset - Trigger reset on CSID module and wait to complete + * @csid: CSID device + * + * Return 0 on success or a negative error code otherwise + */ +static int csid_reset(struct csid_device *csid) +{ + unsigned long time; + u32 val; + int i; + + reinit_completion(&csid->reset_complete); + + val =3D INFO_RST_DONE | BUF_DONE_IRQ_STATUS; + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); + writel(val, csid->base + CSID_TOP_IRQ_MASK); + + val =3D 0; + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_GEN4; i++) { + if (csid->phy.en_vc & BIT(i)) { + /* + * Only need to clear buf done IRQ status here, + * RUP done IRQ status will be cleared once isr + * strobe generated by CSID_RST_CMD + */ + val |=3D BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i); + } + } + writel(val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); + writel(val, csid->base + CSID_BUF_DONE_IRQ_MASK); + + /* Clear all IRQ status with CLEAR bits set */ + val =3D IRQ_CMD_CLEAR; + writel(val, csid->base + CSID_IRQ_CMD); + + val =3D RST_LOCATION | RST_MODE; + writel(val, csid->base + CSID_RST_CFG); + + val =3D SELECT_HW_RST | SELECT_IRQ_RST; + writel(val, csid->base + CSID_RST_CMD); + + time =3D wait_for_completion_timeout(&csid->reset_complete, + msecs_to_jiffies(CSID_RESET_TIMEOUT_MS)); + + if (!time) { + dev_err(csid->camss->dev, "CSID reset timeout\n"); + return -EIO; + } + + return 0; +} + +static void csid_subdev_init(struct csid_device *csid) +{ + csid->testgen.nmodes =3D CSID_PAYLOAD_MODE_DISABLED; +} + +const struct csid_hw_ops csid_ops_gen4 =3D { + .configure_stream =3D csid_configure_stream, + .configure_testgen_pattern =3D csid_configure_testgen_pattern, + .hw_version =3D csid_hw_version, + .isr =3D csid_isr, + .reset =3D csid_reset, + .src_pad_code =3D csid_src_pad_code, + .subdev_init =3D csid_subdev_init, + .reg_update =3D csid_subdev_reg_update, +}; diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media= /platform/qcom/camss/camss-csid.h index aedc96ed84b2..75a113050eb1 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.h +++ b/drivers/media/platform/qcom/camss/camss-csid.h @@ -27,6 +27,8 @@ /* CSID hardware can demultiplex up to 4 outputs */ #define MSM_CSID_MAX_SRC_STREAMS 4 =20 +/* CSIPHY to hardware PHY selector mapping */ +#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 #define CSID_RESET_TIMEOUT_MS 500 =20 enum csid_testgen_mode { @@ -154,7 +156,13 @@ struct csid_device { void __iomem *base; u32 irq; char irq_name[30]; - u32 reg_update; + union { + u32 reg_update; + struct { + u32 rup_update; + u32 aup_update; + }; + }; struct camss_clock *clock; int nclocks; struct regulator_bulk_data *supplies; @@ -217,6 +225,7 @@ extern const struct csid_hw_ops csid_ops_340; extern const struct csid_hw_ops csid_ops_680; extern const struct csid_hw_ops csid_ops_gen2; extern const struct csid_hw_ops csid_ops_gen3; +extern const struct csid_hw_ops csid_ops_gen4; =20 /* * csid_is_lite - Check if CSID is CSID lite. diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 462d509a4a61..d292364d1701 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -139,6 +139,84 @@ static const struct camss_subdev_resources csiphy_res_= kaanapali[] =3D { }, }; =20 +static const struct camss_subdev_resources csid_res_kaanapali[] =3D { + /* CSID0 */ + { + .regulators =3D {}, + .clock =3D { "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid0" }, + .interrupt =3D { "csid0" }, + .csid =3D { + .is_lite =3D false, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID1 */ + { + .regulators =3D {}, + .clock =3D { "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid1" }, + .interrupt =3D { "csid1" }, + .csid =3D { + .is_lite =3D false, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID2 */ + { + .regulators =3D {}, + .clock =3D { "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid2" }, + .interrupt =3D { "csid2" }, + .csid =3D { + .is_lite =3D false, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID_LITE0 */ + { + .regulators =3D {}, + .clock =3D { "vfe_lite_csid", "vfe_lite_cphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid_lite0" }, + .interrupt =3D { "csid_lite0" }, + .csid =3D { + .is_lite =3D true, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID_LITE1 */ + { + .regulators =3D {}, + .clock =3D { "vfe_lite_csid", "vfe_lite_cphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid_lite1" }, + .interrupt =3D { "csid_lite1" }, + .csid =3D { + .is_lite =3D true, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + } +}; + static const struct resources_icc icc_res_kaanapali[] =3D { { .name =3D "cam_ahb", @@ -4869,9 +4947,11 @@ static const struct camss_resources kaanapali_resour= ces =3D { .version =3D CAMSS_KAANAPALI, .pd_name =3D "top", .csiphy_res =3D csiphy_res_kaanapali, + .csid_res =3D csid_res_kaanapali, .icc_res =3D icc_res_kaanapali, .icc_path_num =3D ARRAY_SIZE(icc_res_kaanapali), .csiphy_num =3D ARRAY_SIZE(csiphy_res_kaanapali), + .csid_num =3D ARRAY_SIZE(csid_res_kaanapali), }; =20 static const struct camss_resources msm8916_resources =3D { --=20 2.34.1 From nobody Mon Feb 9 16:53:19 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A009346FCB for ; Mon, 12 Jan 2026 09:02:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768208568; cv=none; b=q36Kn+Ecvf29g+6Ye6B8Ud+P1T3EN0SuG0rPkzlyCqe3QMq286kaOF9lzLPGs8ag5jKj2y3FJ0zsjhQzdSvzzi8xzueWI0+7pwrV/rCBgWlcMdIbOnXN47xHOmYOlQyhPvGqewHxcsikZZDayYRZxUT1ghHIpdNk6eJYyLH8lf0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768208568; c=relaxed/simple; bh=DgX6yku5CgRGY1IjtaneBwzypS1HrwIbUHjf3G7hfGI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ql2dLQCS8bxgiRvyyOKSOV/0wg0BV8PVJw5qpGKrEcynwIN+1eWyI5soKlEOybWe3EK1Q4UXxaqAmfhDPJgZ3TPgzMI+J6UFiwZwUOyMSfeSkpsSw56wkbGcps+OdJu8caew7fUF6rLRWdsxaDxDz41ZGmg9rBepVDtidH3AB/Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=cD07ERwF; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=AIi/jaCy; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="cD07ERwF"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="AIi/jaCy" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 60C8vW7l113520 for ; Mon, 12 Jan 2026 09:02:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= hN2M7tMh6jnIYZFaygnzTExjO8HiF8yj7/+0P1lf4uU=; b=cD07ERwFGSIDlc0E B4/NAv3T8p02EB38sCMjU/43lhCq1Kem1+JW+VcoUBvyGh6m3UdPyYi6UKc0Xp4A 2JPcXlW949EOBA31pqbZLwzR2BkMOhenOYLyqjnCN3M41U9I3om0Yg8Ht0Ve9DPq mFeke/dPBmfSru5qlnh73p0qU1cMeBBD8MmXad6jTbXB5X2Y4CFozH53nC2sSsUI ETGn12EokS8d4OAonh8msDfsRzXXQrnE2Kw4HiOZKU7W2wMTm2D3VuhlpI8MBXKD fatTZ4nY5qRvzWELzRlPDUWvfBh1zsjZUuHtj7gQqUqNsUxqhNpGzvSfR7+EgD5O /I0FSQ== Received: from mail-dl1-f71.google.com (mail-dl1-f71.google.com [74.125.82.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bmr4uh3nj-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 12 Jan 2026 09:02:43 +0000 (GMT) Received: by mail-dl1-f71.google.com with SMTP id a92af1059eb24-121b1cb8377so9043114c88.0 for ; Mon, 12 Jan 2026 01:02:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1768208563; x=1768813363; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=hN2M7tMh6jnIYZFaygnzTExjO8HiF8yj7/+0P1lf4uU=; b=AIi/jaCy2EQL7B/anSct+GOu/V2/c2nFKevi6kFSlKYYgG66k/UL8i9mdSBNruUer9 bZdLjv0M44TyNQwiHfrPWzn/khcjh28Rp7ukS1OkhZy+5oPMQx3LsXUkYhWkIS1UeIjG eEoxJBbnuGNudb8aJBAGtRAJPBQLGx46nG8JgMpO0I6SxQtcVsl41/0MUP6UZohvr3Bu VlS5razYWaQMqH4ZRWgQ9+1oR6uo5SmwEjoZWJXB3p2bDi+9aM31bjngeY9pVAKVaeyt vv5cAUT7+2pVe9p2IDkCLVve9XENzbBbH2GKTZk2PACOGD9fbUC3J4hVF22yVPyDwhUi r8rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768208563; x=1768813363; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=hN2M7tMh6jnIYZFaygnzTExjO8HiF8yj7/+0P1lf4uU=; b=NLyBqe1EPv9Kb3tjSeuouazI+2KKaLVZsaCXE9iFyq3kmk+XXY83weEY59cxgnLRyV r8Ocau417N/NzphwUogfbakr34kGt++dME7NFfXp/iNggOeXlA5wyD5rEA+duuuqqtod XvyYBXNOAaEcK2GC1nzQlDvzrV3HWLE1qorMY8YY5a/e2oDjOaaMvrZlO6PLgDAfLBUX UOHAq4hjRJFytO66m0jsMnnDhM9lNhLeMXnkHKB5624Aa82K5xZjRdxwRD2LoWJMU38I 1H3frs555NpNR5X8uUYBu54G5qBxScyMNqXga1XAh1etWCbBZkmHNFe5Sv9xZENWqrwc DCYg== X-Forwarded-Encrypted: i=1; AJvYcCU3T1ZBG5r2R5Jd/MPMs7i2KA+y14AZ9liwUQptOVjB1n9tOF8mq8Pw2Hpf+DkVoHZbo8Lw+jITY+IEQBE=@vger.kernel.org X-Gm-Message-State: AOJu0Yw66ifmKfbxLOdUEGmuyazGufFawa6eeFZJKGxvyslSRkqWbqFT gPMQ6RApP9uU9yWADI1Cszc25/iIgfr/Z8r9gcJvEwZ4teaaqRCbksGGTvfB9fDPYbWlkloA2iS GLNruH8EdOUPh66v3OQkG8kA/XuUfQuslOnwokfoXbbD8qnYGkU/llPuWp0ctm7/O7VU= X-Gm-Gg: AY/fxX75SUmCYppo8dT7tgLaioSPmvSvgCGFU3VBx9TT463Ozmmx0d79NyBT6OojDKf XQLMjJ3rAc9bI+qRtYXGgTWit8HkC4jGl7qBTJu9ASZkHRmIBe9ifbZarLZAVGiCl0NQfgxCaeY n36yJ58GWohStsDTEcl8RtwjMYuycz/6UtpZnIwu6KQJl5Df2V1ogpuMiwZr+NUf9U7cTq9k+Z8 I1Mw1Jl4OLyL6grKnHEjuFFfYHpQQY2eq1ZKcxipdCsW7YQcyBZRbjx4/2Bfon3S/klALkJo3MH Mr3sbL+DdvE1t8xM+lv7JpDIV1qtD3z6YbwHYabNQVKk26Oha1vvBHySnp+Ji9rHtoyUUR7XTgG Uq/RcVPo6wYY3i3rm98nYk6A7Or6z27g9ObLWhpnP5LY6zjppRdsKuW7gldxnFgj0 X-Received: by 2002:a05:7022:e0c:b0:11d:f44c:ad97 with SMTP id a92af1059eb24-121f8b7b3efmr15176904c88.24.1768208562705; Mon, 12 Jan 2026 01:02:42 -0800 (PST) X-Google-Smtp-Source: AGHT+IEE4XTsezGLjgIim8+smNlhgstBstVNPPZeOCdKjnEZYOuZhd1WXvNQ2KPtloKBq1Aylojuqw== X-Received: by 2002:a05:7022:e0c:b0:11d:f44c:ad97 with SMTP id a92af1059eb24-121f8b7b3efmr15176887c88.24.1768208562087; Mon, 12 Jan 2026 01:02:42 -0800 (PST) Received: from hu-hangxian-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-121f23b798asm18888500c88.0.2026.01.12.01.02.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jan 2026 01:02:41 -0800 (PST) From: Hangxiang Ma Date: Mon, 12 Jan 2026 01:02:30 -0800 Subject: [PATCH v11 5/5] media: qcom: camss: vfe: Add support for VFE gen4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260112-kaanapali-camss-v11-5-81e4f59a5d08@oss.qualcomm.com> References: <20260112-kaanapali-camss-v11-0-81e4f59a5d08@oss.qualcomm.com> In-Reply-To: <20260112-kaanapali-camss-v11-0-81e4f59a5d08@oss.qualcomm.com> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hangxiang Ma , Atiya Kailany X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTEyMDA3MCBTYWx0ZWRfXwwT3JjO7awmb xyTl1qdygQpH6BAeBfqFldKO731DQst1x8ng8OKyQlxrh1+pyrYtwUUAiQpHBphTYoXqlJLiA+p 5TKB9hmsAndL0P2oucsY+gDCl08BHYYYzbUbrz3b6hz8/s4RbAH3TUPGOc7rEdmRPi+uFUyoixL XXKXpb88pj2hBv4JHYTPqwQkhhPCy5q8LoaI0Y5j8dT1fP2u+cx1Fwt2MHMEre1doRclw1wLK3y 4sksARhobNLybv15BbR64l4leVasxObwKzLZRix/gNHRsquNoKIma0aox3UahUdm7ojHVcLxOOx RGzhcYMUbABDcOJU7Sv8V33vcIAK6OP+TsPjR4RyUnjcSX5kzghphfLZRWyjmDa/HCj5DrJPy7q XZiZ5Qlwv1BQl3UxjzAi3H9CtOfHZve/csw1Fzb84fl/u5shCHuXrqvbXZjfnHrCKUHanx7Cszh U4xkopxrG1eMpAyem8A== X-Proofpoint-ORIG-GUID: iopcCCjgeuPTNg-C9WspafM54sihnLnw X-Authority-Analysis: v=2.4 cv=YocChoYX c=1 sm=1 tr=0 ts=6964b8b3 cx=c_pps a=JYo30EpNSr/tUYqK9jHPoA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=4o9gmvoekZ77T9ZvDsgA:9 a=QEXdDO2ut3YA:10 a=Fk4IpSoW4aLDllm1B1p-:22 X-Proofpoint-GUID: iopcCCjgeuPTNg-C9WspafM54sihnLnw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-12_02,2026-01-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 clxscore=1015 impostorscore=0 adultscore=0 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601120070 Add Video Front End (VFE) version gen4 as found on the Kaanapali SoC. The FULL front end modules in Kaanapali camera subsystem are called TFEs (Thin Front End), however, retaining the name VFE at places to maintain consistency and avoid unnecessary code changes. This change limits the VFE output lines to 3 for now as constrained by the CAMSS driver framework. Kaanapali architecture requires for the REG_UPDATE and AUP_UPDATE to be issued after all of the CSID configuration has been done. Additionally, the number of AUP_UPDATEs should match the number of buffers enqueued to the write master while it's being enabled. Although the real time data from TFE goes through the RT_CAMNOC, we are required to enable both the camnoc_rt_axi and camnoc_nrt_axi clocks for the PDX_NOC, that follows both the RT and NRT NOCs in this architecture, to ensure that both of the latter are idle after reset. Co-developed-by: Atiya Kailany Signed-off-by: Atiya Kailany Signed-off-by: Hangxiang Ma --- drivers/media/platform/qcom/camss/Makefile | 1 + drivers/media/platform/qcom/camss/camss-vfe.c | 9 +- drivers/media/platform/qcom/camss/camss-vfe.h | 2 + drivers/media/platform/qcom/camss/camss.c | 143 ++++++++++++++++++++++= ++++ 4 files changed, 153 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/pla= tform/qcom/camss/Makefile index ba9faa635bd7..ed8001ef90a6 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -23,6 +23,7 @@ qcom-camss-objs +=3D \ camss-vfe-480.o \ camss-vfe-680.o \ camss-vfe-gen3.o \ + camss-vfe-gen4.o \ camss-vfe-gen1.o \ camss-vfe-vbif.o \ camss-vfe.o \ diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/= platform/qcom/camss/camss-vfe.c index 9c7ad8aa4058..399be8b70fed 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -351,6 +351,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 = sink_code, case CAMSS_8550: case CAMSS_8650: case CAMSS_8775P: + case CAMSS_KAANAPALI: case CAMSS_X1E80100: switch (sink_code) { case MEDIA_BUS_FMT_YUYV8_1X16: @@ -523,7 +524,8 @@ int vfe_enable_output_v2(struct vfe_line *line) =20 spin_lock_irqsave(&vfe->output_lock, flags); =20 - ops->reg_update_clear(vfe, line->id); + if (ops->reg_update_clear) + ops->reg_update_clear(vfe, line->id); =20 if (output->state > VFE_OUTPUT_RESERVED) { dev_err(vfe->camss->dev, @@ -550,7 +552,9 @@ int vfe_enable_output_v2(struct vfe_line *line) output->gen2.active_num++; ops->vfe_wm_update(vfe, output->wm_idx[0], output->buf[i]->addr[0], line); - ops->reg_update(vfe, line->id); + + if (!vfe->res->reg_update_after_csid_config) + ops->reg_update(vfe, line->id); } =20 spin_unlock_irqrestore(&vfe->output_lock, flags); @@ -2009,6 +2013,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) case CAMSS_8550: case CAMSS_8650: case CAMSS_8775P: + case CAMSS_KAANAPALI: case CAMSS_X1E80100: ret =3D 16; break; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/= platform/qcom/camss/camss-vfe.h index ae9dad353a37..c402ef170c81 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.h +++ b/drivers/media/platform/qcom/camss/camss-vfe.h @@ -133,6 +133,7 @@ struct vfe_isr_ops { =20 struct vfe_subdev_resources { bool is_lite; + bool reg_update_after_csid_config; u8 line_num; bool has_pd; char *pd_name; @@ -249,6 +250,7 @@ extern const struct vfe_hw_ops vfe_ops_340; extern const struct vfe_hw_ops vfe_ops_480; extern const struct vfe_hw_ops vfe_ops_680; extern const struct vfe_hw_ops vfe_ops_gen3; +extern const struct vfe_hw_ops vfe_ops_gen4; =20 int vfe_get(struct vfe_device *vfe); void vfe_put(struct vfe_device *vfe); diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index d292364d1701..2bd4e0934c09 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -217,6 +217,147 @@ static const struct camss_subdev_resources csid_res_k= aanapali[] =3D { } }; =20 +/* In Kaanapali, CAMNOC requires all CAMNOC_RT_TFEX clocks + * to operate on any TFE Full. + */ +static const struct camss_subdev_resources vfe_res_kaanapali[] =3D { + /* VFE0 - TFE Full */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "vfe0_fast_ahb", "vfe0", + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2", + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 360280000, 480000000, 630000000, 716000000, + 833000000 }, + { 0 }, + { 0 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe0" }, + .interrupt =3D { "vfe0" }, + .vfe =3D { + .line_num =3D 3, + .is_lite =3D false, + .reg_update_after_csid_config =3D true, + .has_pd =3D true, + .pd_name =3D "ife0", + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE1 - TFE Full */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "vfe1_fast_ahb", "vfe1", + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2", + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 360280000, 480000000, 630000000, 716000000, + 833000000 }, + { 0 }, + { 0 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe1" }, + .interrupt =3D { "vfe1" }, + .vfe =3D { + .line_num =3D 3, + .is_lite =3D false, + .reg_update_after_csid_config =3D true, + .has_pd =3D true, + .pd_name =3D "ife1", + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE2 - TFE Full */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "vfe2_fast_ahb", "vfe2", + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2", + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 360280000, 480000000, 630000000, 716000000, + 833000000 }, + { 0 }, + { 0 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe2" }, + .interrupt =3D { "vfe2" }, + .vfe =3D { + .line_num =3D 3, + .is_lite =3D false, + .reg_update_after_csid_config =3D true, + .has_pd =3D true, + .pd_name =3D "ife2", + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE3 - IFE Lite */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "vfe_lite_ahb", "vfe_lite", + "camnoc_rt_vfe_lite", "camnoc_rt_axi", + "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 266666667, 400000000, 480000000 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe_lite0" }, + .interrupt =3D { "vfe_lite0" }, + .vfe =3D { + .line_num =3D 4, + .is_lite =3D true, + .reg_update_after_csid_config =3D true, + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE4 - IFE Lite */ + { + .regulators =3D {}, + .clock =3D { "gcc_axi_hf", "vfe_lite_ahb", "vfe_lite", + "camnoc_rt_vfe_lite", "camnoc_rt_axi", + "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 266666667, 400000000, 480000000 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe_lite1" }, + .interrupt =3D { "vfe_lite1" }, + .vfe =3D { + .line_num =3D 4, + .is_lite =3D true, + .reg_update_after_csid_config =3D true, + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, +}; + static const struct resources_icc icc_res_kaanapali[] =3D { { .name =3D "cam_ahb", @@ -4948,10 +5089,12 @@ static const struct camss_resources kaanapali_resou= rces =3D { .pd_name =3D "top", .csiphy_res =3D csiphy_res_kaanapali, .csid_res =3D csid_res_kaanapali, + .vfe_res =3D vfe_res_kaanapali, .icc_res =3D icc_res_kaanapali, .icc_path_num =3D ARRAY_SIZE(icc_res_kaanapali), .csiphy_num =3D ARRAY_SIZE(csiphy_res_kaanapali), .csid_num =3D ARRAY_SIZE(csid_res_kaanapali), + .vfe_num =3D ARRAY_SIZE(vfe_res_kaanapali), }; =20 static const struct camss_resources msm8916_resources =3D { --=20 2.34.1