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Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 2d06c950e814..f6827ed71f4e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -335,13 +335,13 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc= _mixer *mixer, max_alpha =3D 0x3ff; fg_alpha =3D pstate->base.alpha >> 6; } - bg_alpha =3D max_alpha - fg_alpha; =20 /* default to opaque blending */ if (pstate->base.pixel_blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE || !format->alpha_enable) { blend_op =3D DPU_BLEND_FG_ALPHA_FG_CONST | DPU_BLEND_BG_ALPHA_BG_CONST; + bg_alpha =3D max_alpha - fg_alpha; } else if (pstate->base.pixel_blend_mode =3D=3D DRM_MODE_BLEND_PREMULTI) { blend_op =3D DPU_BLEND_FG_ALPHA_FG_CONST | DPU_BLEND_BG_ALPHA_FG_PIXEL; @@ -350,6 +350,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_m= ixer *mixer, blend_op |=3D DPU_BLEND_BG_MOD_ALPHA | DPU_BLEND_BG_INV_MOD_ALPHA; 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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-59b7c2dd9e2sm2373045e87.5.2026.01.11.19.23.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jan 2026 19:23:40 -0800 (PST) From: Dmitry Baryshkov Date: Mon, 12 Jan 2026 05:23:31 +0200 Subject: [PATCH v2 2/2] drm/msm/dpu: use full scale alpha in _dpu_crtc_setup_blend_cfg() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260112-dpu-rework-alpha-v2-2-d168785911d5@oss.qualcomm.com> References: <20260112-dpu-rework-alpha-v2-0-d168785911d5@oss.qualcomm.com> In-Reply-To: <20260112-dpu-rework-alpha-v2-0-d168785911d5@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=5356; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=wVzgQvj4XKBtkSLhvRIrDRSYnT6jGkVdSMihboRjAGk=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBpZGk0nqmrZXcI8g9JEWG9kqjQWiUqm4blxk4KX D8YedEddQ+JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaWRpNAAKCRCLPIo+Aiko 1VUbB/928UmgbNSFQOdbBS355affEJPu8oHSvNiHbmf3wVEWKPNncCUQ6vGP8vznO5DZOX16i82 UW+EpOeGha1lj9kFV6V3en2jejc/THJaBL6DCrclQaPkxKtvKlO4VvU2J/MX8IETP1f4+Ntx9pS RoTQQjKi3iPEiffc4GcteQOqfvzxKf2xYBblBsBZkYa5SUuzYcb0+F+Xjf5N2W9mcFz96990QVC YmO3giRvHYknronhY/8UZ3VzDPsnFoUvKq7UpCs1DTYJYCl4UPKmuzJyu0qOSzNLXmEvLvGmEow Rab71nSjAVGDKRowKla1ykWb2Y/aK4vT9B5ORM7CWYYXgC+G X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=K/sv3iWI c=1 sm=1 tr=0 ts=6964693f cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=9g_qaOd13HrosajSYkoA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTEyMDAyNiBTYWx0ZWRfX5NPrwQ+U9qwM K92PSDPbl3Fy4IjCTOfnwhG/BqiSP/BPHDNMICpcvLnu/+wh+JvrhXJCfGJCeSiCSPivNr8DK2P 5HCub79VLlmf2lnlOYhFLzWLKsPhrCCOEgwQqU6ZQg8W+9qmivSGc4Lq4sFjQfxwDodJ5Hdao0h DFDtn6/rQMO0akLx3Tk+QyCcGca1Nst0DEf+UFSqVMfDPV7S+R5b27+HXHoKjc+B43V9M6Aeu6X sh1rrRRR5RQlq9hOaxk/Zrp8lXzsMwAObMpcDyQDZmkMbn3YoxStkreJYvxUFt2GfUkykgFuEX9 gSI2exlyL1kYnbkdv0qARAFXh9HMFIftcMZ7gKiAOTPjdIMFDm/GwgOCdSySkAIiIAmEyCfVSNg xshAIxjyOXSZVVPrw3VwDxbLQZ0TiMQmA2z7wInmFjbpnQ48Wt4nX1KdFAGYxOJXwrScANdTVpP uIBBdDXBZAyPfYwfcxg== X-Proofpoint-GUID: MNqIjcoE5vlr2Ae2_IAkL6DGP0UwG_hz X-Proofpoint-ORIG-GUID: MNqIjcoE5vlr2Ae2_IAkL6DGP0UwG_hz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-11_09,2026-01-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 suspectscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601120026 Both _dpu_crtc_setup_blend_cfg() and setup_blend_config_alpha() callbacks embed knowledge about platform's alpha range (8-bit or 10-bit). Make _dpu_crtc_setup_blend_cfg() use full 16-bit values for alpha and reduce alpha only in DPU-specific callbacks. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 16 +++++----------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 21 +++++++++++++-------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 2 +- 3 files changed, 19 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index f6827ed71f4e..61af96fdd7e0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -326,26 +326,20 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc= _mixer *mixer, { struct dpu_hw_mixer *lm =3D mixer->hw_lm; u32 blend_op; - u32 fg_alpha, bg_alpha, max_alpha; + u32 fg_alpha, bg_alpha; =20 - if (mdss_ver->core_major_ver < 12) { - max_alpha =3D 0xff; - fg_alpha =3D pstate->base.alpha >> 8; - } else { - max_alpha =3D 0x3ff; - fg_alpha =3D pstate->base.alpha >> 6; - } + fg_alpha =3D pstate->base.alpha; =20 /* default to opaque blending */ if (pstate->base.pixel_blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE || !format->alpha_enable) { blend_op =3D DPU_BLEND_FG_ALPHA_FG_CONST | DPU_BLEND_BG_ALPHA_BG_CONST; - bg_alpha =3D max_alpha - fg_alpha; + bg_alpha =3D DRM_BLEND_ALPHA_OPAQUE - fg_alpha; } else if (pstate->base.pixel_blend_mode =3D=3D DRM_MODE_BLEND_PREMULTI) { blend_op =3D DPU_BLEND_FG_ALPHA_FG_CONST | DPU_BLEND_BG_ALPHA_FG_PIXEL; - if (fg_alpha !=3D max_alpha) { + if (fg_alpha !=3D DRM_BLEND_ALPHA_OPAQUE) { bg_alpha =3D fg_alpha; blend_op |=3D DPU_BLEND_BG_MOD_ALPHA | DPU_BLEND_BG_INV_MOD_ALPHA; @@ -357,7 +351,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_m= ixer *mixer, /* coverage blending */ blend_op =3D DPU_BLEND_FG_ALPHA_FG_PIXEL | DPU_BLEND_BG_ALPHA_FG_PIXEL; - if (fg_alpha !=3D max_alpha) { + if (fg_alpha !=3D DRM_BLEND_ALPHA_OPAQUE) { bg_alpha =3D fg_alpha; blend_op |=3D DPU_BLEND_FG_MOD_ALPHA | DPU_BLEND_FG_INV_MOD_ALPHA | diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_hw_lm.c index e8a76d5192c2..b7779726bf10 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -126,7 +126,9 @@ static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *= ctx, u32 *misr_value) } =20 static void dpu_hw_lm_setup_blend_config_combined_alpha(struct dpu_hw_mixe= r *ctx, - u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) + u32 stage, + u16 fg_alpha, u16 bg_alpha, + u32 blend_op) { struct dpu_hw_blk_reg_map *c =3D &ctx->hw; int stage_off; @@ -139,15 +141,16 @@ static void dpu_hw_lm_setup_blend_config_combined_alp= ha(struct dpu_hw_mixer *ctx if (WARN_ON(stage_off < 0)) return; =20 - const_alpha =3D (bg_alpha & 0xFF) | ((fg_alpha & 0xFF) << 16); + const_alpha =3D (bg_alpha >> 8) | ((fg_alpha >> 8) << 16); DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha); DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); } =20 static void dpu_hw_lm_setup_blend_config_combined_alpha_v12(struct dpu_hw_mixer *ctx, - u32 stage, u32 fg_alpha, - u32 bg_alpha, u32 blend_op) + u32 stage, + u16 fg_alpha, u16 bg_alpha, + u32 blend_op) { struct dpu_hw_blk_reg_map *c =3D &ctx->hw; int stage_off; @@ -160,13 +163,15 @@ dpu_hw_lm_setup_blend_config_combined_alpha_v12(struc= t dpu_hw_mixer *ctx, if (WARN_ON(stage_off < 0)) return; =20 - const_alpha =3D (bg_alpha & 0x3ff) | ((fg_alpha & 0x3ff) << 16); + const_alpha =3D (bg_alpha >> 6) | ((fg_alpha >> 6) << 16); DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA_V12 + stage_off, const_alpha); DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); } =20 static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx, - u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) + u32 stage, + u16 fg_alpha, u16 bg_alpha, + u32 blend_op) { struct dpu_hw_blk_reg_map *c =3D &ctx->hw; int stage_off; @@ -178,8 +183,8 @@ static void dpu_hw_lm_setup_blend_config(struct dpu_hw_= mixer *ctx, if (WARN_ON(stage_off < 0)) return; =20 - DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha); - DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha); + DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha >> 8); + DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha >> 8); DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); } =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_hw_lm.h index ecbb77711d83..380ca673f6de 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h @@ -41,7 +41,7 @@ struct dpu_hw_lm_ops { * for the specified stage */ void (*setup_blend_config)(struct dpu_hw_mixer *ctx, uint32_t stage, - uint32_t fg_alpha, uint32_t bg_alpha, uint32_t blend_op); + u16 fg_alpha, u16 bg_alpha, uint32_t blend_op); =20 /** * @setup_alpha_out: Alpha color component selection from either fg or bg --=20 2.47.3