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Sun, 11 Jan 2026 01:28:47 -0800 (PST) Received: from buffalo-ssd.taila54753.ts.net ([240b:253:4760:f400:1ebf:ceff:fe7f:5e0b]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a3e3cd2b3asm143851625ad.88.2026.01.11.01.28.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jan 2026 01:28:47 -0800 (PST) From: Akari Tsuyukusa To: Sean Wang , Linus Walleij , Matthias Brugger , AngeloGioacchino Del Regno , linux-mediatek@lists.infradead.org (moderated list:PIN CONTROLLER - MEDIATEK), linux-gpio@vger.kernel.org (open list:PIN CONTROL SUBSYSTEM), linux-kernel@vger.kernel.org (open list:ARM/Mediatek SoC support), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support) Cc: Akari Tsuyukusa Subject: [PATCH] pinctrl: mediatek: common-v1: introduce per-function multibase control Date: Sun, 11 Jan 2026 18:28:31 +0900 Message-ID: <20260111092833.466263-1-akkun11.open@gmail.com> X-Mailer: git-send-email 2.52.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The current common-v1 framework implicitly assumes that certain register operations might span across multiple base addresses. This logic is currently hardcoded in mtk_get_regmap, where any pin falling within the [type1_start, type1_end) range is redirected to regmap2. This approach is suboptimal for two reasons: 1. It forces all SoCs except MT8135 to define dummy type1_start/end values (set to the last pin number + 1) to avoid unintended regmap switching, which is non-intuitive and cluttering the SoC data. 2. It assumes most register types (DRV, IES, SMT, etc.) follow the same splitting rule, even though hardware design might only require it for specific functional registers. Refactor the framework by introducing explicit '[func]_multibase' flags for each register category in struct mtk_pinctrl_devdata. This allows each SoC to explicitly declare which operations require multiple bases. For MT8135, which is currently the only multipre regmap user, enable needed multibase flags to keep existing behavior. For other SoCs, multibase flags will default to false, removing the need for fragile range-based workarounds and making the regmap selection logic more robust and explicit. Also, delete type1_start and type1_end, which are no longer needed by this refactor, from struct mtk_pinctrl_devdata. Signed-off-by: Akari Tsuyukusa --- drivers/pinctrl/mediatek/pinctrl-mt2701.c | 2 - drivers/pinctrl/mediatek/pinctrl-mt2712.c | 2 - drivers/pinctrl/mediatek/pinctrl-mt6397.c | 2 - drivers/pinctrl/mediatek/pinctrl-mt8127.c | 2 - drivers/pinctrl/mediatek/pinctrl-mt8135.c | 8 +++ drivers/pinctrl/mediatek/pinctrl-mt8167.c | 2 - drivers/pinctrl/mediatek/pinctrl-mt8173.c | 2 - drivers/pinctrl/mediatek/pinctrl-mt8365.c | 2 - drivers/pinctrl/mediatek/pinctrl-mt8516.c | 2 - drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 62 ++++++++++++------- drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 9 +++ 11 files changed, 57 insertions(+), 38 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c b/drivers/pinctrl/me= diatek/pinctrl-mt2701.c index 6b1c7122b0fb..30bec29de9bd 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c @@ -504,8 +504,6 @@ static const struct mtk_pinctrl_devdata mt2701_pinctrl_= data =3D { .dout_offset =3D 0x0500, .din_offset =3D 0x0630, .pinmux_offset =3D 0x0760, - .type1_start =3D 280, - .type1_end =3D 280, .port_shf =3D 4, .port_mask =3D 0x1f, .port_align =3D 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c b/drivers/pinctrl/me= diatek/pinctrl-mt2712.c index bb7394ae252b..eb6ecaa72679 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2712.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c @@ -553,8 +553,6 @@ static const struct mtk_pinctrl_devdata mt2712_pinctrl_= data =3D { .dout_offset =3D 0x0300, .din_offset =3D 0x0400, .pinmux_offset =3D 0x0500, - .type1_start =3D 210, - .type1_end =3D 210, .port_shf =3D 4, .port_mask =3D 0xf, .port_align =3D 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6397.c b/drivers/pinctrl/me= diatek/pinctrl-mt6397.c index 03d0f65d7bcc..af5f48039895 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6397.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6397.c @@ -27,8 +27,6 @@ static const struct mtk_pinctrl_devdata mt6397_pinctrl_da= ta =3D { .dout_offset =3D (MT6397_PIN_REG_BASE + 0x080), .din_offset =3D (MT6397_PIN_REG_BASE + 0x0a0), .pinmux_offset =3D (MT6397_PIN_REG_BASE + 0x0c0), - .type1_start =3D 41, - .type1_end =3D 41, .port_shf =3D 3, .port_mask =3D 0x3, .port_align =3D 2, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8127.c b/drivers/pinctrl/me= diatek/pinctrl-mt8127.c index f5030a9ea40b..1ec1ddb317c3 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c @@ -272,8 +272,6 @@ static const struct mtk_pinctrl_devdata mt8127_pinctrl_= data =3D { .dout_offset =3D 0x0400, .din_offset =3D 0x0500, .pinmux_offset =3D 0x0600, - .type1_start =3D 143, - .type1_end =3D 143, .port_shf =3D 4, .port_mask =3D 0xf, .port_align =3D 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/me= diatek/pinctrl-mt8135.c index 77c6ac464e86..9c9689be33be 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c @@ -292,15 +292,23 @@ static const struct mtk_pinctrl_devdata mt8135_pinctr= l_data =3D { .n_grp_cls =3D ARRAY_SIZE(mt8135_drv_grp), .pin_drv_grp =3D mt8135_pin_drv, .n_pin_drv_grps =3D ARRAY_SIZE(mt8135_pin_drv), + .drv_multibase =3D true, .spec_pull_set =3D spec_pull_set, .dir_offset =3D 0x0000, + .dir_multibase =3D true, .ies_offset =3D 0x0100, + .ies_multibase =3D true, .pullen_offset =3D 0x0200, + .pullen_multibase =3D true, .smt_offset =3D 0x0300, + .smt_multibase =3D true, .pullsel_offset =3D 0x0400, + .pullsel_multibase =3D true, .dout_offset =3D 0x0800, + .dout_multibase =3D true, .din_offset =3D 0x0A00, .pinmux_offset =3D 0x0C00, + .pinmux_multibase =3D true, .type1_start =3D 34, .type1_end =3D 149, .port_shf =3D 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8167.c b/drivers/pinctrl/me= diatek/pinctrl-mt8167.c index 143c26622272..27dfaabbf41e 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8167.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8167.c @@ -305,8 +305,6 @@ static const struct mtk_pinctrl_devdata mt8167_pinctrl_= data =3D { .dout_offset =3D 0x0100, .din_offset =3D 0x0200, .pinmux_offset =3D 0x0300, - .type1_start =3D 125, - .type1_end =3D 125, .port_shf =3D 4, .port_mask =3D 0xf, .port_align =3D 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/me= diatek/pinctrl-mt8173.c index b214deeafbf1..cc1ad8963502 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c @@ -313,8 +313,6 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_= data =3D { .dout_offset =3D 0x0400, .din_offset =3D 0x0500, .pinmux_offset =3D 0x0600, - .type1_start =3D 135, - .type1_end =3D 135, .port_shf =3D 4, .port_mask =3D 0xf, .port_align =3D 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/me= diatek/pinctrl-mt8365.c index e3e0d66cfbbf..b793caac5773 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c @@ -457,8 +457,6 @@ static const struct mtk_pinctrl_devdata mt8365_pinctrl_= data =3D { .pullen_offset =3D 0x0860, .pullsel_offset =3D 0x0900, .drv_offset =3D 0x0710, - .type1_start =3D 145, - .type1_end =3D 145, .port_shf =3D 4, .port_mask =3D 0x1f, .port_align =3D 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/me= diatek/pinctrl-mt8516.c index abda75d4354e..c91e5f001c10 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c @@ -305,8 +305,6 @@ static const struct mtk_pinctrl_devdata mt8516_pinctrl_= data =3D { .dout_offset =3D 0x0100, .din_offset =3D 0x0200, .pinmux_offset =3D 0x0300, - .type1_start =3D 125, - .type1_end =3D 125, .port_shf =3D 4, .port_mask =3D 0xf, .port_align =3D 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctr= l/mediatek/pinctrl-mtk-common.c index d6a46fe0cda8..032944184a07 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -42,14 +42,15 @@ static const char * const mtk_gpio_functions[] =3D { }; =20 /* - * There are two base address for pull related configuration - * in mt8135, and different GPIO pins use different base address. - * When pin number greater than type1_start and less than type1_end, - * should use the second base address. + * Some chips (e.g., mt8135) have multiple base addresses for pin configur= ation. + * When multibase is true and the pin number falls within the specified ra= nge + * [type1_start, type1_end), the second base address should be used. */ static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl, - unsigned long pin) + unsigned long pin, bool multibase) { + if (!multibase) + return pctl->regmap1; if (pin >=3D pctl->devdata->type1_start && pin < pctl->devdata->type1_end) return pctl->regmap2; return pctl->regmap1; @@ -82,7 +83,8 @@ static int mtk_pmx_gpio_set_direction(struct pinctrl_dev = *pctldev, else reg_addr =3D SET_ADDR(reg_addr, pctl); =20 - regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); + regmap_write(mtk_get_regmap(pctl, offset, pctl->devdata->dir_multibase), + reg_addr, bit); return 0; } =20 @@ -100,7 +102,8 @@ static int mtk_gpio_set(struct gpio_chip *chip, unsigne= d int offset, int value) else reg_addr =3D CLR_ADDR(reg_addr, pctl); =20 - return regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); + return regmap_write(mtk_get_regmap(pctl, offset, pctl->devdata->dout_mult= ibase), + reg_addr, bit); } =20 static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, @@ -108,6 +111,7 @@ static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pc= tl, unsigned pin, { unsigned int reg_addr, offset; unsigned int bit; + bool multibase; =20 /** * Due to some soc are not support ies/smt config, add this special @@ -123,12 +127,18 @@ static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *= pctl, unsigned pin, arg =3D=3D PIN_CONFIG_INPUT_SCHMITT_ENABLE) return -EINVAL; =20 + if (arg =3D=3D PIN_CONFIG_INPUT_ENABLE) + multibase =3D pctl->devdata->ies_multibase; + else + multibase =3D pctl->devdata->smt_multibase; + /* * Due to some pins are irregular, their input enable and smt * control register are discontinuous, so we need this special handle. */ if (pctl->devdata->spec_ies_smt_set) { - return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), + return pctl->devdata->spec_ies_smt_set( + mtk_get_regmap(pctl, pin, multibase), pctl->devdata, pin, value, arg); } =20 @@ -144,7 +154,7 @@ static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pc= tl, unsigned pin, else reg_addr =3D CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl); =20 - regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit); + regmap_write(mtk_get_regmap(pctl, pin, multibase), reg_addr, bit); return 0; } =20 @@ -229,7 +239,8 @@ static int mtk_pconf_set_driving(struct mtk_pinctrl *pc= tl, shift =3D pin_drv->bit + drv_grp->low_bit; mask <<=3D shift; val <<=3D shift; - return regmap_update_bits(mtk_get_regmap(pctl, pin), + return regmap_update_bits( + mtk_get_regmap(pctl, pin, pctl->devdata->drv_multibase), pin_drv->offset, mask, val); } =20 @@ -314,9 +325,9 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl= *pctl, * the parameter should be "MTK_PUPD_SET_R1R0_00". */ r1r0 =3D enable ? arg : MTK_PUPD_SET_R1R0_00; - ret =3D pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin), - pctl->devdata, pin, isup, - r1r0); + ret =3D pctl->devdata->spec_pull_set( + mtk_get_regmap(pctl, pin, pctl->devdata->pullsel_multibase), + pctl->devdata, pin, isup, r1r0); if (!ret) return 0; } @@ -334,7 +345,8 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl= *pctl, pctl->devdata->pullen_offset; reg_pullsel =3D mtk_get_port(pctl, pin) + pctl->devdata->pullsel_offset; - ret =3D pctl->devdata->mt8365_set_clr_mode(mtk_get_regmap(pctl, pin), + /* MT8365 do not use multibase. */ + ret =3D pctl->devdata->mt8365_set_clr_mode(pctl->regmap1, bit, reg_pullen, reg_pullsel, enable, isup); if (ret) @@ -358,8 +370,10 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctr= l *pctl, reg_pullsel =3D CLR_ADDR(mtk_get_port(pctl, pin) + pctl->devdata->pullsel_offset, pctl); =20 - regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit); - regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit); + regmap_write(mtk_get_regmap(pctl, pin, pctl->devdata->pullen_multibase), + reg_pullen, bit); + regmap_write(mtk_get_regmap(pctl, pin, pctl->devdata->pullsel_multibase), + reg_pullsel, bit); return 0; } =20 @@ -710,8 +724,9 @@ static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev, struct mtk_pinctrl *pctl =3D pinctrl_dev_get_drvdata(pctldev); =20 if (pctl->devdata->spec_pinmux_set) - pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin), - pin, mode); + pctl->devdata->spec_pinmux_set( + mtk_get_regmap(pctl, pin, pctl->devdata->pinmux_multibase), + pin, mode); =20 reg_addr =3D ((pin / pctl->devdata->mode_per_reg) << pctl->devdata->port_= shf) + pctl->devdata->pinmux_offset; @@ -720,8 +735,9 @@ static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev, bit =3D pin % pctl->devdata->mode_per_reg; mask <<=3D (GPIO_MODE_BITS * bit); val =3D (mode << (GPIO_MODE_BITS * bit)); - return regmap_update_bits(mtk_get_regmap(pctl, pin), - reg_addr, mask, val); + return regmap_update_bits( + mtk_get_regmap(pctl, pin, pctl->devdata->pinmux_multibase), + reg_addr, mask, val); } =20 static const struct mtk_desc_pin * @@ -832,7 +848,8 @@ static int mtk_gpio_get_direction(struct gpio_chip *chi= p, unsigned offset) if (pctl->devdata->spec_dir_set) pctl->devdata->spec_dir_set(®_addr, offset); =20 - regmap_read(pctl->regmap1, reg_addr, &read_val); + regmap_read(mtk_get_regmap(pctl, offset, pctl->devdata->dir_multibase), + reg_addr, &read_val); if (read_val & bit) return GPIO_LINE_DIRECTION_OUT; =20 @@ -850,7 +867,8 @@ static int mtk_gpio_get(struct gpio_chip *chip, unsigne= d offset) pctl->devdata->din_offset; =20 bit =3D BIT(offset & pctl->devdata->mode_mask); - regmap_read(pctl->regmap1, reg_addr, &read_val); + regmap_read(mtk_get_regmap(pctl, offset, pctl->devdata->din_multibase), + reg_addr, &read_val); return !!(read_val & bit); } =20 diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctr= l/mediatek/pinctrl-mtk-common.h index 11afa12a96cb..1c5c956ff33b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -277,6 +277,15 @@ struct mtk_pinctrl_devdata { unsigned int mode_mask; unsigned int mode_per_reg; unsigned int mode_shf; + bool dir_multibase; + bool ies_multibase; + bool smt_multibase; + bool pullen_multibase; + bool pullsel_multibase; + bool drv_multibase; + bool dout_multibase; + bool din_multibase; + bool pinmux_multibase; }; =20 struct mtk_pinctrl { --=20 2.52.0