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[2a02:3100:af95:6f00:1e86:bff:fe2f:57b7]) by smtp.googlemail.com with ESMTPSA id a640c23a62f3a-b842a56c552sm1483591066b.68.2026.01.10.12.04.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Jan 2026 12:04:49 -0800 (PST) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, adrian.larumbe@collabora.com, steven.price@arm.com, boris.brezillon@collabora.com, robh@kernel.org, Martin Blumenstingl Subject: [PATCH 3/3] arm64: dts: amlogic: S4: Add the Mali-G31 GPU Date: Sat, 10 Jan 2026 21:04:26 +0100 Message-ID: <20260110200426.1461575-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260110200426.1461575-1-martin.blumenstingl@googlemail.com> References: <20260110200426.1461575-1-martin.blumenstingl@googlemail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The vendor BSP indicates that the Mali-G31 GPU on Meson S4 SoCs is similar to the setup on G12A SoCs. The OPP table and resets are the same, but the clocks (G12A only has one, S4 has two) and interrupt numbers are different. Describe the Mali-G31 GPU with it's resources and enable it by default since all frequencies are using the same voltage (as the GPU is supplied by VDDEE changes to the VDDEE voltage are not needed at runtime). Signed-off-by: Martin Blumenstingl --- arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 49 +++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dt= s/amlogic/meson-s4.dtsi index 9d99ed2994df..efd3dda7d2c1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -66,6 +66,39 @@ xtal: xtal-clk { #clock-cells =3D <0>; }; =20 + gpu_opp_table: opp-table-gpu { + compatible =3D "operating-points-v2"; + + opp-124999998 { + opp-hz =3D /bits/ 64 <124999998>; + opp-microvolt =3D <800000>; + }; + opp-249999996 { + opp-hz =3D /bits/ 64 <249999996>; + opp-microvolt =3D <800000>; + }; + opp-285714281 { + opp-hz =3D /bits/ 64 <285714281>; + opp-microvolt =3D <800000>; + }; + opp-399999994 { + opp-hz =3D /bits/ 64 <399999994>; + opp-microvolt =3D <800000>; + }; + opp-499999992 { + opp-hz =3D /bits/ 64 <499999992>; + opp-microvolt =3D <800000>; + }; + opp-666666656 { + opp-hz =3D /bits/ 64 <666666656>; + opp-microvolt =3D <800000>; + }; + opp-799999988 { + opp-hz =3D /bits/ 64 <799999988>; + opp-microvolt =3D <800000>; + }; + }; + firmware { sm: secure-monitor { compatible =3D "amlogic,meson-gxbb-sm"; @@ -783,6 +816,22 @@ ir: ir@84040 { status =3D "disabled"; }; =20 + gpu: gpu@400000 { + compatible =3D "amlogic,meson-s4-mali", "arm,mali-bifrost"; + reg =3D <0x00 0xfe400000 0x00 0x40000>; + interrupts =3D , + , + ; + interrupt-names =3D "job", "mmu", "gpu"; + clocks =3D <&clkc_periphs CLKID_MALI_SEL>, + <&clkc_periphs CLKID_MALI>; + clock-names =3D "gpu", "bus"; + resets =3D <&reset RESET_MALI>, + <&reset RESET_MALI_APB>; + operating-points-v2 =3D <&gpu_opp_table>; + #cooling-cells =3D <2>; + }; + hwrng: rng@440788 { compatible =3D "amlogic,meson-s4-rng"; reg =3D <0x0 0x440788 0x0 0x0c>; --=20 2.52.0