From nobody Sat Feb 7 08:44:37 2026 Received: from out-170.mta0.migadu.com (out-170.mta0.migadu.com [91.218.175.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C4E933A715 for ; Sat, 10 Jan 2026 13:11:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768050698; cv=none; b=naCAkVzw3RxwY6t83UknVV1yII4xf99OhPWHAdPUPj/veztzC84fHD9c7eJb0bNqQfJgDhWtnBSX0lvxOnUttzJQWxx/vwDM6QV/piP+Wu+NaVzqrmhRV6Pvz7e1klZB2c4BsO6QRqLic76eUNW9YNFs7v9B0DagTpmEmqi5eKQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768050698; c=relaxed/simple; bh=zTpLRTSy0ZUqiQJ+KvqsMfzFVY6/tmYVMzLvCconr3g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tBaOYJRy9wxM5lJoHUzq1O3B1q7D0BoWueG2nX3LaqNKxI9yCBz1fILdtaKKxQVkgk33ZSZ1iRo1zSw3cgK8O6FhTLqb9wmzTh80FT4T44Uonr4tQ6HC3YQPHakLWVgDxdYd/5YrNcjlytDb5zqvkNKJTjNxBXvK/SdSpov3kaQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=KM3bz/v7; arc=none smtp.client-ip=91.218.175.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="KM3bz/v7" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1768050694; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qlejOwTnBJqaPxH2B148xQWvfCM7iTTuVyvcvolJRno=; b=KM3bz/v7BSQvKc3Vt4/QgNGzBOvcoP+MQ5VhhG2tkQO1yfhDTXGI8tyGn9ZEyS6ozZQX7s HfUp91vsbgQUDchxI/wOBJUVrK7DxpmWgoROXdRVSB82MEaPQB/68FNZsNIrHhXgXRCvyb xCl92OOuasJWmCjj2v71YqsoYrPMT20= From: George Guo To: chenhuacai@kernel.org Cc: dongtai.guo@linux.dev, guodongtai@kylinos.cn, hengqi.chen@gmail.com, kernel@xen0n.name, lianyangyang@kylinos.cn, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, r@hev.cc, xry111@xry111.site Subject: [PATCH v10 loongarch-next 1/3] LoongArch: Add SCQ support detection Date: Sat, 10 Jan 2026 21:11:22 +0800 Message-ID: <20260110131124.99866-2-dongtai.guo@linux.dev> In-Reply-To: <20260110131124.99866-1-dongtai.guo@linux.dev> References: <20260110131124.99866-1-dongtai.guo@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Check CPUCFG2_SCQ bit to determine if the CPU supports SCQ instruction. Co-developed-by: Yangyang Lian Signed-off-by: Yangyang Lian Reviewed-by: Hengqi Chen Tested-by: Hengqi Chen Signed-off-by: George Guo --- arch/loongarch/include/asm/cpu-features.h | 1 + arch/loongarch/include/asm/cpu.h | 2 ++ arch/loongarch/include/uapi/asm/hwcap.h | 1 + arch/loongarch/kernel/cpu-probe.c | 4 ++++ arch/loongarch/kernel/proc.c | 1 + 5 files changed, 9 insertions(+) diff --git a/arch/loongarch/include/asm/cpu-features.h b/arch/loongarch/inc= lude/asm/cpu-features.h index 3745d991a99a..39c7fe64c3ef 100644 --- a/arch/loongarch/include/asm/cpu-features.h +++ b/arch/loongarch/include/asm/cpu-features.h @@ -67,5 +67,6 @@ #define cpu_has_msgint cpu_opt(LOONGARCH_CPU_MSGINT) #define cpu_has_avecint cpu_opt(LOONGARCH_CPU_AVECINT) #define cpu_has_redirectint cpu_opt(LOONGARCH_CPU_REDIRECTINT) +#define cpu_has_scq cpu_opt(LOONGARCH_CPU_SCQ) =20 #endif /* __ASM_CPU_FEATURES_H */ diff --git a/arch/loongarch/include/asm/cpu.h b/arch/loongarch/include/asm/= cpu.h index f3efb00b6141..5531039027ec 100644 --- a/arch/loongarch/include/asm/cpu.h +++ b/arch/loongarch/include/asm/cpu.h @@ -125,6 +125,7 @@ static inline char *id_to_core_name(unsigned int id) #define CPU_FEATURE_MSGINT 29 /* CPU has MSG interrupt */ #define CPU_FEATURE_AVECINT 30 /* CPU has AVEC interrupt */ #define CPU_FEATURE_REDIRECTINT 31 /* CPU has interrupt remapping */ +#define CPU_FEATURE_SCQ 32 /* CPU has SC.Q instruction */ =20 #define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG) #define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM) @@ -158,5 +159,6 @@ static inline char *id_to_core_name(unsigned int id) #define LOONGARCH_CPU_MSGINT BIT_ULL(CPU_FEATURE_MSGINT) #define LOONGARCH_CPU_AVECINT BIT_ULL(CPU_FEATURE_AVECINT) #define LOONGARCH_CPU_REDIRECTINT BIT_ULL(CPU_FEATURE_REDIRECTINT) +#define LOONGARCH_CPU_SCQ BIT_ULL(CPU_FEATURE_SCQ) =20 #endif /* _ASM_CPU_H */ diff --git a/arch/loongarch/include/uapi/asm/hwcap.h b/arch/loongarch/inclu= de/uapi/asm/hwcap.h index 2b34e56cfa9e..a3c570d407b9 100644 --- a/arch/loongarch/include/uapi/asm/hwcap.h +++ b/arch/loongarch/include/uapi/asm/hwcap.h @@ -18,5 +18,6 @@ #define HWCAP_LOONGARCH_LBT_MIPS (1 << 12) #define HWCAP_LOONGARCH_PTW (1 << 13) #define HWCAP_LOONGARCH_LSPW (1 << 14) +#define HWCAP_LOONGARCH_CPU_SCQ (1 << 15) =20 #endif /* _UAPI_ASM_HWCAP_H */ diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-= probe.c index 08a227034042..7c7708ce4063 100644 --- a/arch/loongarch/kernel/cpu-probe.c +++ b/arch/loongarch/kernel/cpu-probe.c @@ -177,6 +177,10 @@ static void cpu_probe_common(struct cpuinfo_loongarch = *c) c->options |=3D LOONGARCH_CPU_LAM; elf_hwcap |=3D HWCAP_LOONGARCH_LAM; } + if (config & CPUCFG2_SCQ) { + c->options |=3D LOONGARCH_CPU_SCQ; + elf_hwcap |=3D HWCAP_LOONGARCH_CPU_SCQ; + } if (config & CPUCFG2_FP) { c->options |=3D LOONGARCH_CPU_FPU; elf_hwcap |=3D HWCAP_LOONGARCH_FPU; diff --git a/arch/loongarch/kernel/proc.c b/arch/loongarch/kernel/proc.c index a8800d20e11b..a60471b96440 100644 --- a/arch/loongarch/kernel/proc.c +++ b/arch/loongarch/kernel/proc.c @@ -62,6 +62,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "Features\t\t:"); if (cpu_has_cpucfg) seq_printf(m, " cpucfg"); if (cpu_has_lam) seq_printf(m, " lam"); + if (cpu_has_scq) seq_printf(m, " scq"); if (cpu_has_ual) seq_printf(m, " ual"); if (cpu_has_fpu) seq_printf(m, " fpu"); if (cpu_has_lsx) seq_printf(m, " lsx"); --=20 2.49.0 From nobody Sat Feb 7 08:44:37 2026 Received: from out-183.mta0.migadu.com (out-183.mta0.migadu.com [91.218.175.183]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD1E5345CAE for ; Sat, 10 Jan 2026 13:11:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.183 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768050705; cv=none; b=axkMc6QzrQmR0BHDjm9U7rbuza8CE+8qiFy9NJnalh7BCSh9ahDmlPttNden1BT/x5qpK2x1iObQZvMGpdX7c6QGxZFWNzMMecCBmK5aBbAaY951y4bl1nXNej5lKrPXzi4+oXHhWr3VraK/q2Qxx+SL1Rn6W5vpLHOrqmyWX30= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768050705; c=relaxed/simple; bh=uOZnKZf6yAtdKjU6Ca5rsP0oyljxPvc5Qx6oKowl4C0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=f+TmmhuDKkVC+jw3jooWnorkdJpp+pJghzEBeFPedWEEZUd4cv3LMqYvq2TGp6jAODCe9arGqzhW8hkSPQfnMm/zU0kBMqzgX1VtgK/aWRYejHI0I70Tg/KXIpnnErv9hu8EQPCCDz02gbKdTS235EQv/V2xhXS4/Vcsrsb0PaE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=brdWQvxW; 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DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1768050696; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4UEks7loLN2fnIS414ze+LIrWa/uXQyvGPLMWxyd64o=; b=brdWQvxWbyGqaic7rTdaeZejS0KQ2y1KAK38KOqQ0pIN9repa2QbLx6q8yS1cUgbBbdeAA 3HTXZa9RmuihpZYu/HTpMO50jjTOxTBHC9Iry+sZjVX3nmshQYOhPWZFLbg1caxPGURyvR 9mIfeTFxl+gz+yRmyiSx12JSZzHktd4= From: George Guo To: chenhuacai@kernel.org Cc: dongtai.guo@linux.dev, guodongtai@kylinos.cn, hengqi.chen@gmail.com, kernel@xen0n.name, lianyangyang@kylinos.cn, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, r@hev.cc, xry111@xry111.site Subject: [PATCH v10 loongarch-next 2/3] LoongArch: Add 128-bit atomic cmpxchg support Date: Sat, 10 Jan 2026 21:11:23 +0800 Message-ID: <20260110131124.99866-3-dongtai.guo@linux.dev> In-Reply-To: <20260110131124.99866-1-dongtai.guo@linux.dev> References: <20260110131124.99866-1-dongtai.guo@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" From: George Guo Implement 128-bit atomic compare-and-exchange using LoongArch's LL.D/SC.Q instructions. At the same time, fix BPF scheduler test failures (scx_central scx_qmap) caused by kmalloc_nolock_noprof returning NULL due to missing 128-bit atomics. The NULL returns led to -ENOMEM errors during scheduler initialization, causing test cases to fail. Verified by testing with the scx_qmap scheduler (located in tools/sched_ext/). Building with `make` and running ./tools/sched_ext/build/bin/scx_qmap. Link: https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf.git/commit/?i= d=3D5fb750e8a9ae Acked-by: Hengqi Chen Tested-by: Hengqi Chen Signed-off-by: George Guo --- arch/loongarch/Kconfig | 2 ++ arch/loongarch/include/asm/cmpxchg.h | 48 ++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig index 730f34214519..f9845ebec1a4 100644 --- a/arch/loongarch/Kconfig +++ b/arch/loongarch/Kconfig @@ -114,6 +114,7 @@ config LOONGARCH select GENERIC_TIME_VSYSCALL select GPIOLIB select HAS_IOPORT + select HAVE_ALIGNED_STRUCT_PAGE select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_BITREVERSE select HAVE_ARCH_JUMP_LABEL @@ -130,6 +131,7 @@ config LOONGARCH select HAVE_ARCH_TRANSPARENT_HUGEPAGE select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD select HAVE_ASM_MODVERSIONS + select HAVE_CMPXCHG_DOUBLE select HAVE_CONTEXT_TRACKING_USER select HAVE_C_RECORDMCOUNT select HAVE_DEBUG_KMEMLEAK diff --git a/arch/loongarch/include/asm/cmpxchg.h b/arch/loongarch/include/= asm/cmpxchg.h index 0494c2ab553e..d25e25d8fc9e 100644 --- a/arch/loongarch/include/asm/cmpxchg.h +++ b/arch/loongarch/include/asm/cmpxchg.h @@ -8,6 +8,7 @@ #include #include #include +#include =20 #define __xchg_amo_asm(amswap_db, m, val) \ ({ \ @@ -137,6 +138,44 @@ __arch_xchg(volatile void *ptr, unsigned long x, int s= ize) __ret; \ }) =20 +union __u128_halves { + u128 full; + struct { + u64 low; + u64 high; + }; +}; + +#define __arch_cmpxchg128(ptr, old, new) \ +({ \ + union __u128_halves __old, __new, __ret; \ + volatile u64 *__ptr =3D (volatile u64 *)(ptr); \ + \ + __old.full =3D (old); \ + __new.full =3D (new); \ + \ + __asm__ __volatile__( \ + "1: ll.d %0, %3 # 128-bit cmpxchg low \n" \ + __WEAK_LLSC_MB \ + " ld.d %1, %4 # 128-bit cmpxchg high \n" \ + " bne %0, %z5, 2f \n" \ + " bne %1, %z6, 2f \n" \ + " move $t0, %z7 \n" \ + " move $t1, %z8 \n" \ + " sc.q $t0, $t1, %2 \n" \ + " beqz $t0, 1b \n" \ + "2: \n" \ + __WEAK_LLSC_MB \ + : "=3D&r" (__ret.low), "=3D&r" (__ret.high) \ + : "r" (__ptr), \ + "ZC" (__ptr[0]), "m" (__ptr[1]), \ + "Jr" (__old.low), "Jr" (__old.high), \ + "Jr" (__new.low), "Jr" (__new.high) \ + : "t0", "t1", "memory"); \ + \ + __ret.full; \ +}) + static inline unsigned int __cmpxchg_small(volatile void *ptr, unsigned in= t old, unsigned int new, unsigned int size) { @@ -224,6 +263,15 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsig= ned long new, unsigned int __res; \ }) =20 +/* cmpxchg128 */ +#define system_has_cmpxchg128() (cpu_has_scq) + +#define arch_cmpxchg128(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) !=3D 16); \ + __arch_cmpxchg128(ptr, o, n); \ +}) + #ifdef CONFIG_64BIT #define arch_cmpxchg64_local(ptr, o, n) \ ({ \ --=20 2.49.0 From nobody Sat Feb 7 08:44:37 2026 Received: from out-182.mta0.migadu.com (out-182.mta0.migadu.com [91.218.175.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43F692737FC for ; Sat, 10 Jan 2026 13:11:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768050703; cv=none; b=PCYL0QUj/bJSvN64mXz382oOHYY6cohYLfzeVbMhXV8R7SMmPYuwIBQ+JrnDAyMWEZITyEk9JywoAjcxGcmsFjX0cLVWZYZLPfcRNqGgnDbBFTisR8XMj1gEzdk+l7z6A3bgKTQKaghEG5xt893FwOly1oGh2qKztRRK9CZVALY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768050703; c=relaxed/simple; bh=mXzYmdPymKdFZmqUTG4DDgWxoPAZbBB43kYBnZLwNXw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rxbEafTyEeREN0K4C4DCMtjgIJW6fq8d+7BoSnzI5T/5fULbCSRaLBfXIKjA3neEqN3tojhyZGD2DX+POpXn3Og3XYduKUAN3St9AISnwGIIWhkMmMbnvaDmzCbUKkllUPOyBUtVtn5lX9mGedSbRCFQpzbn5J3d7NgkQMN06yU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=e7qKrdHg; arc=none smtp.client-ip=91.218.175.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="e7qKrdHg" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1768050699; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PnZbaDT/Si5j8xWwOdVLRST9Yhvt2+rDxL/Ki8l0ZZw=; b=e7qKrdHg6YSuL6mQjRD22hW0DOs0hAUAHpqf57Y/I/Kypm7gsrwmPr3fCVS9h4G76nTmmE B3/xlb/udI6ER7ToRs+5+9bQdt8ry9kiqLx/z4SMWM1Ujj9+kqo7wukmU2bon064OW072J Uy36aRizIGHRZ5y1efHvUedUT/0kZW4= From: George Guo To: chenhuacai@kernel.org Cc: dongtai.guo@linux.dev, guodongtai@kylinos.cn, hengqi.chen@gmail.com, kernel@xen0n.name, lianyangyang@kylinos.cn, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, r@hev.cc, xry111@xry111.site Subject: [PATCH v10 loongarch-next 3/3] LoongArch: Replace seq_printf with seq_puts for simple strings Date: Sat, 10 Jan 2026 21:11:24 +0800 Message-ID: <20260110131124.99866-4-dongtai.guo@linux.dev> In-Reply-To: <20260110131124.99866-1-dongtai.guo@linux.dev> References: <20260110131124.99866-1-dongtai.guo@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Fix warnings like: "Prefer seq_puts to seq_printf" by checkpatch.pl. Replace seq_printf() calls with seq_puts() in show_cpuinfo() when outputting simple constant strings without format specifiers. This improves performance slightly as seq_puts() avoids parsing the format string. Signed-off-by: George Guo --- arch/loongarch/kernel/proc.c | 64 ++++++++++++++++++++++-------------- 1 file changed, 40 insertions(+), 24 deletions(-) diff --git a/arch/loongarch/kernel/proc.c b/arch/loongarch/kernel/proc.c index a60471b96440..a8127e83da65 100644 --- a/arch/loongarch/kernel/proc.c +++ b/arch/loongarch/kernel/proc.c @@ -50,33 +50,49 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "Address Sizes\t\t: %d bits physical, %d bits virtual\n", cpu_pabits + 1, cpu_vabits + 1); =20 - seq_printf(m, "ISA\t\t\t:"); + seq_puts(m, "ISA\t\t\t:"); if (isa & LOONGARCH_CPU_ISA_LA32R) - seq_printf(m, " loongarch32r"); + seq_puts(m, " loongarch32r"); if (isa & LOONGARCH_CPU_ISA_LA32S) - seq_printf(m, " loongarch32s"); + seq_puts(m, " loongarch32s"); if (isa & LOONGARCH_CPU_ISA_LA64) - seq_printf(m, " loongarch64"); - seq_printf(m, "\n"); + seq_puts(m, " loongarch64"); + seq_puts(m, "\n"); =20 - seq_printf(m, "Features\t\t:"); - if (cpu_has_cpucfg) seq_printf(m, " cpucfg"); - if (cpu_has_lam) seq_printf(m, " lam"); - if (cpu_has_scq) seq_printf(m, " scq"); - if (cpu_has_ual) seq_printf(m, " ual"); - if (cpu_has_fpu) seq_printf(m, " fpu"); - if (cpu_has_lsx) seq_printf(m, " lsx"); - if (cpu_has_lasx) seq_printf(m, " lasx"); - if (cpu_has_crc32) seq_printf(m, " crc32"); - if (cpu_has_complex) seq_printf(m, " complex"); - if (cpu_has_crypto) seq_printf(m, " crypto"); - if (cpu_has_ptw) seq_printf(m, " ptw"); - if (cpu_has_lspw) seq_printf(m, " lspw"); - if (cpu_has_lvz) seq_printf(m, " lvz"); - if (cpu_has_lbt_x86) seq_printf(m, " lbt_x86"); - if (cpu_has_lbt_arm) seq_printf(m, " lbt_arm"); - if (cpu_has_lbt_mips) seq_printf(m, " lbt_mips"); - seq_printf(m, "\n"); + seq_puts(m, "Features\t\t:"); + if (cpu_has_cpucfg) + seq_puts(m, " cpucfg"); + if (cpu_has_lam) + seq_puts(m, " lam"); + if (cpu_has_scq) + seq_puts(m, " scq"); + if (cpu_has_ual) + seq_puts(m, " ual"); + if (cpu_has_fpu) + seq_puts(m, " fpu"); + if (cpu_has_lsx) + seq_puts(m, " lsx"); + if (cpu_has_lasx) + seq_puts(m, " lasx"); + if (cpu_has_crc32) + seq_puts(m, " crc32"); + if (cpu_has_complex) + seq_puts(m, " complex"); + if (cpu_has_crypto) + seq_puts(m, " crypto"); + if (cpu_has_ptw) + seq_puts(m, " ptw"); + if (cpu_has_lspw) + seq_puts(m, " lspw"); + if (cpu_has_lvz) + seq_puts(m, " lvz"); + if (cpu_has_lbt_x86) + seq_puts(m, " lbt_x86"); + if (cpu_has_lbt_arm) + seq_puts(m, " lbt_arm"); + if (cpu_has_lbt_mips) + seq_puts(m, " lbt_mips"); + seq_puts(m, "\n"); =20 seq_printf(m, "Hardware Watchpoint\t: %s", str_yes_no(cpu_has_watch)); if (cpu_has_watch) { @@ -84,7 +100,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) cpu_data[n].watch_ireg_count, cpu_data[n].watch_dreg_count); } =20 - seq_printf(m, "\n\n"); + seq_puts(m, "\n\n"); =20 return 0; } --=20 2.49.0