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Fri, 09 Jan 2026 21:19:05 -0800 (PST) From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:13 +0800 Subject: [PATCH v4 01/11] dt-bindings: riscv: add SpacemiT X100 CPU compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260110-k3-basic-dt-v4-1-d492f3a30ffa@riscstar.com> References: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com> In-Reply-To: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Greg Kroah-Hartman , Jiri Slaby , Lubomir Rintel , Yangyu Chen Cc: Paul Walmsley , Conor Dooley , Heinrich Schuchardt , Kevin Meng Zhang , Anup Patel , Andrew Jones , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, linux-serial@vger.kernel.org, Guodong Xu , Krzysztof Kozlowski , Heinrich Schuchardt X-Mailer: b4 0.14.3 Add compatible string for the SpacemiT X100 core. [1] The X100 is a 64-bit RVA23-compliant RISC-V core from SpacemiT. X100 supports the RISC-V vector and hypervisor extensions and all mandatory extersions as required by the RVA23U64 and RVA23S64 profiles, per the definition in 'RVA23 Profile, Version 1.0'. [2] From a microarchieture viewpoint, the X100 features a 4-issue out-of-order pipeline. X100 is used in SpacemiT K3 SoC. Link: https://www.spacemit.com/en/spacemit-x100-core/ [1] Link: https://docs.riscv.org/reference/profiles/rva23/_attachments/rva23-pr= ofile.pdf [2] Acked-by: Krzysztof Kozlowski Reviewed-by: Yixun Lan Reviewed-by: Heinrich Schuchardt Signed-off-by: Guodong Xu Acked-by: Paul Walmsley --- v4: No change. v3: Added Acked-by from Krzysztof. v2: Fixed alphanumeric sorting of compatible strings, put x100 before x60, as per Krzysztof's feedback. Added reviewed-by from Yixun and Heinrich. Updated the commit message to provide more information about X100. --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index d733c0bd534f..5feeb2203050 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -61,6 +61,7 @@ properties: - sifive,u7 - sifive,u74 - sifive,u74-mc + - spacemit,x100 - spacemit,x60 - thead,c906 - thead,c908 --=20 2.43.0 From nobody Sat Feb 7 22:54:50 2026 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2939623817E for ; Sat, 10 Jan 2026 05:19:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.177 ARC-Seal: i=1; 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Fri, 09 Jan 2026 21:19:16 -0800 (PST) Received: from [127.0.1.1] ([45.8.220.108]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a3e3cc88cdsm118208265ad.73.2026.01.09.21.19.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jan 2026 21:19:16 -0800 (PST) From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:14 +0800 Subject: [PATCH v4 02/11] dt-bindings: timer: add SpacemiT K3 CLINT Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260110-k3-basic-dt-v4-2-d492f3a30ffa@riscstar.com> References: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com> In-Reply-To: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Greg Kroah-Hartman , Jiri Slaby , Lubomir Rintel , Yangyu Chen Cc: Paul Walmsley , Conor Dooley , Heinrich Schuchardt , Kevin Meng Zhang , Anup Patel , Andrew Jones , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, linux-serial@vger.kernel.org, Guodong Xu , Conor Dooley X-Mailer: b4 0.14.3 Add compatible string for SpacemiT K3 CLINT. Acked-by: Conor Dooley Signed-off-by: Guodong Xu --- v4: No change. v3: No change. v2: Add Conor's Acked-by. --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Do= cumentation/devicetree/bindings/timer/sifive,clint.yaml index 0d3b8dc362ba..3bab40500df9 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -33,6 +33,7 @@ properties: - eswin,eic7700-clint # ESWIN EIC7700 - sifive,fu540-c000-clint # SiFive FU540 - spacemit,k1-clint # SpacemiT K1 + - spacemit,k3-clint # SpacemiT K3 - starfive,jh7100-clint # StarFive JH7100 - starfive,jh7110-clint # StarFive JH7110 - starfive,jh8100-clint # StarFive JH8100 --=20 2.43.0 From nobody Sat Feb 7 22:54:50 2026 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6F9623817E for ; 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Acked-by: Conor Dooley Signed-off-by: Guodong Xu --- v4: No change. v3: No change. v2: Add Conor's Acked-by. --- Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml | = 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,a= plic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,ap= lic.yaml index bef00521d5da..0718071444d2 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.ya= ml +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.ya= ml @@ -28,6 +28,7 @@ properties: items: - enum: - qemu,aplic + - spacemit,k3-aplic - const: riscv,aplic =20 reg: --=20 2.43.0 From nobody Sat Feb 7 22:54:50 2026 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 185AD2E413 for ; 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Fri, 09 Jan 2026 21:19:38 -0800 (PST) Received: from [127.0.1.1] ([45.8.220.108]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a3e3cc88cdsm118208265ad.73.2026.01.09.21.19.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jan 2026 21:19:38 -0800 (PST) From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:16 +0800 Subject: [PATCH v4 04/11] dt-bindings: interrupt-controller: add SpacemiT K3 IMSIC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260110-k3-basic-dt-v4-4-d492f3a30ffa@riscstar.com> References: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com> In-Reply-To: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Greg Kroah-Hartman , Jiri Slaby , Lubomir Rintel , Yangyu Chen Cc: Paul Walmsley , Conor Dooley , Heinrich Schuchardt , Kevin Meng Zhang , Anup Patel , Andrew Jones , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, linux-serial@vger.kernel.org, Guodong Xu , Krzysztof Kozlowski X-Mailer: b4 0.14.3 Add compatible string for SpacemiT K3 IMSIC. Acked-by: Krzysztof Kozlowski Signed-off-by: Guodong Xu --- v4: No change. v3: Add Acked-by from Krzysztof. v2: Fix the order to keep things alphabetically. --- Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml |= 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,i= msics.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,i= msics.yaml index c23b5c09fdb9..feec122bddde 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.y= aml +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.y= aml @@ -48,6 +48,7 @@ properties: items: - enum: - qemu,imsics + - spacemit,k3-imsics - const: riscv,imsics =20 reg: --=20 2.43.0 From nobody Sat Feb 7 22:54:50 2026 Received: from mail-pg1-f195.google.com (mail-pg1-f195.google.com [209.85.215.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8BF32E54D1 for ; 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Fri, 09 Jan 2026 21:19:49 -0800 (PST) Received: from [127.0.1.1] ([45.8.220.108]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a3e3cc88cdsm118208265ad.73.2026.01.09.21.19.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jan 2026 21:19:48 -0800 (PST) From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:17 +0800 Subject: [PATCH v4 05/11] dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260110-k3-basic-dt-v4-5-d492f3a30ffa@riscstar.com> References: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com> In-Reply-To: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Greg Kroah-Hartman , Jiri Slaby , Lubomir Rintel , Yangyu Chen Cc: Paul Walmsley , Conor Dooley , Heinrich Schuchardt , Kevin Meng Zhang , Anup Patel , Andrew Jones , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, linux-serial@vger.kernel.org, Guodong Xu X-Mailer: b4 0.14.3 Add DT binding documentation for the SpacemiT K3 SoC and the board Pico-ITX which is a 2.5-inch single-board computer. Signed-off-by: Guodong Xu Acked-by: Conor Dooley Reviewed-by: Yixun Lan --- v4: Adjust maintainers list in alphabetic order. Declare spacemit,k3-pico-itx as an enum, which can save future code change when adding new boards. v3: No change. v2: Use one-blank-space between name and email address. --- Documentation/devicetree/bindings/riscv/spacemit.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Docume= ntation/devicetree/bindings/riscv/spacemit.yaml index 9c49482002f7..b958b94a924d 100644 --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml @@ -7,6 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: SpacemiT SoC-based boards =20 maintainers: + - Guodong Xu - Yangyu Chen - Yixun Lan =20 @@ -26,6 +27,10 @@ properties: - xunlong,orangepi-r2s - xunlong,orangepi-rv2 - const: spacemit,k1 + - items: + - enum: + - spacemit,k3-pico-itx + - const: spacemit,k3 =20 additionalProperties: true =20 --=20 2.43.0 From nobody Sat Feb 7 22:54:50 2026 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF81823ABA1 for ; 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Fri, 09 Jan 2026 21:19:58 -0800 (PST) Received: from [127.0.1.1] ([45.8.220.108]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a3e3cc88cdsm118208265ad.73.2026.01.09.21.19.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jan 2026 21:19:58 -0800 (PST) From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:18 +0800 Subject: [PATCH v4 06/11] dt-bindings: riscv: Add B ISA extension description Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260110-k3-basic-dt-v4-6-d492f3a30ffa@riscstar.com> References: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com> In-Reply-To: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Greg Kroah-Hartman , Jiri Slaby , Lubomir Rintel , Yangyu Chen Cc: Paul Walmsley , Conor Dooley , Heinrich Schuchardt , Kevin Meng Zhang , Anup Patel , Andrew Jones , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, linux-serial@vger.kernel.org, Guodong Xu X-Mailer: b4 0.14.3 Add description of the single-letter B extension for Bit Manipulation. B is mandatory for RVA23U64. The B extension is ratified in the 20240411 version of the unprivileged ISA specification. According to the ratified spec, the B standard extension comprises instructions provided by the Zba, Zbb, and Zbs extensions. Add two-way dependency check to enforce that B implies Zba/Zbb/Zbs; and when Zba/Zbb/Zbs (all of them) are specified, then B must be added too. The reason why B/Zba/Zbb/Zbs must coexist at the same time is that unlike other single-letter extensions, B was ratified (Apr/2024) much later than its component extensions Zba/Zbb/Zbs (Jun/2021). When "b" is specified, zba/zbb/zbs must be present to ensure backward compatibility with existing software and kernels that only look for the explicit component strings. When all three components zba/zbb/zbs are specified, "b" should also be present. Making "b" mandatory when all three components are present. Existing devicetrees with zba/zbb/zbs but without "b" will generate warnings that can be fixed in follow-up patches. Signed-off-by: Guodong Xu --- v4: No change. v3: Update the commit message to explain the retionale why B and Zba/Zbb/Zbs should all exist in DT. v2: New patch. --- .../devicetree/bindings/riscv/extensions.yaml | 31 ++++++++++++++++++= ++++ 1 file changed, 31 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index b615083f2544..f671299ac819 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -109,6 +109,13 @@ properties: The standard C extension for compressed instructions, as ratif= ied in the 20191213 version of the unprivileged ISA specification. =20 + - const: b + description: + The standard B extension for bit manipulation instructions, as + ratified in the 20240411 version of the unprivileged ISA + specification. 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Fri, 09 Jan 2026 21:20:08 -0800 (PST) Received: from [127.0.1.1] ([45.8.220.108]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a3e3cc88cdsm118208265ad.73.2026.01.09.21.19.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jan 2026 21:20:08 -0800 (PST) From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:19 +0800 Subject: [PATCH v4 07/11] dt-bindings: riscv: Add descriptions for Za64rs, Ziccamoa, Ziccif, and Zicclsm Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260110-k3-basic-dt-v4-7-d492f3a30ffa@riscstar.com> References: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com> In-Reply-To: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Greg Kroah-Hartman , Jiri Slaby , Lubomir Rintel , Yangyu Chen Cc: Paul Walmsley , Conor Dooley , Heinrich Schuchardt , Kevin Meng Zhang , Anup Patel , Andrew Jones , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, linux-serial@vger.kernel.org, Guodong Xu X-Mailer: b4 0.14.3 Add descriptions for four extensions: Za64rs, Ziccamoa, Ziccif, and Zicclsm. These extensions are ratified in RISC-V Profiles Version 1.0 (commit b1d806605f87 "Updated to ratified state."). They are introduced as new extension names for existing features and regulate implementation details for RISC-V Profile compliance. According to RISC-V Profiles Version 1.0 and RVA23 Profiles Version 1.0, they are mandatory for the following profiles: - za64rs: Mandatory in RVA22U64, RVA23U64 - ziccamoa: Mandatory in RVA20U64, RVA22U64, RVA23U64 - ziccif: Mandatory in RVA20U64, RVA22U64, RVA23U64 - zicclsm: Mandatory in RVA20U64, RVA22U64, RVA23U64 Ziccrse specifies the main memory must support "RsrvEventual", which is one (totally there are four) of the support level for Load-Reserved/ Store-Conditional (LR/SC) atomic instructions. Thus it depends on Zalrsc. Ziccamoa specifies the main memory must support AMOArithmetic, among the four levels of PMA support defined for AMOs in the A extension. Thus it depends on Zaamo. Za64rs defines reservation sets are contiguous, naturally aligned, and a maximum of 64 bytes. Za64rs is consumed by two extensions: Zalrsc and Zawrs. Zawrs itself depends on Zalrsc too. Based on the relationship that "A" =3D Zaamo + Zalrsc, add the following dependencies checks: Za64rs -> Zalrsc or A Ziccrse -> Zalrsc or A Ziccamoa -> Zaamo or A Signed-off-by: Guodong Xu Acked-by: Conor Dooley --- v4: No change. v3: Update the commit message to explain the relationship of Za64rs, Ziccrse, Ziccamoa, Zalrsc and A. Add dependency checks. v2: New patch. --- .../devicetree/bindings/riscv/extensions.yaml | 49 ++++++++++++++++++= ++++ 1 file changed, 49 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index f671299ac819..345624326e9f 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -240,6 +240,12 @@ properties: as ratified at commit 4a69197e5617 ("Update to ratified state"= ) of riscv-svvptc. =20 + - const: za64rs + description: + The standard Za64rs extension for reservation set size of at m= ost + 64 bytes, as ratified in RISC-V Profiles Version 1.0, with com= mit + b1d806605f87 ("Updated to ratified state.") + - const: zaamo description: | The standard Zaamo extension for atomic memory operations as @@ -381,6 +387,27 @@ properties: in commit 64074bc ("Update version numbers for Zfh/Zfinx") of riscv-isa-manual. =20 + - const: ziccamoa + description: + The standard Ziccamoa extension for main memory (cacheability = and + coherence) must support all atomics in A, as ratified in RISC-V + Profiles Version 1.0, with commit b1d806605f87 ("Updated to + ratified state.") + + - const: ziccif + description: + The standard Ziccif extension for main memory (cacheability and + coherence) instruction fetch atomicity, as ratified in RISC-V + Profiles Version 1.0, with commit b1d806605f87 ("Updated to + ratified state.") + + - const: zicclsm + description: + The standard Zicclsm extension for main memory (cacheability a= nd + coherence) must support misaligned loads and stores, as ratifi= ed + in RISC-V Profiles Version 1.0, with commit b1d806605f87 ("Upd= ated + to ratified state.") + - const: ziccrse description: The standard Ziccrse extension which provides forward progress @@ -783,6 +810,18 @@ properties: then: contains: const: b + # Za64rs and Ziccrse depend on Zalrsc or A + - if: + contains: + anyOf: + - const: za64rs + - const: ziccrse + then: + oneOf: + - contains: + const: zalrsc + - contains: + const: a # Zcb depends on Zca - if: contains: @@ -824,6 +863,16 @@ properties: then: contains: const: f + # Ziccamoa depends on Zaamo or A + - if: + contains: + const: ziccamoa + then: + oneOf: + - contains: + const: zaamo + - contains: + const: a # Zvfbfmin depends on V or Zve32f - if: contains: --=20 2.43.0 From nobody Sat Feb 7 22:54:50 2026 Received: from mail-pl1-f194.google.com (mail-pl1-f194.google.com [209.85.214.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B843023817E for ; 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Fri, 09 Jan 2026 21:20:18 -0800 (PST) Received: from [127.0.1.1] ([45.8.220.108]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a3e3cc88cdsm118208265ad.73.2026.01.09.21.20.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jan 2026 21:20:17 -0800 (PST) From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:20 +0800 Subject: [PATCH v4 08/11] dt-bindings: riscv: Add Ssccptr, Sscounterenw, Sstvala, Sstvecd, Ssu64xl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260110-k3-basic-dt-v4-8-d492f3a30ffa@riscstar.com> References: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com> In-Reply-To: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Greg Kroah-Hartman , Jiri Slaby , Lubomir Rintel , Yangyu Chen Cc: Paul Walmsley , Conor Dooley , Heinrich Schuchardt , Kevin Meng Zhang , Anup Patel , Andrew Jones , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, linux-serial@vger.kernel.org, Guodong Xu X-Mailer: b4 0.14.3 Add descriptions for five new extensions: Ssccptr, Sscounterenw, Sstvala, Sstvecd, and Ssu64xl. These extensions are ratified in RISC-V Profiles Version 1.0 (commit b1d806605f87 "Updated to ratified state."). They are introduced as new extension names for existing features and regulate implementation details for RISC-V Profile compliance. According to RISC-V Profiles Version 1.0 and RVA23 Profiles Version 1.0, their requirement status are: - Ssccptr: Mandatory in RVA20S64, RVA22S64, RVA23S64 - Sscounterenw: Mandatory in RVA22S64, RVA23S64 - Sstvala: Mandatory in RVA20S64, RVA22S64, RVA23S64 - Sstvecd: Mandatory in RVA20S64, RVA22S64, RVA23S64 - Ssu64xl: Optional in RVA20S64, RVA22S64; Mandatory in RVA23S64 Signed-off-by: Guodong Xu Acked-by: Conor Dooley --- v4: No change. v3: No change. v2: New patch. --- .../devicetree/bindings/riscv/extensions.yaml | 32 ++++++++++++++++++= ++++ 1 file changed, 32 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 345624326e9f..900270e8d22e 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -161,12 +161,26 @@ properties: behavioural changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of risc= v-aia. =20 + - const: ssccptr + description: | + The standard Ssccptr extension for main memory (cacheability a= nd + coherence) hardware page-table reads, as ratified in RISC-V + Profiles Version 1.0, with commit b1d806605f87 ("Updated to + ratified state.") + - const: sscofpmf description: | The standard Sscofpmf supervisor-level extension for count ove= rflow and mode-based filtering as ratified at commit 01d1df0 ("Add a= bility to manually trigger workflow. (#2)") of riscv-count-overflow. =20 + - const: sscounterenw + description: | + The standard Sscounterenw extension for support writable enabl= es + in scounteren for any supported counter, as ratified in RISC-V + Profiles Version 1.0, with commit b1d806605f87 ("Updated to + ratified state.") + - const: ssnpm description: | The standard Ssnpm extension for next-mode pointer masking as @@ -179,6 +193,24 @@ properties: ratified at commit 3f9ed34 ("Add ability to manually trigger workflow. (#2)") of riscv-time-compare. =20 + - const: sstvala + description: | + The standard Sstvala extension for stval provides all needed v= alues + as ratified in RISC-V Profiles Version 1.0, with commit b1d806= 605f87 + ("Updated to ratified state.") + + - const: sstvecd + description: | + The standard Sstvecd extension for stvec supports Direct mode = as + ratified in RISC-V Profiles Version 1.0, with commit b1d806605= f87 + ("Updated to ratified state.") + + - const: ssu64xl + description: | + The standard Ssu64xl extension for UXLEN=3D64 must be supporte= d, as + ratified in RISC-V Profiles Version 1.0, with commit b1d806605= f87 + ("Updated to ratified state.") + - const: svade description: | The standard Svade supervisor-level extension for SW-managed P= TE A/D --=20 2.43.0 From nobody Sat Feb 7 22:54:50 2026 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47DA22E54D1 for ; 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Fri, 09 Jan 2026 21:20:28 -0800 (PST) Received: from [127.0.1.1] ([45.8.220.108]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a3e3cc88cdsm118208265ad.73.2026.01.09.21.20.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jan 2026 21:20:28 -0800 (PST) From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:21 +0800 Subject: [PATCH v4 09/11] dt-bindings: riscv: Add Sha and its comprised extensions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260110-k3-basic-dt-v4-9-d492f3a30ffa@riscstar.com> References: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com> In-Reply-To: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Greg Kroah-Hartman , Jiri Slaby , Lubomir Rintel , Yangyu Chen Cc: Paul Walmsley , Conor Dooley , Heinrich Schuchardt , Kevin Meng Zhang , Anup Patel , Andrew Jones , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, linux-serial@vger.kernel.org, Guodong Xu X-Mailer: b4 0.14.3 Add descriptions for the Sha extension and the seven extensions it comprises: Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, Shvstvecd, and Ssstateen. Sha is ratified in the RVA23 Profiles Version 1.0 (commit 0273f3c921b6 "rva23/rvb23 ratified") as a new profile-defined extension that captures the full set of features that are mandated to be supported along with the H extension. Extensions Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, Shvstvecd, and Ssstateen are ratified in the RISC-V Profiles Version 1.0 (commit b1d806605f87 "Updated to ratified state"). The requirement status for Sha and its comprised extension in RISC-V Profiles are: - Sha: Mandatory in RVA23S64 - H: Optional in RVA22S64; Mandatory in RVA23S64 - Shcounterenw: Optional in RVA22S64; Mandatory in RVA23S64 - Shgatpa: Optional in RVA22S64; Mandatory in RVA23S64 - Shtvala: Optional in RVA22S64; Mandatory in RVA23S64 - Shvsatpa: Optional in RVA22S64; Mandatory in RVA23S64 - Shvstvala: Optional in RVA22S64; Mandatory in RVA23S64 - Shvstvecd: Optional in RVA22S64; Mandatory in RVA23S64 - Ssstateen: Optional in RVA22S64; Mandatory in RVA23S64 Signed-off-by: Guodong Xu Acked-by: Conor Dooley --- v4: No change. v3: Drop dependency check for Sha. Both Sha and the extensions it implies are allowed to co-exist in DT. v2: New patch. --- .../devicetree/bindings/riscv/extensions.yaml | 57 ++++++++++++++++++= ++++ 1 file changed, 57 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 900270e8d22e..41cb4aeb2667 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -129,6 +129,57 @@ properties: Document Version 20211203. =20 # multi-letter extensions, sorted alphanumerically + - const: sha + description: | + The standard Sha extension for augmented hypervisor extension = as + ratified in RVA23 Profiles Version 1.0, with commit 0273f3c921= b6 + ("rva23/rvb23 ratified"). + + Sha captures the full set of features that are mandated to be + supported along with the H extension. Sha comprises the follow= ing + extensions: H, Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvst= vala, + Shvstvecd, and Ssstateen. + + - const: shcounterenw + description: | + The standard Shcounterenw extension for support writable enabl= es + in hcounteren for any supported counter, as ratified in RISC-V + Profiles Version 1.0, with commit b1d806605f87 ("Updated to + ratified state.") + + - const: shgatpa + description: | + The standard Shgatpa extension indicates that for each support= ed + virtual memory scheme SvNN supported in satp, the corresponding + hgatp SvNNx4 mode must be supported. The hgatp mode Bare must + also be supported. It is ratified in RISC-V Profiles Version 1= .0, + with commit b1d806605f87 ("Updated to ratified state.") + + - const: shtvala + description: | + The standard Shtvala extension for htval be written with the + faulting guest physical address in all circumstances permitted= by + the ISA. It is ratified in RISC-V Profiles Version 1.0, with + commit b1d806605f87 ("Updated to ratified state.") + + - const: shvsatpa + description: | + The standard Shvsatpa extension for vsatp supporting all trans= lation + modes supported in satp, as ratified in RISC-V Profiles Versio= n 1.0, + with commit b1d806605f87 ("Updated to ratified state.") + + - const: shvstvala + description: | + The standard Shvstvala extension for vstval provides all needed + values as ratified in RISC-V Profiles Version 1.0, with commit + b1d806605f87 ("Updated to ratified state.") + + - const: shvstvecd + description: | + The standard Shvstvecd extension for vstvec supporting Direct = mode, + as ratified in RISC-V Profiles Version 1.0, with commit b1d806= 605f87 + ("Updated to ratified state.") + - const: smaia description: | The standard Smaia supervisor-level extension for the advanced @@ -187,6 +238,12 @@ properties: ratified at commit d70011dde6c2 ("Update to ratified state") of riscv-j-extension. =20 + - const: ssstateen + description: | + The standard Ssstateen extension for supervisor-mode view of t= he + state-enable extension, as ratified in RISC-V Profiles Version= 1.0, + with commit b1d806605f87 ("Updated to ratified state.") + - const: sstc description: | The standard Sstc supervisor-level extension for time compare = as --=20 2.43.0 From nobody Sat Feb 7 22:54:50 2026 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9EEE30E0FC for ; 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Fri, 09 Jan 2026 21:20:39 -0800 (PST) Received: from [127.0.1.1] ([45.8.220.108]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a3e3cc88cdsm118208265ad.73.2026.01.09.21.20.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jan 2026 21:20:38 -0800 (PST) From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:22 +0800 Subject: [PATCH v4 10/11] riscv: dts: spacemit: add initial device tree of SpacemiT K3 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260110-k3-basic-dt-v4-10-d492f3a30ffa@riscstar.com> References: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com> In-Reply-To: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Greg Kroah-Hartman , Jiri Slaby , Lubomir Rintel , Yangyu Chen Cc: Paul Walmsley , Conor Dooley , Heinrich Schuchardt , Kevin Meng Zhang , Anup Patel , Andrew Jones , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, linux-serial@vger.kernel.org, Guodong Xu X-Mailer: b4 0.14.3 SpacemiT K3 is equipped with 8 X100 cores, which are RVA23 compliant. Add nodes of uarts, timer and interrupt-controllers. Signed-off-by: Guodong Xu --- v4: Fix missing blank space after commas in compatible string. Add m-mode imsic and aplic node. Reorder properties in simsic, saplic, mimsic, and maplic nodes to match DTS coding style. v3: Remove "supm" from the riscv,isa-extensions list. v2: Remove aliases from k3.dtsi, they should be in board DTS. Updated riscv,isa-extensions with new extensions from the extensions.ya= ml. --- arch/riscv/boot/dts/spacemit/k3.dtsi | 590 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 590 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spa= cemit/k3.dtsi new file mode 100644 index 000000000000..a815f85cf5a6 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -0,0 +1,590 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2025 SpacemiT (Hangzhou) Technology Co. Ltd + * Copyright (c) 2025 Guodong Xu + */ + +#include + +/dts-v1/; + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + model =3D "SpacemiT K3"; + compatible =3D "spacemit,k3"; + + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <24000000>; + + cpu_0: cpu@0 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <0>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu_1: cpu@1 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <1>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu1_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu_2: cpu@2 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <2>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu2_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu_3: cpu@3 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <3>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu3_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu_4: cpu@4 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <4>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu4_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu_5: cpu@5 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <5>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu5_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu_6: cpu@6 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <6>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu6_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu_7: cpu@7 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <7>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu7_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + l2_cache0: cache-controller-0 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <4194304>; + cache-sets =3D <4096>; + cache-unified; + }; + + l2_cache1: cache-controller-1 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <4194304>; + cache-sets =3D <4096>; + cache-unified; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu_0>; + }; + core1 { + cpu =3D <&cpu_1>; + }; + core2 { + cpu =3D <&cpu_2>; + }; + core3 { + cpu =3D <&cpu_3>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu_4>; + }; + core1 { + cpu =3D <&cpu_5>; + }; + core2 { + cpu =3D <&cpu_6>; + }; + core3 { + cpu =3D <&cpu_7>; + }; + }; + }; + }; + + soc: soc { + compatible =3D "simple-bus"; + interrupt-parent =3D <&saplic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-noncoherent; + ranges; + + uart0: serial@d4017000 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017000 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <42 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart2: serial@d4017100 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017100 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <44 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart3: serial@d4017200 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017200 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <45 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart4: serial@d4017300 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017300 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <46 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart5: serial@d4017400 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017400 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <47 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart6: serial@d4017500 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017500 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <48 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart7: serial@d4017600 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017600 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <49 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart8: serial@d4017700 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017700 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <50 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart9: serial@d4017800 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017800 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <51 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart10: serial@d401f000 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd401f000 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <281 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + simsic: interrupt-controller@e0400000 { + compatible =3D "spacemit,k3-imsics", "riscv,imsics"; + reg =3D <0x0 0xe0400000 0x0 0x200000>; + #interrupt-cells =3D <0>; + #msi-cells =3D <0>; + interrupt-controller; + interrupts-extended =3D <&cpu0_intc 9>, <&cpu1_intc 9>, + <&cpu2_intc 9>, <&cpu3_intc 9>, + <&cpu4_intc 9>, <&cpu5_intc 9>, + <&cpu6_intc 9>, <&cpu7_intc 9>; + msi-controller; + riscv,guest-index-bits =3D <6>; + riscv,hart-index-bits =3D <4>; + riscv,num-guest-ids =3D <511>; + riscv,num-ids =3D <511>; + }; + + saplic: interrupt-controller@e0804000 { + compatible =3D "spacemit,k3-aplic", "riscv,aplic"; + reg =3D <0x0 0xe0804000 0x0 0x4000>; + #interrupt-cells =3D <2>; + interrupt-controller; + msi-parent =3D <&simsic>; + riscv,num-sources =3D <512>; + }; + + clint: timer@e081c000 { + compatible =3D "spacemit,k3-clint", "sifive,clint0"; + reg =3D <0x0 0xe081c000 0x0 0x4000>; + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>, + <&cpu5_intc 3>, <&cpu5_intc 7>, + <&cpu6_intc 3>, <&cpu6_intc 7>, + <&cpu7_intc 3>, <&cpu7_intc 7>; + }; + + mimsic: interrupt-controller@f1000000 { + compatible =3D "spacemit,k3-imsics", "riscv,imsics"; + reg =3D <0x0 0xf1000000 0x0 0x10000>; + #interrupt-cells =3D <0>; + #msi-cells =3D <0>; + interrupt-controller; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu1_intc 11>, + <&cpu2_intc 11>, <&cpu3_intc 11>, + <&cpu4_intc 11>, <&cpu5_intc 11>, + <&cpu6_intc 11>, <&cpu7_intc 11>; + msi-controller; + riscv,guest-index-bits =3D <6>; + riscv,hart-index-bits =3D <4>; + riscv,num-guest-ids =3D <511>; + riscv,num-ids =3D <511>; + + status =3D "disabled"; + }; + + maplic: interrupt-controller@f1800000 { + compatible =3D "spacemit,k3-aplic", "riscv,aplic"; + reg =3D <0x0 0xf1800000 0x0 0x4000>; + #interrupt-cells =3D <2>; + interrupt-controller; + msi-parent =3D <&mimsic>; + riscv,children =3D <&saplic>; + riscv,delegate =3D <&saplic 1 512>; + riscv,num-sources =3D <512>; + + status =3D "disabled"; + }; + }; +}; --=20 2.43.0 From nobody Sat Feb 7 22:54:50 2026 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BB663242C8 for ; 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Fri, 09 Jan 2026 21:20:48 -0800 (PST) Received: from [127.0.1.1] ([45.8.220.108]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a3e3cc88cdsm118208265ad.73.2026.01.09.21.20.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jan 2026 21:20:48 -0800 (PST) From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:23 +0800 Subject: [PATCH v4 11/11] riscv: dts: spacemit: add SpacemiT K3 Pico-ITX board device tree Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260110-k3-basic-dt-v4-11-d492f3a30ffa@riscstar.com> References: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com> In-Reply-To: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Daniel Lezcano , Thomas Gleixner , Samuel Holland , Anup Patel , Greg Kroah-Hartman , Jiri Slaby , Lubomir Rintel , Yangyu Chen Cc: Paul Walmsley , Conor Dooley , Heinrich Schuchardt , Kevin Meng Zhang , Anup Patel , Andrew Jones , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, linux-serial@vger.kernel.org, Guodong Xu X-Mailer: b4 0.14.3 K3 Pico-ITX is a 2.5-inch single-board computer equipted with a SpacemiT K3 SoC. This minimal device tree enables booting into a serial console with UART output. Signed-off-by: Guodong Xu --- v4: No change. v3: No change. v2: Add aliases node in this board DT. Update the memory node to reflect the hardware truth. Address starts at 0x100000000 (4G) boundary. --- arch/riscv/boot/dts/spacemit/Makefile | 1 + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 38 ++++++++++++++++++++++++= ++++ 2 files changed, 39 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/sp= acemit/Makefile index 95889e7269d1..7e2b87702571 100644 --- a/arch/riscv/boot/dts/spacemit/Makefile +++ b/arch/riscv/boot/dts/spacemit/Makefile @@ -4,3 +4,4 @@ dtb-$(CONFIG_ARCH_SPACEMIT) +=3D k1-milkv-jupiter.dtb dtb-$(CONFIG_ARCH_SPACEMIT) +=3D k1-musepi-pro.dtb dtb-$(CONFIG_ARCH_SPACEMIT) +=3D k1-orangepi-r2s.dtb dtb-$(CONFIG_ARCH_SPACEMIT) +=3D k1-orangepi-rv2.dtb +dtb-$(CONFIG_ARCH_SPACEMIT) +=3D k3-pico-itx.dtb diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot= /dts/spacemit/k3-pico-itx.dts new file mode 100644 index 000000000000..037ce757e5bc --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2025 SpacemiT (Hangzhou) Technology Co. Ltd + * Copyright (c) 2025 Guodong Xu + */ + +#include "k3.dtsi" + +/ { + model =3D "SpacemiT K3 Pico-ITX"; + compatible =3D "spacemit,k3-pico-itx", "spacemit,k3"; + + aliases { + serial0 =3D &uart0; + serial2 =3D &uart2; + serial3 =3D &uart3; + serial4 =3D &uart4; + serial5 =3D &uart5; + serial6 =3D &uart6; + serial7 =3D &uart7; + serial8 =3D &uart8; + serial9 =3D &uart9; + serial10 =3D &uart10; + }; + + chosen { + stdout-path =3D "serial0"; + }; + + memory@100000000 { + device_type =3D "memory"; + reg =3D <0x1 0x00000000 0x4 0x00000000>; + }; +}; + +&uart0 { + status =3D "okay"; +}; --=20 2.43.0