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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next v2 2/2] net: pcs: rzn1-miic: Add support for PHY link active-level configuration Date: Fri, 9 Jan 2026 14:22:50 +0000 Message-ID: <20260109142250.3313448-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260109142250.3313448-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260109142250.3313448-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add support to configure the PHY link signal active level per converter using the DT property "renesas,miic-phylink-active-low". Introduce the MIIC_PHYLINK register definition and extend the MIIC driver with a new `phylink` structure to store the mask and value for PHY link configuration. Implement `miic_configure_phylink()` to determine the bit position and polarity for each port based on the SoC type, such as RZ/N1 or RZ/T2H/N2H. The accumulated configuration is stored during DT parsing and applied later in `miic_probe()` after hardware initialization, since the MIIC registers can only be modified safely once the hardware setup is complete. Signed-off-by: Lad Prabhakar --- v1->v2: - No changes. --- drivers/net/pcs/pcs-rzn1-miic.c | 108 +++++++++++++++++++++++++++++++- 1 file changed, 106 insertions(+), 2 deletions(-) diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-mii= c.c index 885f17c32643..cc090f27e559 100644 --- a/drivers/net/pcs/pcs-rzn1-miic.c +++ b/drivers/net/pcs/pcs-rzn1-miic.c @@ -28,6 +28,8 @@ =20 #define MIIC_MODCTRL 0x8 =20 +#define MIIC_PHYLINK 0x14 + #define MIIC_CONVCTRL(port) (0x100 + (port) * 4) =20 #define MIIC_CONVCTRL_CONV_SPEED GENMASK(1, 0) @@ -177,6 +179,16 @@ static const char * const rzt2h_reset_ids[] =3D { "crst", }; =20 +/** + * struct phylink - Phylink configuration + * @mask: Mask of phylink bits + * @val: Value of phylink bits + */ +struct phylink { + u32 mask; + u32 val; +}; + /** * struct miic - MII converter structure * @base: base address of the MII converter @@ -184,6 +196,7 @@ static const char * const rzt2h_reset_ids[] =3D { * @lock: Lock used for read-modify-write access * @rsts: Reset controls for the MII converter * @of_data: Pointer to OF data + * @phylink: Phylink configuration */ struct miic { void __iomem *base; @@ -191,6 +204,12 @@ struct miic { spinlock_t lock; struct reset_control_bulk_data rsts[MIIC_MAX_NUM_RSTS]; const struct miic_of_data *of_data; + struct phylink phylink; +}; + +enum miic_type { + MIIC_TYPE_RZN1, + MIIC_TYPE_RZT2H, }; =20 /** @@ -210,6 +229,7 @@ struct miic { * @init_unlock_lock_regs: Flag to indicate if registers need to be unlock= ed * before access. * @miic_write: Function pointer to write a value to a MIIC register + * @type: Type of MIIC */ struct miic_of_data { struct modctrl_match *match_table; @@ -226,6 +246,7 @@ struct miic_of_data { u8 reset_count; bool init_unlock_lock_regs; void (*miic_write)(struct miic *miic, int offset, u32 value); + enum miic_type type; }; =20 /** @@ -581,10 +602,82 @@ static int miic_match_dt_conf(struct miic *miic, s8 *= dt_val, u32 *mode_cfg) return -EINVAL; } =20 +static void miic_configure_phylink(struct miic *miic, u32 conf, + u32 port, bool active_low) +{ + bool polarity_active_high; + u32 mask, val; + int shift; + + /* determine shift and polarity for this conf */ + if (miic->of_data->type =3D=3D MIIC_TYPE_RZN1) { + switch (conf) { + /* switch ports =3D> bits [3:0] (shift 0), active when low */ + case MIIC_SWITCH_PORTA: + case MIIC_SWITCH_PORTB: + case MIIC_SWITCH_PORTC: + case MIIC_SWITCH_PORTD: + shift =3D 0; + polarity_active_high =3D false; + break; + + /* EtherCAT ports =3D> bits [7:4] (shift 4), active when high */ + case MIIC_ETHERCAT_PORTA: + case MIIC_ETHERCAT_PORTB: + case MIIC_ETHERCAT_PORTC: + shift =3D 4; + polarity_active_high =3D true; + break; + + /* Sercos ports =3D> bits [11:8] (shift 8), active when high */ + case MIIC_SERCOS_PORTA: + case MIIC_SERCOS_PORTB: + shift =3D 8; + polarity_active_high =3D true; + break; + + default: + return; + } + } else { + switch (conf) { + /* ETHSW ports =3D> bits [3:0] (shift 0), active when low */ + case ETHSS_ETHSW_PORT0: + case ETHSS_ETHSW_PORT1: + case ETHSS_ETHSW_PORT2: + shift =3D 0; + polarity_active_high =3D false; + break; + + /* ESC ports =3D> bits [7:4] (shift 4), active when high */ + case ETHSS_ESC_PORT0: + case ETHSS_ESC_PORT1: + case ETHSS_ESC_PORT2: + shift =3D 4; + polarity_active_high =3D true; + break; + + default: + return; + } + } + + mask =3D BIT(port) << shift; + + if (polarity_active_high) + val =3D (active_low ? 0 : BIT(port)) << shift; + else + val =3D (active_low ? BIT(port) : 0) << shift; + + miic->phylink.mask |=3D mask; + miic->phylink.val =3D (miic->phylink.val & ~mask) | (val & mask); +} + static int miic_parse_dt(struct miic *miic, u32 *mode_cfg) { struct device_node *np =3D miic->dev->of_node; struct device_node *conv; + bool active_low; int port, ret; s8 *dt_val; u32 conf; @@ -605,8 +698,15 @@ static int miic_parse_dt(struct miic *miic, u32 *mode_= cfg) =20 /* Adjust for 0 based index */ port +=3D !miic->of_data->miic_port_start; - if (of_property_read_u32(conv, "renesas,miic-input", &conf) =3D=3D 0) - dt_val[port] =3D conf; + if (of_property_read_u32(conv, "renesas,miic-input", &conf)) + continue; + + dt_val[port] =3D conf; + + active_low =3D of_property_read_bool(conv, "renesas,miic-phylink-active-= low"); + + miic_configure_phylink(miic, conf, port - !miic->of_data->miic_port_star= t, + active_low); } =20 ret =3D miic_match_dt_conf(miic, dt_val, mode_cfg); @@ -696,6 +796,8 @@ static int miic_probe(struct platform_device *pdev) if (ret) goto disable_runtime_pm; =20 + miic_reg_rmw(miic, MIIC_PHYLINK, miic->phylink.mask, miic->phylink.val); + /* miic_create() relies on that fact that data are attached to the * platform device to determine if the driver is ready so this needs to * be the last thing to be done after everything is initialized @@ -729,6 +831,7 @@ static struct miic_of_data rzn1_miic_of_data =3D { .sw_mode_mask =3D GENMASK(4, 0), .init_unlock_lock_regs =3D true, .miic_write =3D miic_reg_writel_unlocked, + .type =3D MIIC_TYPE_RZN1, }; =20 static struct miic_of_data rzt2h_miic_of_data =3D { @@ -745,6 +848,7 @@ static struct miic_of_data rzt2h_miic_of_data =3D { .reset_ids =3D rzt2h_reset_ids, .reset_count =3D ARRAY_SIZE(rzt2h_reset_ids), .miic_write =3D miic_reg_writel_locked, + .type =3D MIIC_TYPE_RZT2H, }; =20 static const struct of_device_id miic_of_mtable[] =3D { --=20 2.52.0