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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next v2 1/2] dt-bindings: net: pcs: renesas,rzn1-miic: Add renesas,miic-phylink-active-low property Date: Fri, 9 Jan 2026 14:22:49 +0000 Message-ID: <20260109142250.3313448-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260109142250.3313448-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260109142250.3313448-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add the renesas,miic-phylink-active-low property to allow configuring the active level of PHY link status signals provided by the MIIC block. EtherPHY link-up and link-down status is required as a hardware feature independent of whether GMAC or ETHSW is used. With GMAC, link status is obtained via MDC/MDIO and handled in software. In contrast, ETHSW exposes dedicated PHY link pins that provide this information directly in hardware. These PHY link signals are required not only for host-controlled traffic but also for switch-only forwarding paths where frames are exchanged between external nodes without CPU involvement. This is particularly important for redundancy protocols such as DLR (Device Level Ring), which depend on fast detection of link-down events caused by cable or port failures. Handling such events purely in software introduces latency, which is why ETHSW provides dedicated hardware link pins. Signed-off-by: Lad Prabhakar Acked-by: Rob Herring (Arm) --- v1->v2: - Updated commit message to elaborate the necessity of PHY link signals. --- .../devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.ya= ml b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml index 3adbcf56d2be..825ae8a91e8b 100644 --- a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml +++ b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml @@ -86,6 +86,13 @@ patternProperties: and include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h for RZ/= N2H, RZ/T2H SoCs. $ref: /schemas/types.yaml#/definitions/uint32 =20 + renesas,miic-phylink-active-low: + type: boolean + description: Indicates that the PHY-link signal provided by the Et= hernet switch, + EtherCAT, or SERCOS3 interface is active low. When present, this= property + sets the corresponding signal polarity to active low. When omitt= ed, the signal + defaults to active high. + required: - reg - renesas,miic-input --=20 2.52.0