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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next v2 1/2] dt-bindings: net: pcs: renesas,rzn1-miic: Add renesas,miic-phylink-active-low property Date: Fri, 9 Jan 2026 14:22:49 +0000 Message-ID: <20260109142250.3313448-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260109142250.3313448-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260109142250.3313448-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add the renesas,miic-phylink-active-low property to allow configuring the active level of PHY link status signals provided by the MIIC block. EtherPHY link-up and link-down status is required as a hardware feature independent of whether GMAC or ETHSW is used. With GMAC, link status is obtained via MDC/MDIO and handled in software. In contrast, ETHSW exposes dedicated PHY link pins that provide this information directly in hardware. These PHY link signals are required not only for host-controlled traffic but also for switch-only forwarding paths where frames are exchanged between external nodes without CPU involvement. This is particularly important for redundancy protocols such as DLR (Device Level Ring), which depend on fast detection of link-down events caused by cable or port failures. Handling such events purely in software introduces latency, which is why ETHSW provides dedicated hardware link pins. Signed-off-by: Lad Prabhakar Acked-by: Rob Herring (Arm) --- v1->v2: - Updated commit message to elaborate the necessity of PHY link signals. --- .../devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.ya= ml b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml index 3adbcf56d2be..825ae8a91e8b 100644 --- a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml +++ b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml @@ -86,6 +86,13 @@ patternProperties: and include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h for RZ/= N2H, RZ/T2H SoCs. $ref: /schemas/types.yaml#/definitions/uint32 =20 + renesas,miic-phylink-active-low: + type: boolean + description: Indicates that the PHY-link signal provided by the Et= hernet switch, + EtherCAT, or SERCOS3 interface is active low. When present, this= property + sets the corresponding signal polarity to active low. When omitt= ed, the signal + defaults to active high. + required: - reg - renesas,miic-input --=20 2.52.0 From nobody Mon Feb 9 13:46:38 2026 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0304435C196 for ; Fri, 9 Jan 2026 14:23:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767968587; cv=none; b=F4jXT1XoFW+JWyq6d1WT8Re4HynA9wkNTkPmCIVZgeTkJ0RDqdgbPeisEYlPkvuukQCmmoS2hkyzyWuG4ixSN+zdzdrhgwMJUCU/RYO+hmTz9k+N2UgYrcvT0H6Aqt1AabcGrmvrrCO6VV9Kgp6hZ4RCOakbbxR7HdUc8fwEgPE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767968587; c=relaxed/simple; bh=IZX0GyFDL7t70J/Ljr/Ww9EPikfNIA5b00sjzTAqWpU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ghgp7RL2wY2RINToKnQODot/vDfno6TOzr48PyFWSIykw8BXnaW59wEVaYOb4yM++qorVCoCufL68+3ROHElwqpFdjI3MZ+XwES7vUvDSaPyYbHPtLLTWmH7iDWMVSkL5AGUoM2obBlmFftnHSdRevyVFkYiZMGM8eqO0pf5hdY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=JHVb+DEb; arc=none smtp.client-ip=209.85.128.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="JHVb+DEb" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-4779a4fc95aso16173195e9.1 for ; Fri, 09 Jan 2026 06:23:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1767968583; x=1768573383; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GJuTI/pP3gTuIvrfb63LlTSw7eNSK1HBmiLz7uaNHpI=; b=JHVb+DEbPsUUdQ3cNFP1ezBmkMcT6jWEl5c/QP7+37dKQ8hLV1AF7H/rMwKWV/a9ZM UE9atsV6eVXjU32O0N5KgQbBxRrUx/lOxzruizKkgSzrjPbhMGu3kJ6KqKVOsi6o71vY fMytUL9+E5YHW45k1zUrlXIELR0/4bqFs/Z5maZsTsoO2p3naxAE0QSmnzf8RzfTOZSF d0M9uKdkmCH9Ni6dPYT6wUKoEdjsj7w8xaSqgeuWOulBayCuKXdVRa0P2WHVeHkSp1mY Ny0QXLdX/Ze74F9C6rnsY2vL7D+6CXBF5V/K8IGJtq84JZGf48ha6zWXoQI7QYtFL59G YcNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767968583; x=1768573383; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=GJuTI/pP3gTuIvrfb63LlTSw7eNSK1HBmiLz7uaNHpI=; b=aP9JFHFTI1mmSF1HvHpFAy4yDZho/wRQuHMGmKVrxlR+mWlCQMG9gIRAe22mky5GsO nueyYVS84iKu4X1f9yP5kJlsiSlcU8A7NY9/2L7e9PRraQJo/llTkWGh7TsNvwa8KZRf oG0REERlpHRXN9w1tg5ljnKYe8Lo+ocDjhawg4UtTvjg9oajwAY8Bogpdp8dT4DCx0Ra TrE360AhJbiqp0Xr/ndbTx872hDY0yy6Qqgdg4Enlx2MT21TLX9b195hMXJl2XMT/xdu qWWmdKLFj8350b/hlNmMibKnkof2OZ06VcN7UgTK2D79/0VuvxQwVTIF78pHDcZ1iAlI LTxg== X-Forwarded-Encrypted: i=1; AJvYcCWUUcKBc618JIss4+UuD9dfBzR/9hDaFTr7hRa2PDZFq651BG+YuDApT7NsTsv2h2/2FG2tCaA68VeBcv8=@vger.kernel.org X-Gm-Message-State: AOJu0Ywffva88KIFDO+XOzidN34MvOt/kfGwSkNPVuN9I2UN1/6Ae0m7 OBBYj6ayNNHZ1fVbvTEVnSKSIGIoz63h7D421ySwJDhKDo/sjmgMgyoD X-Gm-Gg: AY/fxX4u4JRyFXPXda/qE9OIC3gSSrJglpY0J9PdzJ8A/ps7iUz2eTz/cuXGZKgyllq 5SAcDVaL0So76r5hv2x8WAJJI5UdE10szAJ3xQJ5Nzi/AVi13GJEOY7x8d9c2MwYaEOBmXlBEcE dk2LVAAIsAPj3mNaVxD35rPX9Xk5fA+CVBFqsLJhklvJlY/T82h8yH+Ntt9T2K9jJIrHvOSkux0 zWxGL8z0Om2nJf0pZY0w0PcwGKbDcb309076AKNG7+wJwI4jRSirPE6AHo7UxgoCLM2TXnFTUDL CGNl4IRwyCIkvVZqQUA4dCe7NIM7ftnGb2I3x8bbSewaT7pNFhw3p0q2/ZT4T65+5Xkprzlq/Jg UM6rYjfx0rLZNgQB191qROrax+BtRJpiRu4oF7gWIf6elCuMicTLdrFSwwdGUNxXQ9T6c/segIE BzlTPi6R/lbyujLh2sKSiivNUMMXjgf0I26gWd+bjo4eJXDpIkQ9sB9nGa7aVRi6596B0YzyAPy gAgWkuaQwQOmhOxNxim4Ko= X-Google-Smtp-Source: AGHT+IHuqWKzRFHwggueYURnOwU1f6nLlo3Dx/aAg2AtNERz9s/rUtlR+rwtsB4ngafpJcpJ++sTBg== X-Received: by 2002:a05:600c:3541:b0:477:9fa0:7495 with SMTP id 5b1f17b1804b1-47d848787e3mr127679765e9.14.1767968583016; Fri, 09 Jan 2026 06:23:03 -0800 (PST) Received: from iku.Home ([2a06:5906:61b:2d00:3d06:ce2:401e:8cb8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47d871a1e11sm61448855e9.19.2026.01.09.06.23.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jan 2026 06:23:02 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next v2 2/2] net: pcs: rzn1-miic: Add support for PHY link active-level configuration Date: Fri, 9 Jan 2026 14:22:50 +0000 Message-ID: <20260109142250.3313448-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260109142250.3313448-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260109142250.3313448-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add support to configure the PHY link signal active level per converter using the DT property "renesas,miic-phylink-active-low". Introduce the MIIC_PHYLINK register definition and extend the MIIC driver with a new `phylink` structure to store the mask and value for PHY link configuration. Implement `miic_configure_phylink()` to determine the bit position and polarity for each port based on the SoC type, such as RZ/N1 or RZ/T2H/N2H. The accumulated configuration is stored during DT parsing and applied later in `miic_probe()` after hardware initialization, since the MIIC registers can only be modified safely once the hardware setup is complete. Signed-off-by: Lad Prabhakar --- v1->v2: - No changes. --- drivers/net/pcs/pcs-rzn1-miic.c | 108 +++++++++++++++++++++++++++++++- 1 file changed, 106 insertions(+), 2 deletions(-) diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-mii= c.c index 885f17c32643..cc090f27e559 100644 --- a/drivers/net/pcs/pcs-rzn1-miic.c +++ b/drivers/net/pcs/pcs-rzn1-miic.c @@ -28,6 +28,8 @@ =20 #define MIIC_MODCTRL 0x8 =20 +#define MIIC_PHYLINK 0x14 + #define MIIC_CONVCTRL(port) (0x100 + (port) * 4) =20 #define MIIC_CONVCTRL_CONV_SPEED GENMASK(1, 0) @@ -177,6 +179,16 @@ static const char * const rzt2h_reset_ids[] =3D { "crst", }; =20 +/** + * struct phylink - Phylink configuration + * @mask: Mask of phylink bits + * @val: Value of phylink bits + */ +struct phylink { + u32 mask; + u32 val; +}; + /** * struct miic - MII converter structure * @base: base address of the MII converter @@ -184,6 +196,7 @@ static const char * const rzt2h_reset_ids[] =3D { * @lock: Lock used for read-modify-write access * @rsts: Reset controls for the MII converter * @of_data: Pointer to OF data + * @phylink: Phylink configuration */ struct miic { void __iomem *base; @@ -191,6 +204,12 @@ struct miic { spinlock_t lock; struct reset_control_bulk_data rsts[MIIC_MAX_NUM_RSTS]; const struct miic_of_data *of_data; + struct phylink phylink; +}; + +enum miic_type { + MIIC_TYPE_RZN1, + MIIC_TYPE_RZT2H, }; =20 /** @@ -210,6 +229,7 @@ struct miic { * @init_unlock_lock_regs: Flag to indicate if registers need to be unlock= ed * before access. * @miic_write: Function pointer to write a value to a MIIC register + * @type: Type of MIIC */ struct miic_of_data { struct modctrl_match *match_table; @@ -226,6 +246,7 @@ struct miic_of_data { u8 reset_count; bool init_unlock_lock_regs; void (*miic_write)(struct miic *miic, int offset, u32 value); + enum miic_type type; }; =20 /** @@ -581,10 +602,82 @@ static int miic_match_dt_conf(struct miic *miic, s8 *= dt_val, u32 *mode_cfg) return -EINVAL; } =20 +static void miic_configure_phylink(struct miic *miic, u32 conf, + u32 port, bool active_low) +{ + bool polarity_active_high; + u32 mask, val; + int shift; + + /* determine shift and polarity for this conf */ + if (miic->of_data->type =3D=3D MIIC_TYPE_RZN1) { + switch (conf) { + /* switch ports =3D> bits [3:0] (shift 0), active when low */ + case MIIC_SWITCH_PORTA: + case MIIC_SWITCH_PORTB: + case MIIC_SWITCH_PORTC: + case MIIC_SWITCH_PORTD: + shift =3D 0; + polarity_active_high =3D false; + break; + + /* EtherCAT ports =3D> bits [7:4] (shift 4), active when high */ + case MIIC_ETHERCAT_PORTA: + case MIIC_ETHERCAT_PORTB: + case MIIC_ETHERCAT_PORTC: + shift =3D 4; + polarity_active_high =3D true; + break; + + /* Sercos ports =3D> bits [11:8] (shift 8), active when high */ + case MIIC_SERCOS_PORTA: + case MIIC_SERCOS_PORTB: + shift =3D 8; + polarity_active_high =3D true; + break; + + default: + return; + } + } else { + switch (conf) { + /* ETHSW ports =3D> bits [3:0] (shift 0), active when low */ + case ETHSS_ETHSW_PORT0: + case ETHSS_ETHSW_PORT1: + case ETHSS_ETHSW_PORT2: + shift =3D 0; + polarity_active_high =3D false; + break; + + /* ESC ports =3D> bits [7:4] (shift 4), active when high */ + case ETHSS_ESC_PORT0: + case ETHSS_ESC_PORT1: + case ETHSS_ESC_PORT2: + shift =3D 4; + polarity_active_high =3D true; + break; + + default: + return; + } + } + + mask =3D BIT(port) << shift; + + if (polarity_active_high) + val =3D (active_low ? 0 : BIT(port)) << shift; + else + val =3D (active_low ? BIT(port) : 0) << shift; + + miic->phylink.mask |=3D mask; + miic->phylink.val =3D (miic->phylink.val & ~mask) | (val & mask); +} + static int miic_parse_dt(struct miic *miic, u32 *mode_cfg) { struct device_node *np =3D miic->dev->of_node; struct device_node *conv; + bool active_low; int port, ret; s8 *dt_val; u32 conf; @@ -605,8 +698,15 @@ static int miic_parse_dt(struct miic *miic, u32 *mode_= cfg) =20 /* Adjust for 0 based index */ port +=3D !miic->of_data->miic_port_start; - if (of_property_read_u32(conv, "renesas,miic-input", &conf) =3D=3D 0) - dt_val[port] =3D conf; + if (of_property_read_u32(conv, "renesas,miic-input", &conf)) + continue; + + dt_val[port] =3D conf; + + active_low =3D of_property_read_bool(conv, "renesas,miic-phylink-active-= low"); + + miic_configure_phylink(miic, conf, port - !miic->of_data->miic_port_star= t, + active_low); } =20 ret =3D miic_match_dt_conf(miic, dt_val, mode_cfg); @@ -696,6 +796,8 @@ static int miic_probe(struct platform_device *pdev) if (ret) goto disable_runtime_pm; =20 + miic_reg_rmw(miic, MIIC_PHYLINK, miic->phylink.mask, miic->phylink.val); + /* miic_create() relies on that fact that data are attached to the * platform device to determine if the driver is ready so this needs to * be the last thing to be done after everything is initialized @@ -729,6 +831,7 @@ static struct miic_of_data rzn1_miic_of_data =3D { .sw_mode_mask =3D GENMASK(4, 0), .init_unlock_lock_regs =3D true, .miic_write =3D miic_reg_writel_unlocked, + .type =3D MIIC_TYPE_RZN1, }; =20 static struct miic_of_data rzt2h_miic_of_data =3D { @@ -745,6 +848,7 @@ static struct miic_of_data rzt2h_miic_of_data =3D { .reset_ids =3D rzt2h_reset_ids, .reset_count =3D ARRAY_SIZE(rzt2h_reset_ids), .miic_write =3D miic_reg_writel_locked, + .type =3D MIIC_TYPE_RZT2H, }; =20 static const struct of_device_id miic_of_mtable[] =3D { --=20 2.52.0