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Fri, 09 Jan 2026 10:45:19 +0000 (GMT) Received: from pps.filterd (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 609AjHeD007216; Fri, 9 Jan 2026 10:45:17 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 4bev6mpxxv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 09 Jan 2026 10:45:17 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 609AjGLT007202; Fri, 9 Jan 2026 10:45:16 GMT Received: from cse-cd02-lnx.ap.qualcomm.com (smtphost-taiwan.qualcomm.com [10.249.136.33]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 609AjGiK007195 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 09 Jan 2026 10:45:16 +0000 Received: by cse-cd02-lnx.ap.qualcomm.com (Postfix, from userid 4438065) id 0293277E; Fri, 9 Jan 2026 18:45:15 +0800 (CST) From: Ziyue Zhang To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ziyue.zhang@oss.qualcomm.com, jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org, kishon@kernel.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, kw@linux.com Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com Subject: [PATCH v4 1/3] arm64: dts: qcom: hamoa: Move PHY, PERST, and Wake GPIOs to PCIe port nodes and add port Nodes for all PCIe ports Date: Fri, 9 Jan 2026 18:45:02 +0800 Message-Id: <20260109104504.3147745-2-ziyue.zhang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260109104504.3147745-1-ziyue.zhang@oss.qualcomm.com> References: <20260109104504.3147745-1-ziyue.zhang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA5MDA3OCBTYWx0ZWRfXzXpu1DDYh7Wh XMf+PaIta7OWnPn9FmtZIJefmrh7ArhCDN8mXLy6j6Ii4k/l0GI7W5+827cNy9xWZgF4zdl+Vns GBxqhyk4A3WS/3sEQr1X4ANycniY9lOVkAMHNd3RTaV2VnfjGLJJuSzt44D7N2Km8tNIjkg6kyx wVRQjf1WAMj+AS81tgJRJX2vGdEQCzga80YkvXsrxD7n/F5EZROeLx178gL1eD1GJmADcYr864L ekCc4Yih9QaJIr6UncVe6InRAhDAojd8HXl4VWFRZ4pDnP+EjxpYoCWG7y7gh0ps126jehgvzfy 8bl3H58JdXF091ljMRgA5vCqCCd5dqREwmP0dgyH6jFcKvmhHMpA4Q95She0+9Gf43F7yJ+Vp37 Tje1XB6ROfIHMepUDFI7qS+r6lbY45M+2iAn4FF0tZXb1qSPv47wgd5B6YFK3r5G2unwoQ6Igjl xkZw+GNnnrc+4sjC5/Q== X-Proofpoint-ORIG-GUID: 3HaNlheKjElwUT99LnPjCtvnD2mMpzav X-Proofpoint-GUID: 3HaNlheKjElwUT99LnPjCtvnD2mMpzav X-Authority-Analysis: v=2.4 cv=QPFlhwLL c=1 sm=1 tr=0 ts=6960dc3f cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=vUbySO9Y5rIA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=aKaZ7cjhLP4wjK1lvm8A:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-09_03,2026-01-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 adultscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601090078 Content-Type: text/plain; charset="utf-8" Since describing the PCIe PHY directly under the RC node is now deprecated, move the references to the respective PCIe port nodes, creating them where necessary.Also add port nodes for PCIe5 and PCIe6a with proper PHY references. And also move the PCIe PERST and wake GPIOs from the controller nodes to the corresponding PCIe port nodes on Hamoa-based platforms: - x1e001de-devkit - x1e78100-lenovo-thinkpad-t14s - x1e80100-asus-vivobook-s15 - x1e80100-asus-zenbook-a14 - x1e80100-dell-xps13-9345 - x1e80100-lenovo-yoga-slim7x - x1e80100-microsoft-romulus - x1e80100-qcp Signed-off-by: Ziyue Zhang Reviewed-by: Dmitry Baryshkov Reviewed-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 42 +++++++++++++------ arch/arm64/boot/dts/qcom/x1e001de-devkit.dts | 24 +++++++---- .../qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 24 +++++++---- .../dts/qcom/x1e80100-asus-vivobook-s15.dts | 14 ++++--- .../dts/qcom/x1e80100-asus-zenbook-a14.dts | 3 ++ .../dts/qcom/x1e80100-dell-xps13-9345.dts | 14 ++++--- .../dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 8 ++-- .../dts/qcom/x1e80100-microsoft-romulus.dtsi | 19 ++++++--- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 21 ++++++---- 9 files changed, 108 insertions(+), 61 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom= /hamoa.dtsi index a559f6340af9..f464ff3b89cb 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -3261,9 +3261,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, =20 power-domains =3D <&gcc GCC_PCIE_3_GDSC>; =20 - phys =3D <&pcie3_phy>; - phy-names =3D "pciephy"; - eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555 0x5555 0x5555 0x5555 0x5555 0x5555 0x5555>; eq-presets-16gts =3D /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; @@ -3404,12 +3401,14 @@ opp-128000000-4 { }; }; =20 - pcie3_port: pcie@0 { + pcie3_port0: pcie@0 { device_type =3D "pci"; compatible =3D "pciclass,0604"; reg =3D <0x0 0x0 0x0 0x0 0x0>; bus-range =3D <0x01 0xff>; =20 + phys =3D <&pcie3_phy>; + #address-cells =3D <3>; #size-cells =3D <2>; ranges; @@ -3538,13 +3537,22 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, power-domains =3D <&gcc GCC_PCIE_6A_GDSC>; required-opps =3D <&rpmhpd_opp_nom>; =20 - phys =3D <&pcie6a_phy>; - phy-names =3D "pciephy"; - eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; eq-presets-16gts =3D /bits/ 8 <0x55 0x55 0x55 0x55>; =20 status =3D "disabled"; + + pcie6a_port0: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + phys =3D <&pcie6a_phy>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; }; =20 pcie6a_phy: phy@1bfc000 { @@ -3670,12 +3678,21 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, power-domains =3D <&gcc GCC_PCIE_5_GDSC>; required-opps =3D <&rpmhpd_opp_nom>; =20 - phys =3D <&pcie5_phy>; - phy-names =3D "pciephy"; - eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555>; =20 status =3D "disabled"; + + pcie5_port0: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + phys =3D <&pcie5_phy>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; }; =20 pcie5_phy: phy@1c06000 { @@ -3800,9 +3817,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, power-domains =3D <&gcc GCC_PCIE_4_GDSC>; required-opps =3D <&rpmhpd_opp_nom>; =20 - phys =3D <&pcie4_phy>; - phy-names =3D "pciephy"; - eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555>; =20 status =3D "disabled"; @@ -3812,6 +3826,8 @@ pcie4_port0: pcie@0 { reg =3D <0x0 0x0 0x0 0x0 0x0>; bus-range =3D <0x01 0xff>; =20 + phys =3D <&pcie4_phy>; + #address-cells =3D <3>; #size-cells =3D <2>; ranges; diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot= /dts/qcom/x1e001de-devkit.dts index a9643cd746d5..d5a60671a383 100644 --- a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -1003,9 +1003,6 @@ &mdss_dp2_out { }; =20 &pcie4 { - perst-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; - pinctrl-0 =3D <&pcie4_default>; pinctrl-names =3D "default"; =20 @@ -1019,10 +1016,12 @@ &pcie4_phy { status =3D "okay"; }; =20 -&pcie5 { - perst-gpios =3D <&tlmm 149 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 151 GPIO_ACTIVE_LOW>; +&pcie4_port0 { + reset-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; +}; =20 +&pcie5 { vddpe-3v3-supply =3D <&vreg_wwan>; =20 pinctrl-0 =3D <&pcie5_default>; @@ -1038,10 +1037,12 @@ &pcie5_phy { status =3D "okay"; }; =20 -&pcie6a { - perst-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; +&pcie5_port0 { + reset-gpios =3D <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 151 GPIO_ACTIVE_LOW>; +}; =20 +&pcie6a { vddpe-3v3-supply =3D <&vreg_nvme>; =20 pinctrl-names =3D "default"; @@ -1057,6 +1058,11 @@ &pcie6a_phy { status =3D "okay"; }; =20 +&pcie6a_port0 { + reset-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + &pm8550_gpios { rtmr0_default: rtmr0-reset-n-active-state { pins =3D "gpio10"; diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/= arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index 7aee9a20c6df..b45e377a22c6 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -1113,9 +1113,6 @@ &mdss_dp3_phy { }; =20 &pcie4 { - perst-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; - pinctrl-0 =3D <&pcie4_default>; pinctrl-names =3D "default"; =20 @@ -1129,10 +1126,12 @@ &pcie4_phy { status =3D "okay"; }; =20 -&pcie5 { - perst-gpios =3D <&tlmm 149 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 151 GPIO_ACTIVE_LOW>; +&pcie4_port0 { + reset-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; +}; =20 +&pcie5 { vddpe-3v3-supply =3D <&vreg_wwan>; =20 pinctrl-0 =3D <&pcie5_default>; @@ -1148,10 +1147,12 @@ &pcie5_phy { status =3D "okay"; }; =20 -&pcie6a { - perst-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; +&pcie5_port0 { + reset-gpios =3D <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 151 GPIO_ACTIVE_LOW>; +}; =20 +&pcie6a { vddpe-3v3-supply =3D <&vreg_nvme>; =20 pinctrl-0 =3D <&pcie6a_default>; @@ -1167,6 +1168,11 @@ &pcie6a_phy { status =3D "okay"; }; =20 +&pcie6a_port0 { + reset-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + &pm8550_gpios { rtmr0_default: rtmr0-reset-n-active-state { pins =3D "gpio10"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts b/arch= /arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts index 34467b84a2fa..17269eb0638a 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts @@ -907,9 +907,6 @@ &mdss_dp3_phy { }; =20 &pcie4 { - perst-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; - pinctrl-0 =3D <&pcie4_default>; pinctrl-names =3D "default"; =20 @@ -924,6 +921,9 @@ &pcie4_phy { }; =20 &pcie4_port0 { + reset-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; + wifi@0 { compatible =3D "pci17cb,1107"; reg =3D <0x10000 0x0 0x0 0x0 0x0>; @@ -941,9 +941,6 @@ wifi@0 { }; =20 &pcie6a { - perst-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply =3D <&vreg_nvme>; =20 pinctrl-0 =3D <&pcie6a_default>; @@ -959,6 +956,11 @@ &pcie6a_phy { status =3D "okay"; }; =20 +&pcie6a_port0 { + reset-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + &pm8550_gpios { rtmr0_default: rtmr0-reset-n-active-state { pins =3D "gpio10"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts b/arch/= arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts index 0408ade7150f..b42318c75ed2 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts @@ -82,6 +82,9 @@ &gpu_zap_shader { }; =20 &pcie4_port0 { + reset-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; + wifi@0 { compatible =3D "pci17cb,1107"; reg =3D <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts b/arch/a= rm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts index 2f533e56c8c8..4c95b1af2c64 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts @@ -941,9 +941,6 @@ &mdss_dp3_phy { }; =20 &pcie4 { - perst-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; - pinctrl-0 =3D <&pcie4_default>; pinctrl-names =3D "default"; =20 @@ -958,6 +955,9 @@ &pcie4_phy { }; =20 &pcie4_port0 { + reset-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; + wifi@0 { compatible =3D "pci17cb,1107"; reg =3D <0x10000 0x0 0x0 0x0 0x0>; @@ -975,9 +975,6 @@ wifi@0 { }; =20 &pcie6a { - perst-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply =3D <&vreg_nvme>; =20 pinctrl-0 =3D <&pcie6a_default>; @@ -993,6 +990,11 @@ &pcie6a_phy { status =3D "okay"; }; =20 +&pcie6a_port0 { + reset-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + &pm8550_gpios { rtmr0_default: rtmr0-reset-n-active-state { pins =3D "gpio10"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arc= h/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index 4c31d14a07bc..d6472e5a3f9f 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -1160,9 +1160,6 @@ wifi@0 { }; =20 &pcie6a { - perst-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply =3D <&vreg_nvme>; =20 pinctrl-0 =3D <&pcie6a_default>; @@ -1178,6 +1175,11 @@ &pcie6a_phy { status =3D "okay"; }; =20 +&pcie6a_port0 { + reset-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + &pm8550_gpios { rtmr0_default: rtmr0-reset-n-active-state { pins =3D "gpio10"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi b/arc= h/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi index 7e1e808ea983..37539a09b76e 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi @@ -1094,9 +1094,6 @@ &mdss_dp3_phy { }; =20 &pcie3 { - perst-gpios =3D <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 145 GPIO_ACTIVE_HIGH>; - pinctrl-0 =3D <&pcie3_default>; pinctrl-names =3D "default"; =20 @@ -1112,6 +1109,11 @@ &pcie3_phy { status =3D "okay"; }; =20 +&pcie3_port0 { + reset-gpios =3D <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie4 { status =3D "okay"; }; @@ -1124,6 +1126,9 @@ &pcie4_phy { }; =20 &pcie4_port0 { + reset-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; + wifi@0 { compatible =3D "pci17cb,1107"; reg =3D <0x10000 0x0 0x0 0x0 0x0>; @@ -1141,9 +1146,6 @@ wifi@0 { }; =20 &pcie6a { - perst-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply =3D <&vreg_nvme>; =20 pinctrl-0 =3D <&pcie6a_default>; @@ -1159,6 +1161,11 @@ &pcie6a_phy { status =3D "okay"; }; =20 +&pcie6a_port0 { + reset-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + &pm8550_gpios { rtmr0_default: rtmr0-reset-n-active-state { pins =3D "gpio10"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dt= s/qcom/x1e80100-qcp.dts index b742aabd9c04..1d402ef86512 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -979,8 +979,6 @@ pm_sde7_main_3p3_en: pcie-main-3p3-default-state { &pcie3 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pcie3_default>; - perst-gpios =3D <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 145 GPIO_ACTIVE_LOW>; =20 status =3D "okay"; }; @@ -992,16 +990,16 @@ &pcie3_phy { status =3D "okay"; }; =20 -&pcie3_port { +&pcie3_port0 { vpcie12v-supply =3D <&vreg_pcie_12v>; vpcie3v3-supply =3D <&vreg_pcie_3v3>; vpcie3v3aux-supply =3D <&vreg_pcie_3v3_aux>; + + reset-gpios =3D <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 145 GPIO_ACTIVE_LOW>; }; =20 &pcie4 { - perst-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; - pinctrl-0 =3D <&pcie4_default>; pinctrl-names =3D "default"; =20 @@ -1016,6 +1014,9 @@ &pcie4_phy { }; =20 &pcie4_port0 { + reset-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; + wifi@0 { compatible =3D "pci17cb,1107"; reg =3D <0x10000 0x0 0x0 0x0 0x0>; @@ -1033,9 +1034,6 @@ wifi@0 { }; =20 &pcie6a { - perst-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply =3D <&vreg_nvme>; =20 pinctrl-names =3D "default"; @@ -1051,6 +1049,11 @@ &pcie6a_phy { status =3D "okay"; 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charset="utf-8" HAMOA IoT SOM requires PCIe3 and PCIe5 connectivity for SATA controller and SDX65. Add the required sideband signals (PERST#, WAKE#, CLKREQ#), pinctrl states and power supply properties in the device tree, which PCIe3 and PCIe5 require. Signed-off-by: Ziyue Zhang Reviewed-by: Krishna Chaitanya Chundru Reviewed-by: Dmitry Baryshkov Reviewed-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 74 +++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/= dts/qcom/hamoa-iot-som.dtsi index 4a69852e9176..81866f94fe01 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -390,6 +390,20 @@ &gpu_zap_shader { firmware-name =3D "qcom/x1e80100/gen70500_zap.mbn"; }; =20 +&pcie3 { + pinctrl-0 =3D <&pcie3_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie3_phy { + vdda-phy-supply =3D <&vreg_l3c_0p8>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + &pcie4 { perst-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; @@ -407,6 +421,20 @@ &pcie4_phy { status =3D "okay"; }; =20 +&pcie5 { + pinctrl-0 =3D <&pcie5_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie5_phy { + vdda-phy-supply =3D <&vreg_l3i_0p8>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + &pcie6a { perst-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; @@ -453,6 +481,29 @@ &remoteproc_cdsp { &tlmm { gpio-reserved-ranges =3D <34 2>; /* TPM LP & INT */ =20 + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins =3D "gpio144"; + function =3D "pcie3_clk"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio143"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio145"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + pcie4_default: pcie4-default-state { clkreq-n-pins { pins =3D "gpio147"; @@ -476,6 +527,29 @@ wake-n-pins { }; }; =20 + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins =3D "gpio150"; + function =3D "pcie5_clk"; + drive-strength =3D <2>; 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charset="utf-8" HAMAO IoT EVK uses PCIe5 to connect an SDX65 module for WWAN functionality and PCIe3 to connect a SATA controller. These interfaces require multiple voltage rails: PCIe5 needs 3.3V supplied by vreg_wwan, while PCIe3 requires 12V, 3.3V, and 3.3V AUX rails, controlled via PMIC GPIOs. Add the required fixed regulators with related pin configuration, and connect them to the PCIe3 and PCIe5 ports to ensure proper power for the SDX65 module and SATA controller. Move reset and wake GPIO properties from RC nodes to port nodes. Signed-off-by: Ziyue Zhang Reviewed-by: Krishna Chaitanya Chundru Reviewed-by: Dmitry Baryshkov Reviewed-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 97 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 6 -- 2 files changed, 97 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/d= ts/qcom/hamoa-iot-evk.dts index 898b92627f84..07378ee183f9 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -253,6 +253,48 @@ vreg_nvme: regulator-nvme { regulator-boot-on; }; =20 + vreg_pcie_12v: regulator-pcie-12v { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_PCIE_12V"; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + + gpio =3D <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&pcie_x8_12v>; + pinctrl-names =3D "default"; + }; + + vreg_pcie_3v3: regulator-pcie-3v3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_PCIE_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pmc8380_3_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&pm_sde7_main_3p3_en>; + pinctrl-names =3D "default"; + }; + + vreg_pcie_3v3_aux: regulator-pcie-3v3-aux { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_PCIE_3P3_AUX"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pmc8380_3_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&pm_sde7_aux_3p3_en>; + pinctrl-names =3D "default"; + }; + /* Left unused as the retimer is not used on this board. */ vreg_rtmr0_1p15: regulator-rtmr0-1p15 { compatible =3D "regulator-fixed"; @@ -920,7 +962,19 @@ &mdss_dp3_phy { status =3D "okay"; }; =20 +&pcie3_port0 { + vpcie12v-supply =3D <&vreg_pcie_12v>; + vpcie3v3-supply =3D <&vreg_pcie_3v3>; + vpcie3v3aux-supply =3D <&vreg_pcie_3v3_aux>; + + reset-gpios =3D <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie4_port0 { + reset-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; + wifi@0 { compatible =3D "pci17cb,1107"; reg =3D <0x10000 0x0 0x0 0x0 0x0>; @@ -937,10 +991,24 @@ wifi@0 { }; }; =20 +&pcie5 { + vddpe-3v3-supply =3D <&vreg_wwan>; +}; + +&pcie5_port0 { + reset-gpios =3D <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 151 GPIO_ACTIVE_LOW>; +}; + &pcie6a { vddpe-3v3-supply =3D <&vreg_nvme>; }; =20 +&pcie6a_port0 { + reset-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + &pm8550_gpios { rtmr0_default: rtmr0-reset-n-active-state { pins =3D "gpio10"; @@ -961,6 +1029,17 @@ usb0_3p3_reg_en: usb0-3p3-reg-en-state { }; }; =20 +&pm8550ve_8_gpios { + pcie_x8_12v: pcie-12v-default-state { + pins =3D "gpio8"; + function =3D "normal"; + output-enable; + output-high; + bias-pull-down; + power-source =3D <0>; + }; +}; + &pm8550ve_9_gpios { usb0_1p8_reg_en: usb0-1p8-reg-en-state { pins =3D "gpio8"; @@ -1025,6 +1104,24 @@ edp_bl_reg_en: edp-bl-reg-en-state { }; }; =20 +&pmc8380_3_gpios { + pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state { + pins =3D "gpio8"; + function =3D "normal"; + output-enable; + bias-pull-down; + power-source =3D <0>; + }; + + pm_sde7_main_3p3_en: pcie-main-3p3-default-state { + pins =3D "gpio6"; + function =3D "normal"; + output-enable; + bias-pull-down; + power-source =3D <0>; + }; +}; + &pmc8380_5_gpios { usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { pins =3D "gpio8"; diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/= dts/qcom/hamoa-iot-som.dtsi index 81866f94fe01..b8e3e04a6fbd 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -405,9 +405,6 @@ &pcie3_phy { }; =20 &pcie4 { - perst-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; - pinctrl-0 =3D <&pcie4_default>; pinctrl-names =3D "default"; =20 @@ -436,9 +433,6 @@ &pcie5_phy { }; =20 &pcie6a { - perst-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; - pinctrl-0 =3D <&pcie6a_default>; pinctrl-names =3D "default"; =20 --=20 2.34.1