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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-819c59e826asm9831562b3a.54.2026.01.09.01.02.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jan 2026 01:02:59 -0800 (PST) From: Himanshu Chauhan To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-efi@vger.kernel.org, acpica-devel@lists.linux.dev, paul.walmsley@sifive.com, palmer@dabbelt.com, lenb@kernel.org, james.morse@arm.com, tony.luck@intel.com, ardb@kernel.org, conor@kernel.org, cleger@rivosinc.com, robert.moore@intel.com, sunilvl@oss.qualcomm.com, anup.patel@oss.qualcomm.com Cc: Himanshu Chauhan Subject: [PATCH v3 06/10] riscv: Add functions to register ghes having SSE notification Date: Fri, 9 Jan 2026 14:32:20 +0530 Message-ID: <20260109090224.3105465-7-himanshu.chauhan@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260109090224.3105465-1-himanshu.chauhan@oss.qualcomm.com> References: <20260109090224.3105465-1-himanshu.chauhan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=RN2+3oi+ c=1 sm=1 tr=0 ts=6960c444 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=2d44Z0_5zRK2QUa08RUA:9 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-GUID: sL_-5ralHn8XMYNFFv5AlwXnCqMszq3z X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA5MDA2NCBTYWx0ZWRfX6eKuQ29f8bQS Wf12PwriD7LV0VN3TuE8IA3kMcX4eqhwWSFuS9K6dWGvObdk51GzwyW5sEbSLZHiLDvKBKFpvgn RX7GDJcNJSFQzx42l6SEdhzQP0i2RH4QQZHetn6zBMFlyn/EisfN2NECSh69quXgXtByxnUu7iy 0L7InRY/xRPzfLLtG+SrE8wb8ZT8flPHIRiS8zL/D2bBKKgsfUdnlpDDOYRXF0BztFz4muszUVA BSy9t+Wk6GxbBCvvOeEitU5Hj2ce4wgR7KB/ETuh0+JIh6kvcA8f2WzgpiC/RA5aR9lYsQ/LOSL M3iCMMDwcYRpyF5fsg53mHl1xSA5fRFswqs3p74ZawmkHiAq5b9N6UxZz6yN52tDE7KUHuw05up OyIGtGiFNmauO+YZiblcUTkVkxHSTinYG977SVzBjfvS/C2kWYGXeRHTx+/CSMLYOUhLgGriWic JaMnGHEji38Mg/aZNFA== X-Proofpoint-ORIG-GUID: sL_-5ralHn8XMYNFFv5AlwXnCqMszq3z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-09_02,2026-01-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 malwarescore=0 impostorscore=0 adultscore=0 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601090064 Content-Type: text/plain; charset="utf-8" Add functions to register the ghes entries which have SSE as notification type. The vector inside the ghes is the SSE event ID that should be registered. Signed-off-by: Himanshu Chauhan --- drivers/firmware/riscv/riscv_sbi_sse.c | 146 +++++++++++++++++++++++++ include/linux/riscv_sbi_sse.h | 16 +++ 2 files changed, 162 insertions(+) diff --git a/drivers/firmware/riscv/riscv_sbi_sse.c b/drivers/firmware/risc= v/riscv_sbi_sse.c index c7f29b10cdfb..ee288a0c1680 100644 --- a/drivers/firmware/riscv/riscv_sbi_sse.c +++ b/drivers/firmware/riscv/riscv_sbi_sse.c @@ -5,6 +5,8 @@ =20 #define pr_fmt(fmt) "sse: " fmt =20 +#include +#include #include #include #include @@ -692,3 +694,147 @@ static int __init sse_init(void) return ret; } arch_initcall(sse_init); + +struct sse_ghes_callback { + struct list_head head; + struct ghes *ghes; + sse_event_handler_fn *callback; +}; + +struct sse_ghes_event_data { + struct list_head head; + u32 event_num; + struct list_head callback_list; + struct sse_event *event; +}; + +static DEFINE_SPINLOCK(sse_ghes_event_list_lock); +static LIST_HEAD(sse_ghes_event_list); + +static int sse_ghes_handler(u32 event_num, void *arg, struct pt_regs *regs) +{ + struct sse_ghes_event_data *ev_data =3D arg; + struct sse_ghes_callback *cb =3D NULL; + + list_for_each_entry(cb, &ev_data->callback_list, head) { + if (cb && cb->ghes && cb->callback) + cb->callback(ev_data->event_num, cb->ghes, regs); + } + + return 0; +} + +int sse_register_ghes(struct ghes *ghes, sse_event_handler_fn *lo_cb, + sse_event_handler_fn *hi_cb) +{ + struct sse_ghes_event_data *ev_data, *evd; + struct sse_ghes_callback *cb; + u32 ev_num; + int err; + + if (!sse_available) + return -EOPNOTSUPP; + if (!ghes || !lo_cb || !hi_cb) + return -EINVAL; + + ev_num =3D ghes->generic->notify.vector; + + ev_data =3D NULL; + spin_lock(&sse_ghes_event_list_lock); + list_for_each_entry(evd, &sse_ghes_event_list, head) { + if (evd->event_num =3D=3D ev_num) { + ev_data =3D evd; + break; + } + } + spin_unlock(&sse_ghes_event_list_lock); + + if (!ev_data) { + ev_data =3D kzalloc(sizeof(*ev_data), GFP_KERNEL); + if (!ev_data) + return -ENOMEM; + + INIT_LIST_HEAD(&ev_data->head); + ev_data->event_num =3D ev_num; + + INIT_LIST_HEAD(&ev_data->callback_list); + + ev_data->event =3D sse_event_register(ev_num, ev_num, + sse_ghes_handler, ev_data); + if (IS_ERR(ev_data->event)) { + pr_err("%s: Couldn't register event 0x%x\n", __func__, ev_num); + kfree(ev_data); + return -ENOMEM; + } + + err =3D sse_event_enable(ev_data->event); + if (err) { + pr_err("%s: Couldn't enable event 0x%x\n", __func__, ev_num); + sse_event_unregister(ev_data->event); + kfree(ev_data); + return err; + } + + spin_lock(&sse_ghes_event_list_lock); + list_add_tail(&ev_data->head, &sse_ghes_event_list); + spin_unlock(&sse_ghes_event_list_lock); + } + + list_for_each_entry(cb, &ev_data->callback_list, head) { + if (cb->ghes =3D=3D ghes) + return -EALREADY; + } + + cb =3D kzalloc(sizeof(*cb), GFP_KERNEL); + if (!cb) + return -ENOMEM; + INIT_LIST_HEAD(&cb->head); + cb->ghes =3D ghes; + cb->callback =3D lo_cb; + list_add_tail(&cb->head, &ev_data->callback_list); + + return 0; +} + +int sse_unregister_ghes(struct ghes *ghes) +{ + struct sse_ghes_event_data *ev_data, *tmp; + struct sse_ghes_callback *cb; + int free_ev_data =3D 0; + + if (!ghes) + return -EINVAL; + + spin_lock(&sse_ghes_event_list_lock); + + list_for_each_entry_safe(ev_data, tmp, &sse_ghes_event_list, head) { + list_for_each_entry(cb, &ev_data->callback_list, head) { + if (cb->ghes !=3D ghes) + continue; + + list_del(&cb->head); + kfree(cb); + break; + } + + if (list_empty(&ev_data->callback_list)) + free_ev_data =3D 1; + + if (free_ev_data) { + spin_unlock(&sse_ghes_event_list_lock); + + sse_event_disable(ev_data->event); + sse_event_unregister(ev_data->event); + ev_data->event =3D NULL; + + spin_lock(&sse_ghes_event_list_lock); + + list_del(&ev_data->head); + kfree(ev_data); + } + } + + spin_unlock(&sse_ghes_event_list_lock); + + return 0; +} diff --git a/include/linux/riscv_sbi_sse.h b/include/linux/riscv_sbi_sse.h index 84165cb5f2d0..be0c9ad0a00c 100644 --- a/include/linux/riscv_sbi_sse.h +++ b/include/linux/riscv_sbi_sse.h @@ -11,6 +11,7 @@ =20 struct sse_event; struct pt_regs; +struct ghes; =20 typedef int (sse_event_handler_fn)(u32 event_num, void *arg, struct pt_regs *regs); @@ -24,6 +25,10 @@ void sse_event_unregister(struct sse_event *evt); =20 int sse_event_set_target_cpu(struct sse_event *sse_evt, unsigned int cpu); =20 +int sse_register_ghes(struct ghes *ghes, sse_event_handler_fn *lo_cb, + sse_event_handler_fn *hi_cb); +int sse_unregister_ghes(struct ghes *ghes); + int sse_event_enable(struct sse_event *sse_evt); =20 void sse_event_disable(struct sse_event *sse_evt); @@ -47,6 +52,17 @@ static inline int sse_event_set_target_cpu(struct sse_ev= ent *sse_evt, return -EOPNOTSUPP; } =20 +static inline int sse_register_ghes(struct ghes *ghes, sse_event_handler_f= n *lo_cb, + sse_event_handler_fn *hi_cb) +{ + return -EOPNOTSUPP; +} + +static inline int sse_unregister_ghes(struct ghes *ghes) +{ + return -EOPNOTSUPP; +} + static inline int sse_event_enable(struct sse_event *sse_evt) { return -EOPNOTSUPP; --=20 2.43.0