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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-819c59e826asm9831562b3a.54.2026.01.09.01.02.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jan 2026 01:02:36 -0800 (PST) From: Himanshu Chauhan To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-efi@vger.kernel.org, acpica-devel@lists.linux.dev, paul.walmsley@sifive.com, palmer@dabbelt.com, lenb@kernel.org, james.morse@arm.com, tony.luck@intel.com, ardb@kernel.org, conor@kernel.org, cleger@rivosinc.com, robert.moore@intel.com, sunilvl@oss.qualcomm.com, anup.patel@oss.qualcomm.com Cc: Himanshu Chauhan Subject: [PATCH v3 01/10] riscv: Define ioremap_cache for RISC-V Date: Fri, 9 Jan 2026 14:32:15 +0530 Message-ID: <20260109090224.3105465-2-himanshu.chauhan@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260109090224.3105465-1-himanshu.chauhan@oss.qualcomm.com> References: <20260109090224.3105465-1-himanshu.chauhan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=YNiSCBGx c=1 sm=1 tr=0 ts=6960c42e cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=JWN5yfGi9shfayy-Z8YA:9 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-GUID: 2prEMZ9IYZ3VMVVwjmnceCybPrM0tz9b X-Proofpoint-ORIG-GUID: 2prEMZ9IYZ3VMVVwjmnceCybPrM0tz9b X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA5MDA2NCBTYWx0ZWRfX3NIH2f7AP8f1 rSJ93wgtQN0KpZrf0iD0AW+0tvc11DJ+nImuQm+XSqh5ttFccp2kg24h+aZiMcLgm5K6zVu3gIA Xke+yhR9Ms2uVlRII4kdMZXwHHsuKjaip2yu/m1qK+xffC6eJdpsPoFW/1v/wxnyO/eoeJi93l9 AyfOPMKJSWwY2SySaGKfXYXDyluObkGVwA47zfBgeKhL69Fg/d01EdhS3XIFpBRWT9Hh4mQMam4 LKVn6rDN//UFa78k63CEr3OmPJK+lsLnx55631pOek9Or53LarGiCYm8+8QcIts+SEXIX768exN p4eBCpYlKtGGT4zPucKpUNyXFE2pl4deQ9A0ZBdDSEvAskwBqgUOTGyh6Lhn2naHZzi1feGWPns IR9tbtZ3KTmcjOOGfKSVUBGLkaEdKknHUfdf7uaZbIwnwvphlM94GifXa7FzbztdzYJ9OnbLCjd Xr8HgawhvRHSNjisVVA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-09_02,2026-01-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 suspectscore=0 impostorscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601090064 Content-Type: text/plain; charset="utf-8" bert and einj drivers use ioremap_cache for mapping entries but ioremap_cache is not defined for RISC-V. Signed-off-by: Himanshu Chauhan --- arch/riscv/include/asm/io.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 09bb5f57a9d3..5550b28f38db 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -142,6 +142,9 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw()) #ifdef CONFIG_MMU #define arch_memremap_wb(addr, size, flags) \ ((__force void *)ioremap_prot((addr), (size), __pgprot(_PAGE_KERNEL))) + +#define ioremap_cache(addr, size) \ + ((__force void *)ioremap_prot((addr), (size), PAGE_KERNEL)) #endif =20 #endif /* _ASM_RISCV_IO_H */ --=20 2.43.0