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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8c37f530c35sm771262185a.40.2026.01.09.00.38.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jan 2026 00:38:37 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, krzysztof.kozlowski@linaro.org, konrad.dybcio@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com Subject: [PATCH 1/2] drm/msm/dpu: fix mismatch between power and frequency Date: Fri, 9 Jan 2026 16:38:07 +0800 Message-Id: <20260109083808.1047-2-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260109083808.1047-1-yuanjie.yang@oss.qualcomm.com> References: <20260109083808.1047-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA5MDA2MCBTYWx0ZWRfXw0PstqbOYbs3 RlySRW7PBw8h4frP5CZ0Kn0g2ICxqvjen5Bw28q72eBOW7ZesCB+UmmohV+Q8pjPPmXCaCoP2m3 aF+oIfdcFYPttL/VO8sv62hTf+Pr8Ip+6btEb3QQIvA6mw70OpUnRW27AOsB3RpWURRDE85rSRo n5finQ6Df10ZJx0IgHxJCvdcsv1eycwbcFPSr/9+PSMfXSmc5esF8Q9tP80AV7NFS9xFMx9mySs z3s41uQ6JjQS9igN8ULjdpr6wGFOg09Dh9gyoiVjBJ7Dd4CX4X1yrMIWJotiKUgnfca3wlKu+Hc mkVItmf8Cbrj2Iyn2rXw5ctGxmkGh7cZqtyMGx5egPFqV9LP8uZEGPJlVJGTGl+XfPf5UEpmXte RQsUEx+UszdraNNimuO6gK2lY8DPyV79ipuFPWLoc2dRuvkWojhZe8SHkILnvVJCxcFcyzSJ+YU S2DQ8J91rwQ6SgSPqZA== X-Proofpoint-ORIG-GUID: YXeR2gFZ6JDTLSLzjWChu32AIA9mdR2M X-Authority-Analysis: v=2.4 cv=ENILElZC c=1 sm=1 tr=0 ts=6960be8f cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=VW4z5CC6hlf1mp1b6PkA:9 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-GUID: YXeR2gFZ6JDTLSLzjWChu32AIA9mdR2M X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-09_02,2026-01-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 suspectscore=0 phishscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 bulkscore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601090060 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang During DPU runtime suspend, calling dev_pm_opp_set_rate(dev, 0) drops the MMCX rail to MIN_SVS while the core clock frequency remains at its original (highest) rate. When runtime resume re-enables the clock, this may result in a mismatch between the rail voltage and the clock rate. For example, in the DPU bind path, the sequence could be: cpu0: dev_sync_state -> rpmhpd_sync_state cpu1: dpu_kms_hw_init timeline 0 ------------------------------------------------> t After rpmhpd_sync_state, the voltage performance is no longer guaranteed to stay at the highest level. During dpu_kms_hw_init, calling dev_pm_opp_set_rate(dev, 0) drops the voltage, causing the MMCX rail to fall to MIN_SVS while the core clock is still at its maximum frequency. When the power is re-enabled, only the clock is enabled, leading to a situation where the MMCX rail is at MIN_SVS but the core clock is at its highest rate. In this state, the rail cannot sustain the clock rate, which may cause instability or system crash. Fix this by setting the corresponding OPP corner during both power-on and power-off sequences to ensure proper alignment of rail voltage and clock frequency. Fixes: b0530eb11913 ("drm/msm/dpu: Use OPP API to set clk/perf state") Signed-off-by: Yuanjie Yang --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 16 ++++++++++++---- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 3 +++ 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 0623f1dbed97..c31488335f2b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1306,9 +1306,14 @@ static int dpu_kms_init(struct drm_device *ddev) struct dpu_kms *dpu_kms =3D to_dpu_kms(priv->kms); struct dev_pm_opp *opp; int ret =3D 0; - unsigned long max_freq =3D ULONG_MAX; + dpu_kms->max_freq =3D ULONG_MAX; + dpu_kms->min_freq =3D 0; =20 - opp =3D dev_pm_opp_find_freq_floor(dev, &max_freq); + opp =3D dev_pm_opp_find_freq_floor(dev, &dpu_kms->max_freq); + if (!IS_ERR(opp)) + dev_pm_opp_put(opp); + + opp =3D dev_pm_opp_find_freq_ceil(dev, &dpu_kms->min_freq); if (!IS_ERR(opp)) dev_pm_opp_put(opp); =20 @@ -1461,8 +1466,8 @@ static int __maybe_unused dpu_runtime_suspend(struct = device *dev) struct msm_drm_private *priv =3D platform_get_drvdata(pdev); struct dpu_kms *dpu_kms =3D to_dpu_kms(priv->kms); =20 - /* Drop the performance state vote */ - dev_pm_opp_set_rate(dev, 0); + /* adjust the performance state vote to low performance state */ + dev_pm_opp_set_rate(dev, dpu_kms->min_freq); clk_bulk_disable_unprepare(dpu_kms->num_clocks, dpu_kms->clocks); =20 for (i =3D 0; i < dpu_kms->num_paths; i++) @@ -1481,6 +1486,9 @@ static int __maybe_unused dpu_runtime_resume(struct d= evice *dev) struct drm_device *ddev; =20 ddev =3D dpu_kms->dev; + /* adjust the performance state vote to high performance state */ + if (dpu_kms->max_freq !=3D ULONG_MAX) + dev_pm_opp_set_rate(dev, dpu_kms->max_freq); =20 rc =3D clk_bulk_prepare_enable(dpu_kms->num_clocks, dpu_kms->clocks); if (rc) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.h index 993cf512f8c5..8d2595d8a5f6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -92,6 +92,9 @@ struct dpu_kms { struct clk_bulk_data *clocks; size_t num_clocks; =20 + unsigned long max_freq; + unsigned long min_freq; + /* reference count bandwidth requests, so we know when we can * release bandwidth. Each atomic update increments, and frame- * done event decrements. Additionally, for video mode, the --=20 2.34.1