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(unknown []) by gzga-smtp-mtada-g1-0 (Coremail) with SMTP id _____wDnzlW4tWBpx1iBFA--.64397S4; Fri, 09 Jan 2026 16:01:02 +0800 (CST) From: Andy Yan To: heiko@sntech.de, dmitry.baryshkov@oss.qualcomm.com Cc: krzk+dt@kernel.org, conor+dt@kernel.org, cristian.ciocaltea@collabora.com, Laurent.pinchart@ideasonboard.com, mripard@kernel.org, hjc@rock-chips.com, robh@kernel.org, sebastian.reichel@collabora.com, tzimmermann@suse.de, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Andy Yan Subject: [PATCH 2/5] drm/bridge: synopsys: dw-dp: Set pixel mode by platform data Date: Fri, 9 Jan 2026 16:00:45 +0800 Message-ID: <20260109080054.228671-3-andyshrk@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260109080054.228671-1-andyshrk@163.com> References: <20260109080054.228671-1-andyshrk@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDnzlW4tWBpx1iBFA--.64397S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxuF1kXFyDCw47Jw1rCF4rXwb_yoWrXF13pF WxAFW5KrWqgF4Y9a4kAr4kCFn0yw1qkayxJa97Kw1Ik34fKFykXr9Ivr15Gwn3XF9xur17 CrsrJrW8Z3W2krUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jmrWwUUUUU= X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbC7R4PbWlgtb710wAA31 Content-Type: text/plain; charset="utf-8" From: Andy Yan The DW DisplayPort hardware block can be configured to work in single, dual,quad pixel mode on differnt platforms, so make the pixel mode set by plat_data to support the upcoming rk3576 variant. Signed-off-by: Andy Yan Reviewed-by: Sebastian Reichel Tested-by: Sebastian Reichel --- drivers/gpu/drm/bridge/synopsys/dw-dp.c | 8 +------- drivers/gpu/drm/rockchip/dw_dp-rockchip.c | 19 +++++++++++++++---- include/drm/bridge/dw_dp.h | 7 +++++++ 3 files changed, 23 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-dp.c b/drivers/gpu/drm/brid= ge/synopsys/dw-dp.c index 82aaf74e1bc0..eccf6299bdb7 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-dp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-dp.c @@ -352,12 +352,6 @@ enum { DW_DP_YCBCR420_16BIT, }; =20 -enum { - DW_DP_MP_SINGLE_PIXEL, - DW_DP_MP_DUAL_PIXEL, - DW_DP_MP_QUAD_PIXEL, -}; - enum { DW_DP_SDP_VERTICAL_INTERVAL =3D BIT(0), DW_DP_SDP_HORIZONTAL_INTERVAL =3D BIT(1), @@ -1984,7 +1978,7 @@ struct dw_dp *dw_dp_bind(struct device *dev, struct d= rm_encoder *encoder, return ERR_CAST(dp); =20 dp->dev =3D dev; - dp->pixel_mode =3D DW_DP_MP_QUAD_PIXEL; + dp->pixel_mode =3D plat_data->pixel_mode; =20 dp->plat_data.max_link_rate =3D plat_data->max_link_rate; bridge =3D &dp->bridge; diff --git a/drivers/gpu/drm/rockchip/dw_dp-rockchip.c b/drivers/gpu/drm/ro= ckchip/dw_dp-rockchip.c index 25ab4e46301e..89d614d53596 100644 --- a/drivers/gpu/drm/rockchip/dw_dp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_dp-rockchip.c @@ -75,7 +75,7 @@ static const struct drm_encoder_helper_funcs dw_dp_encode= r_helper_funcs =3D { static int dw_dp_rockchip_bind(struct device *dev, struct device *master, = void *data) { struct platform_device *pdev =3D to_platform_device(dev); - struct dw_dp_plat_data plat_data; + const struct dw_dp_plat_data *plat_data; struct drm_device *drm_dev =3D data; struct rockchip_dw_dp *dp; struct drm_encoder *encoder; @@ -89,7 +89,10 @@ static int dw_dp_rockchip_bind(struct device *dev, struc= t device *master, void * dp->dev =3D dev; platform_set_drvdata(pdev, dp); =20 - plat_data.max_link_rate =3D 810000; + plat_data =3D of_device_get_match_data(dev); + if (!plat_data) + return -ENODEV; + encoder =3D &dp->encoder.encoder; encoder->possible_crtcs =3D drm_of_find_possible_crtcs(drm_dev, dev->of_n= ode); rockchip_drm_encoder_set_crtc_endpoint_id(&dp->encoder, dev->of_node, 0, = 0); @@ -99,7 +102,7 @@ static int dw_dp_rockchip_bind(struct device *dev, struc= t device *master, void * return ret; drm_encoder_helper_add(encoder, &dw_dp_encoder_helper_funcs); =20 - dp->base =3D dw_dp_bind(dev, encoder, &plat_data); + dp->base =3D dw_dp_bind(dev, encoder, plat_data); if (IS_ERR(dp->base)) { ret =3D PTR_ERR(dp->base); return ret; @@ -134,8 +137,16 @@ static void dw_dp_remove(struct platform_device *pdev) component_del(dp->dev, &dw_dp_rockchip_component_ops); } =20 +static const struct dw_dp_plat_data rk3588_dp_plat_data =3D { + .max_link_rate =3D 810000, + .pixel_mode =3D DW_DP_MP_QUAD_PIXEL, +}; + static const struct of_device_id dw_dp_of_match[] =3D { - { .compatible =3D "rockchip,rk3588-dp", }, + { + .compatible =3D "rockchip,rk3588-dp", + .data =3D &rk3588_dp_plat_data, + }, {} }; MODULE_DEVICE_TABLE(of, dw_dp_of_match); diff --git a/include/drm/bridge/dw_dp.h b/include/drm/bridge/dw_dp.h index d05df49fd884..25363541e69d 100644 --- a/include/drm/bridge/dw_dp.h +++ b/include/drm/bridge/dw_dp.h @@ -11,8 +11,15 @@ struct drm_encoder; struct dw_dp; =20 +enum { + DW_DP_MP_SINGLE_PIXEL, + DW_DP_MP_DUAL_PIXEL, + DW_DP_MP_QUAD_PIXEL, +}; + struct dw_dp_plat_data { u32 max_link_rate; + u8 pixel_mode; }; =20 struct dw_dp *dw_dp_bind(struct device *dev, struct drm_encoder *encoder, --=20 2.43.0