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[98.57.15.22]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-3ffa515f4dasm6274421fac.21.2026.01.08.20.33.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 20:33:58 -0800 (PST) From: Alexandru Gagniuc To: andersson@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, linux-remoteproc@vger.kernel.org, Mathieu Poirier , Gokul Sriram Palanisamy , Govind Singh Cc: robh@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, sboyd@kernel.org, p.zabel@pengutronix.de, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Alexandru Gagniuc Subject: [PATCH v2 1/9] remoteproc: qcom_q6v5_wcss: drop unused clocks from q6v5 struct Date: Thu, 8 Jan 2026 22:33:36 -0600 Message-ID: <20260109043352.3072933-2-mr.nuke.me@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20260109043352.3072933-1-mr.nuke.me@gmail.com> References: <20260109043352.3072933-1-mr.nuke.me@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Three of the clocks from struct q6v5_wcss are not populated, and are not used. Remove them. Fixes: 0af65b9b915e ("remoteproc: qcom: wcss: Add non pas wcss Q6 support f= or QCS404") Signed-off-by: Alexandru Gagniuc Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- Changes since v1: - no changes. Moved patch to the start of series. --- drivers/remoteproc/qcom_q6v5_wcss.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_= q6v5_wcss.c index c27200159a88..07bba47eb084 100644 --- a/drivers/remoteproc/qcom_q6v5_wcss.c +++ b/drivers/remoteproc/qcom_q6v5_wcss.c @@ -123,10 +123,7 @@ struct q6v5_wcss { struct clk *ahbs_cbcr; struct clk *tcm_slave_cbcr; struct clk *qdsp6ss_abhm_cbcr; - struct clk *qdsp6ss_sleep_cbcr; struct clk *qdsp6ss_axim_cbcr; - struct clk *qdsp6ss_xo_cbcr; - struct clk *qdsp6ss_core_gfmux; struct clk *lcc_bcr_sleep; struct regulator *cx_supply; struct qcom_sysmon *sysmon; --=20 2.45.1 From nobody Sun Feb 8 02:21:45 2026 Received: from mail-oa1-f50.google.com (mail-oa1-f50.google.com [209.85.160.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D436B19309C for ; Fri, 9 Jan 2026 04:34:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[98.57.15.22]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-3ffa515f4dasm6274421fac.21.2026.01.08.20.34.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 20:34:03 -0800 (PST) From: Alexandru Gagniuc To: andersson@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, linux-remoteproc@vger.kernel.org, Mathieu Poirier , Rob Herring , Conor Dooley , Alexandru Gagniuc Cc: konradybcio@kernel.org, sboyd@kernel.org, p.zabel@pengutronix.de, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 2/9] dt-bindings: remoteproc: qcom,ipq8074-wcss-pil: convert to DT schema Date: Thu, 8 Jan 2026 22:33:37 -0600 Message-ID: <20260109043352.3072933-3-mr.nuke.me@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20260109043352.3072933-1-mr.nuke.me@gmail.com> References: <20260109043352.3072933-1-mr.nuke.me@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the QCS404 and IPQ WCSS Peripheral Image Loader bindings to DT schema. The text bindngs incorrectly implied that IPQ8074 needs only one qcom,smem-states entry. This is only true for QCS404. IPQ8074 requires both "stop" and "shutdown". The example is to be added in a subsequent commit that adds the IPQ9574 binding. Signed-off-by: Alexandru Gagniuc Reviewed-by: Krzysztof Kozlowski --- Changes since RFC - Add Bjorn (SOC maintainer) as maintaner for binding - rename binding from ipq9574 to ipq8074 - use a real person instead of placeholder as maintainer - drop redundant minItems and descriptions - merge if: clauses as suggested by Krzysztof - various other fixes suggested by Krzysztof --- .../remoteproc/qcom,ipq8074-wcss-pil.yaml | 157 ++++++++++++++++++ .../bindings/remoteproc/qcom,q6v5.txt | 102 ------------ 2 files changed, 157 insertions(+), 102 deletions(-) create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,ipq80= 74-wcss-pil.yaml delete mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,q6v5.= txt diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,ipq8074-wcss= -pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,ipq8074-wcss-= pil.yaml new file mode 100644 index 000000000000..c9bdd46fc745 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,ipq8074-wcss-pil.ya= ml @@ -0,0 +1,157 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,ipq8074-wcss-pil.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ WCSS Peripheral Image Loader + +maintainers: + - Bjorn Andersson + - Alexandru Gagniuc + +description: + The IPQ WCSS peripheral image loader is used to load firmware on the Qua= lcomm + Q6 processor that exposes WiFi-6 devices to the OS via the AHB bus. It is + generally used by ath11k to start up the wireless firmware. + +properties: + compatible: + enum: + - qcom,ipq8074-wcss-pil + - qcom,qcs404-wcss-pil + + reg: + maxItems: 2 + + reg-names: + items: + - const: qdsp6 + - const: rmb + + interrupts: + maxItems: 5 + + interrupt-names: + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + + resets: + maxItems: 3 + + reset-names: + items: + - const: wcss_aon_reset + - const: wcss_reset + - const: wcss_q6_reset + + clocks: + maxItems: 10 + + clock-names: + maxItems: 10 + + cx-supply: + description: + reference to the regulators used for the booting of the Hexagon core + + memory-region: + maxItems: 1 + + qcom,halt-regs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + A phandle reference to a syscon representing TCSR followed by the th= ree + offsets within syscon for q6, wcss and nc halt registers. + items: + - items: + - description: phandle to TCSR_MUTEX registers + - description: offset to the Q6 halt register + - description: offset to the wcss halt register + - description: offset to the nc halt register + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 2 + description: States used by the AP to signal the remote processor + + qcom,smem-state-names: + maxItems: 2 + description: + Names of the states used by the AP to signal the remote processor + + glink-edge: + $ref: /schemas/remoteproc/qcom,glink-edge.yaml# + description: + Qualcomm G-Link subnode which represents communication edge, channels + and devices related to the Modem. + +required: + - compatible + - reg + - reg-names + - interrupts-extended + - interrupt-names + - memory-region + - qcom,halt-regs + - qcom,smem-states + - qcom,smem-state-names + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq8074-wcss-pil + then: + properties: + qcom,smem-states: + items: + - description: Shutdown Q6 + - description: Stop Q6 + qcom,smem-state-names: + items: + - const: shutdown + - const: stop + clock-names: false + clocks: false + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcs404-wcss-pil + then: + properties: + qcom,smem-states: + maxItems: 1 + qcom,smem-state-names: + items: + - const: stop + clocks: + minItems: 10 + maxItems: 10 + clock-names: + items: + - const: xo + - const: gcc_abhs_cbcr + - const: gcc_axim_cbcr + - const: lcc_ahbfabric_cbc + - const: tcsr_lcc_cbc + - const: lcc_abhs_cbc + - const: lcc_tcm_slave_cbc + - const: lcc_abhm_cbc + - const: lcc_axim_cbc + - const: lcc_bcr_sleep + required: + - clocks + - clock-names + - cx-supply + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/D= ocumentation/devicetree/bindings/remoteproc/qcom,q6v5.txt deleted file mode 100644 index 573a88b60677..000000000000 --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt +++ /dev/null @@ -1,102 +0,0 @@ -Qualcomm Hexagon Peripheral Image Loader - -This document defines the binding for a component that loads and boots fir= mware -on the Qualcomm Hexagon core. - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,ipq8074-wcss-pil" - "qcom,qcs404-wcss-pil" - -- reg: - Usage: required - Value type: - Definition: must specify the base address and size of the qdsp6 and - rmb register blocks - -- reg-names: - Usage: required - Value type: - Definition: must be "q6dsp" and "rmb" - -- interrupts-extended: - Usage: required - Value type: - Definition: reference to the interrupts that match interrupt-names - -- interrupt-names: - Usage: required - Value type: - Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack" - -- clocks: - Usage: required - Value type: - Definition: reference to the clocks that match clock-names - -- clock-names: - Usage: required - Value type: - Definition: The clocks needed depend on the compatible string: - qcom,ipq8074-wcss-pil: - no clock names required - qcom,qcs404-wcss-pil: - must be "xo", "gcc_abhs_cbcr", "gcc_abhs_cbcr", - "gcc_axim_cbcr", "lcc_ahbfabric_cbc", "tcsr_lcc_cbc", - "lcc_abhs_cbc", "lcc_tcm_slave_cbc", "lcc_abhm_cbc", - "lcc_axim_cbc", "lcc_bcr_sleep" - -- resets: - Usage: required - Value type: - Definition: reference to the list of 3 reset-controllers for the - wcss sub-system - -- reset-names: - Usage: required - Value type: - Definition: must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset" - for the wcss sub-system - -- memory-region: - Usage: required - Value type: - Definition: reference to wcss reserved-memory region. - -For the compatible string below the following supplies are required: - "qcom,qcs404-wcss-pil" -- cx-supply: - Usage: required - Value type: - Definition: reference to the regulators to be held on behalf of the - booting of the Hexagon core - -- qcom,smem-states: - Usage: required - Value type: - Definition: reference to the smem state for requesting the Hexagon to - shut down - -- qcom,smem-state-names: - Usage: required - Value type: - Definition: must be "stop" - -- qcom,halt-regs: - Usage: required - Value type: - Definition: a phandle reference to a syscon representing TCSR followed - by the three offsets within syscon for q6, wcss and nc - halt registers. - -- memory-region: - Usage: required - Value type: - Definition: reference to the reserved-memory for the region - -The Hexagon node may also have an subnode named either "smd-edge" or -"glink-edge" that describes the communication edge, channels and devices -related to the Hexagon. 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[98.57.15.22]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-3ffa515f4dasm6274421fac.21.2026.01.08.20.34.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 20:34:05 -0800 (PST) From: Alexandru Gagniuc To: andersson@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, linux-remoteproc@vger.kernel.org, Stephen Boyd , Rob Herring , Conor Dooley Cc: mathieu.poirier@linaro.org, konradybcio@kernel.org, p.zabel@pengutronix.de, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Alexandru Gagniuc Subject: [PATCH v2 3/9] dt-bindings: clock: gcc-ipq9574: add wcss remoteproc clocks Date: Thu, 8 Jan 2026 22:33:38 -0600 Message-ID: <20260109043352.3072933-4-mr.nuke.me@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20260109043352.3072933-1-mr.nuke.me@gmail.com> References: <20260109043352.3072933-1-mr.nuke.me@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit da040d560319 ("dt-bindings: clock: qcom: gcc-ipq9574: remove q6 bring up clock macros") removed these clocks on the idea that Q6 firmware is responsible for clock bringup. That statement seems incorrect, as these clocks need to be enabled before the Q6 is booted. Otherwise, the host CPU core that starts the Q6 hangs. Perhaps the statement meant that the TrustZone firmware will start the clocks. This only happens in PAS mode. Under native OS loading, the host needs these clocks, so add them back. Besides the clocks that were erroneously removed, also add defines for GCC_WCSS_AHB_S_CLK, GCC_WCSS_AXI_M_CLK, and GCC_Q6_AXIM2_CLK, as all these clocks are required to operate the remoteproc. Signed-off-by: Alexandru Gagniuc Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/qcom,ipq9574-gcc.h | 22 ++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bind= ings/clock/qcom,ipq9574-gcc.h index 0e7c319897f3..8c74f50a2790 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -132,8 +132,16 @@ #define GCC_NSSNOC_SNOC_1_CLK 123 #define GCC_QDSS_ETR_USB_CLK 124 #define WCSS_AHB_CLK_SRC 125 +#define GCC_Q6_AHB_CLK 126 +#define GCC_Q6_AHB_S_CLK 127 +#define GCC_WCSS_ECAHB_CLK 128 +#define GCC_WCSS_ACMT_CLK 129 +#define GCC_SYS_NOC_WCSS_AHB_CLK 130 #define WCSS_AXI_M_CLK_SRC 131 +#define GCC_ANOC_WCSS_AXI_M_CLK 132 #define QDSS_AT_CLK_SRC 133 +#define GCC_Q6SS_ATBM_CLK 134 +#define GCC_WCSS_DBG_IFC_ATB_CLK 135 #define GCC_NSSNOC_ATB_CLK 136 #define GCC_QDSS_AT_CLK 137 #define GCC_SYS_NOC_AT_CLK 138 @@ -146,18 +154,27 @@ #define QDSS_TRACECLKIN_CLK_SRC 145 #define GCC_QDSS_TRACECLKIN_CLK 146 #define QDSS_TSCTR_CLK_SRC 147 +#define GCC_Q6_TSCTR_1TO2_CLK 148 +#define GCC_WCSS_DBG_IFC_NTS_CLK 149 #define GCC_QDSS_TSCTR_DIV2_CLK 150 #define GCC_QDSS_TS_CLK 151 #define GCC_QDSS_TSCTR_DIV4_CLK 152 #define GCC_NSS_TS_CLK 153 #define GCC_QDSS_TSCTR_DIV8_CLK 154 #define GCC_QDSS_TSCTR_DIV16_CLK 155 +#define GCC_Q6SS_PCLKDBG_CLK 156 +#define GCC_Q6SS_TRIG_CLK 157 +#define GCC_WCSS_DBG_IFC_APB_CLK 158 +#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 159 #define GCC_QDSS_DAP_CLK 160 #define GCC_QDSS_APB2JTAG_CLK 161 #define GCC_QDSS_TSCTR_DIV3_CLK 162 #define QPIC_IO_MACRO_CLK_SRC 163 #define GCC_QPIC_IO_MACRO_CLK 164 #define Q6_AXI_CLK_SRC 165 +#define GCC_Q6_AXIM_CLK 166 +#define GCC_WCSS_Q6_TBU_CLK 167 +#define GCC_MEM_NOC_Q6_AXI_CLK 168 #define Q6_AXIM2_CLK_SRC 169 #define NSSNOC_MEMNOC_BFDCD_CLK_SRC 170 #define GCC_NSSNOC_MEMNOC_CLK 171 @@ -182,6 +199,7 @@ #define GCC_UNIPHY2_SYS_CLK 190 #define GCC_CMN_12GPLL_SYS_CLK 191 #define GCC_NSSNOC_XO_DCD_CLK 192 +#define GCC_Q6SS_BOOT_CLK 193 #define UNIPHY_SYS_CLK_SRC 194 #define NSS_TS_CLK_SRC 195 #define GCC_ANOC_PCIE0_1LANE_M_CLK 196 @@ -203,4 +221,8 @@ #define GCC_PCIE2_PIPE_CLK 212 #define GCC_PCIE3_PIPE_CLK 213 #define GPLL0_OUT_AUX 214 +#define GCC_WCSS_AHB_S_CLK 215 +#define GCC_WCSS_AXI_M_CLK 216 +#define GCC_Q6_AXIM2_CLK 217 + #endif --=20 2.45.1 From nobody Sun Feb 8 02:21:45 2026 Received: from mail-oa1-f52.google.com (mail-oa1-f52.google.com [209.85.160.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86D702DEA64 for ; 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[98.57.15.22]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-3ffa515f4dasm6274421fac.21.2026.01.08.20.34.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 20:34:07 -0800 (PST) From: Alexandru Gagniuc To: andersson@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, linux-remoteproc@vger.kernel.org, Mathieu Poirier , Rob Herring , Conor Dooley , Alexandru Gagniuc Cc: konradybcio@kernel.org, sboyd@kernel.org, p.zabel@pengutronix.de, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 4/9] dt-bindings: remoteproc: qcom: add IPQ9574 image loader Date: Thu, 8 Jan 2026 22:33:39 -0600 Message-ID: <20260109043352.3072933-5-mr.nuke.me@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20260109043352.3072933-1-mr.nuke.me@gmail.com> References: <20260109043352.3072933-1-mr.nuke.me@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the IPQ9574 native (non-PAS) WCSS image loader. It is similar to IPQ8074 WCSS, but requires several new clocks. These clocks must be enabled by the host in non-PAS mode, and are not optional. This binding did not have an example, so add one which uses the "qcom,ipq9574-wcss-pil" binding. Signed-off-by: Alexandru Gagniuc Reviewed-by: Krzysztof Kozlowski --- Changes since v1: - Fixed order of clock-names - Also use minItems: for clocks and clock-names - Explained why example is added to binding. --- .../remoteproc/qcom,ipq8074-wcss-pil.yaml | 116 +++++++++++++++++- 1 file changed, 114 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,ipq8074-wcss= -pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,ipq8074-wcss-= pil.yaml index c9bdd46fc745..865c11ee6d0c 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,ipq8074-wcss-pil.ya= ml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,ipq8074-wcss-pil.ya= ml @@ -19,6 +19,7 @@ properties: compatible: enum: - qcom,ipq8074-wcss-pil + - qcom,ipq9574-wcss-pil - qcom,qcs404-wcss-pil =20 reg: @@ -50,10 +51,12 @@ properties: - const: wcss_q6_reset =20 clocks: - maxItems: 10 + minItems: 10 + maxItems: 13 =20 clock-names: - maxItems: 10 + minItems: 10 + maxItems: 13 =20 cx-supply: description: @@ -121,6 +124,44 @@ allOf: clock-names: false clocks: false =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq9574-wcss-pil + then: + properties: + clocks: + minItems: 13 + clock-names: + items: + - const: anoc_wcss_axi_m + - const: q6_ahb + - const: q6_ahb_s + - const: q6_axim + - const: q6ss_boot + - const: mem_noc_q6_axi + - const: sys_noc_wcss_ahb + - const: wcss_acmt + - const: wcss_ecahb + - const: wcss_q6_tbu + - const: q6_axim2 + - const: wcss_ahb_s + - const: wcss_axi_m + qcom,smem-states: + items: + - description: Shutdown Q6 + - description: Stop Q6 + qcom,smem-state-names: + items: + - const: shutdown + - const: stop + + required: + - clocks + - clock-names + - if: properties: compatible: @@ -155,3 +196,74 @@ allOf: - cx-supply =20 additionalProperties: false + +examples: + - | + #include + #include + #include + + q6v5_wcss: remoteproc@cd00000 { + compatible =3D "qcom,ipq9574-wcss-pil"; + reg =3D <0x0cd00000 0x4040>, + <0x004ab000 0x20>; + reg-names =3D "qdsp6", "rmb"; + + interrupts-extended =3D <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 0 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 1 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 2 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 3 IRQ_TYPE_NONE>; + interrupt-names =3D "wdog", "fatal", "ready", + "handover", "stop-ack"; + + resets =3D <&gcc GCC_WCSSAON_RESET>, + <&gcc GCC_WCSS_BCR>, + <&gcc GCC_WCSS_Q6_BCR>; + reset-names =3D "wcss_aon_reset", + "wcss_reset", + "wcss_q6_reset"; + + clocks =3D <&gcc GCC_ANOC_WCSS_AXI_M_CLK>, + <&gcc GCC_Q6_AHB_CLK>, + <&gcc GCC_Q6_AHB_S_CLK>, + <&gcc GCC_Q6_AXIM_CLK>, + <&gcc GCC_Q6SS_BOOT_CLK>, + <&gcc GCC_MEM_NOC_Q6_AXI_CLK>, + <&gcc GCC_SYS_NOC_WCSS_AHB_CLK>, + <&gcc GCC_WCSS_ACMT_CLK>, + <&gcc GCC_WCSS_ECAHB_CLK>, + <&gcc GCC_WCSS_Q6_TBU_CLK>, + <&gcc GCC_WCSS_AHB_S_CLK>, + <&gcc GCC_Q6_AXIM2_CLK>, + <&gcc GCC_WCSS_AXI_M_CLK>; + + clock-names =3D "anoc_wcss_axi_m", + "q6_ahb", + "q6_ahb_s", + "q6_axim", + "q6ss_boot", + "mem_noc_q6_axi", + "sys_noc_wcss_ahb", + "wcss_acmt", + "wcss_ecahb", + "wcss_q6_tbu", + "q6_axim2", + "wcss_ahb_s", + "wcss_axi_m"; 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[98.57.15.22]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-3ffa515f4dasm6274421fac.21.2026.01.08.20.34.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 20:34:11 -0800 (PST) From: Alexandru Gagniuc To: andersson@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, linux-remoteproc@vger.kernel.org, Konrad Dybcio , Rob Herring , Conor Dooley Cc: mathieu.poirier@linaro.org, sboyd@kernel.org, p.zabel@pengutronix.de, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Alexandru Gagniuc Subject: [PATCH v2 5/9] arm64: dts: qcom: ipq9574: add wcss remoteproc nodes Date: Thu, 8 Jan 2026 22:33:40 -0600 Message-ID: <20260109043352.3072933-6-mr.nuke.me@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20260109043352.3072933-1-mr.nuke.me@gmail.com> References: <20260109043352.3072933-1-mr.nuke.me@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The WCSS remoteproc is typically used by ath11k to load wifi firmware to the Hexagon q6 procesor. Add the nodes required to bring up this processor. Signed-off-by: Alexandru Gagniuc --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 101 ++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qc= om/ipq9574.dtsi index 86c9cb9fffc9..56e6f1370d6c 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -226,6 +226,37 @@ smem@4aa00000 { hwlocks =3D <&tcsr_mutex 3>; no-map; }; + + + q6_region: wcnss@4ab00000 { + no-map; + reg =3D <0x0 0x4ab00000 0x0 0x02b00000>; + }; + }; + + wcss: smp2p-wcss { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <435>, <428>; + + interrupt-parent =3D <&intc>; + interrupts =3D ; + + mboxes =3D <&apcs_glb 9>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <1>; + + wcss_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + qcom,smp2p-feature-ssr-ack; + #qcom,smem-state-cells =3D <1>; + }; + + wcss_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; }; =20 soc: soc@0 { @@ -903,6 +934,76 @@ frame@b128000 { }; }; =20 + q6v5_wcss: remoteproc@cd00000 { + compatible =3D "qcom,ipq9574-wcss-pil"; + reg =3D <0x0cd00000 0x4040>, + <0x004ab000 0x20>; + reg-names =3D "qdsp6", + "rmb"; + + interrupts-extended =3D <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 0 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 1 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 2 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 3 IRQ_TYPE_NONE>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + resets =3D <&gcc GCC_WCSSAON_RESET>, + <&gcc GCC_WCSS_BCR>, + <&gcc GCC_WCSS_Q6_BCR>; + reset-names =3D "wcss_aon_reset", + "wcss_reset", + "wcss_q6_reset"; + + clocks =3D <&gcc GCC_ANOC_WCSS_AXI_M_CLK>, + <&gcc GCC_Q6_AHB_CLK>, + <&gcc GCC_Q6_AHB_S_CLK>, + <&gcc GCC_Q6_AXIM_CLK>, + <&gcc GCC_Q6SS_BOOT_CLK>, + <&gcc GCC_MEM_NOC_Q6_AXI_CLK>, + <&gcc GCC_SYS_NOC_WCSS_AHB_CLK>, + <&gcc GCC_WCSS_ACMT_CLK>, + <&gcc GCC_WCSS_ECAHB_CLK>, + <&gcc GCC_WCSS_Q6_TBU_CLK>, + <&gcc GCC_WCSS_AHB_S_CLK>, + <&gcc GCC_Q6_AXIM2_CLK>, + <&gcc GCC_WCSS_AXI_M_CLK>; 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[98.57.15.22]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-3ffa515f4dasm6274421fac.21.2026.01.08.20.34.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 20:34:15 -0800 (PST) From: Alexandru Gagniuc To: andersson@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, linux-remoteproc@vger.kernel.org, Stephen Boyd Cc: mathieu.poirier@linaro.org, robh@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, p.zabel@pengutronix.de, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Alexandru Gagniuc Subject: [PATCH v2 6/9] clk: qcom: gcc-ipq9574: add wcss remoteproc clocks Date: Thu, 8 Jan 2026 22:33:41 -0600 Message-ID: <20260109043352.3072933-7-mr.nuke.me@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20260109043352.3072933-1-mr.nuke.me@gmail.com> References: <20260109043352.3072933-1-mr.nuke.me@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit fa1d525404b6 ("clk: qcom: ipq9574: remove q6 bring up clocks") removed these clocks on the idea that Q6 firmware is responsible for clock bringup. That statement seems incorrect, as these clocks need to be enabled before the Q6 is booted. Otherwise, the host CPU core that starts the Q6 hangs. Perhaps the statement meant that the TrustZone firmware will start the clocks. This only happens in PAS mode. Under native OS loading, the host needs to enable these clocks, so add them back. Besides the clocks that were erroneously removed, also add defines for GCC_WCSS_AHB_S_CLK, GCC_WCSS_AXI_M_CLK, and GCC_Q6_AXIM2_CLK. These clocks are required in order to operate the remoteproc. Signed-off-by: Alexandru Gagniuc --- drivers/clk/qcom/gcc-ipq9574.c | 378 +++++++++++++++++++++++++++++++++ 1 file changed, 378 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index 6dc86e686de4..aef5ed5cd9f5 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -2659,6 +2659,24 @@ static struct clk_rcg2 system_noc_bfdcd_clk_src =3D { }, }; =20 +static struct clk_branch gcc_q6ss_boot_clk =3D { + .halt_reg =3D 0x25080, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x25080, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_q6ss_boot_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &system_noc_bfdcd_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_nssnoc_snoc_clk =3D { .halt_reg =3D 0x17028, .clkr =3D { @@ -2729,6 +2747,108 @@ static struct clk_rcg2 wcss_ahb_clk_src =3D { }, }; =20 +static struct clk_branch gcc_q6_ahb_clk =3D { + .halt_reg =3D 0x25014, + .clkr =3D { + .enable_reg =3D 0x25014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_q6_ahb_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &wcss_ahb_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_q6_ahb_s_clk =3D { + .halt_reg =3D 0x25018, + .clkr =3D { + .enable_reg =3D 0x25018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_q6_ahb_s_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &wcss_ahb_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_ecahb_clk =3D { + .halt_reg =3D 0x25058, + .clkr =3D { + .enable_reg =3D 0x25058, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_wcss_ecahb_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &wcss_ahb_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_acmt_clk =3D { + .halt_reg =3D 0x2505c, + .clkr =3D { + .enable_reg =3D 0x2505c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_wcss_acmt_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &wcss_ahb_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + + +static struct clk_branch gcc_wcss_ahb_s_clk =3D { + .halt_reg =3D 0x25060, + .clkr =3D { + .enable_reg =3D 0x25060, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data) { + .name =3D "gcc_wcss_ahb_s_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &wcss_ahb_clk_src.clkr.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_wcss_ahb_clk =3D { + .halt_reg =3D 0x2e030, + .clkr =3D { + .enable_reg =3D 0x2e030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sys_noc_wcss_ahb_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &wcss_ahb_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + static const struct freq_tbl ftbl_wcss_axi_m_clk_src[] =3D { F(24000000, P_XO, 1, 0, 0), F(133333333, P_GPLL0, 6, 0, 0), @@ -2749,6 +2869,39 @@ static struct clk_rcg2 wcss_axi_m_clk_src =3D { }, }; =20 +static struct clk_branch gcc_wcss_axi_m_clk =3D { + .halt_reg =3D 0x25064, + .clkr =3D { + .enable_reg =3D 0x25064, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data) { + .name =3D "gcc_wcss_axi_m_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &wcss_axi_m_clk_src.clkr.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_anoc_wcss_axi_m_clk =3D { + .halt_reg =3D 0x2e0a8, + .clkr =3D { + .enable_reg =3D 0x2e0a8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_anoc_wcss_axi_m_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &wcss_axi_m_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + static const struct freq_tbl ftbl_qdss_at_clk_src[] =3D { F(240000000, P_GPLL4, 5, 0, 0), { } @@ -2767,6 +2920,40 @@ static struct clk_rcg2 qdss_at_clk_src =3D { }, }; =20 +static struct clk_branch gcc_q6ss_atbm_clk =3D { + .halt_reg =3D 0x2501c, + .clkr =3D { + .enable_reg =3D 0x2501c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_q6ss_atbm_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &qdss_at_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_dbg_ifc_atb_clk =3D { + .halt_reg =3D 0x2503c, + .clkr =3D { + .enable_reg =3D 0x2503c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_wcss_dbg_ifc_atb_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &qdss_at_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_nssnoc_atb_clk =3D { .halt_reg =3D 0x17014, .clkr =3D { @@ -3003,6 +3190,40 @@ static struct clk_fixed_factor qdss_tsctr_div2_clk_s= rc =3D { }, }; =20 +static struct clk_branch gcc_q6_tsctr_1to2_clk =3D { + .halt_reg =3D 0x25020, + .clkr =3D { + .enable_reg =3D 0x25020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_q6_tsctr_1to2_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &qdss_tsctr_div2_clk_src.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_dbg_ifc_nts_clk =3D { + .halt_reg =3D 0x25040, + .clkr =3D { + .enable_reg =3D 0x25040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_wcss_dbg_ifc_nts_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &qdss_tsctr_div2_clk_src.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_qdss_tsctr_div2_clk =3D { .halt_reg =3D 0x2d044, .clkr =3D { @@ -3177,6 +3398,74 @@ static struct clk_branch gcc_qdss_tsctr_div16_clk = =3D { }, }; =20 +static struct clk_branch gcc_q6ss_pclkdbg_clk =3D { + .halt_reg =3D 0x25024, + .clkr =3D { + .enable_reg =3D 0x25024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_q6ss_pclkdbg_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &qdss_dap_sync_clk_src.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_q6ss_trig_clk =3D { + .halt_reg =3D 0x25068, + .clkr =3D { + .enable_reg =3D 0x25068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_q6ss_trig_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &qdss_dap_sync_clk_src.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_dbg_ifc_apb_clk =3D { + .halt_reg =3D 0x25038, + .clkr =3D { + .enable_reg =3D 0x25038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_wcss_dbg_ifc_apb_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &qdss_dap_sync_clk_src.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk =3D { + .halt_reg =3D 0x25044, + .clkr =3D { + .enable_reg =3D 0x25044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_wcss_dbg_ifc_dapbus_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &qdss_dap_sync_clk_src.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_qdss_dap_clk =3D { .halt_reg =3D 0x2d058, .clkr =3D { @@ -3298,6 +3587,58 @@ static struct clk_rcg2 q6_axi_clk_src =3D { }, }; =20 +static struct clk_branch gcc_q6_axim_clk =3D { + .halt_reg =3D 0x2500c, + .clkr =3D { + .enable_reg =3D 0x2500c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_q6_axim_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &q6_axi_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_q6_tbu_clk =3D { + .halt_reg =3D 0x12050, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0xb00c, + .enable_mask =3D BIT(6), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_wcss_q6_tbu_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &q6_axi_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mem_noc_q6_axi_clk =3D { + .halt_reg =3D 0x19010, + .clkr =3D { + .enable_reg =3D 0x19010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_mem_noc_q6_axi_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &q6_axi_clk_src.clkr.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + static const struct freq_tbl ftbl_q6_axim2_clk_src[] =3D { F(342857143, P_GPLL4, 3.5, 0, 0), { } @@ -3323,6 +3664,22 @@ static struct clk_rcg2 q6_axim2_clk_src =3D { }, }; =20 +static struct clk_branch gcc_q6_axim2_clk =3D { + .halt_reg =3D 0x25010, + .clkr =3D { + .enable_reg =3D 0x25010, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data) { + .name =3D "gcc_q6_axim2_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &q6_axim2_clk_src.clkr.hw }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + static const struct freq_tbl ftbl_nssnoc_memnoc_bfdcd_clk_src[] =3D { F(533333333, P_GPLL0, 1.5, 0, 0), { } @@ -3847,8 +4204,18 @@ static struct clk_regmap *gcc_ipq9574_clks[] =3D { [GCC_NSSNOC_SNOC_1_CLK] =3D &gcc_nssnoc_snoc_1_clk.clkr, [GCC_QDSS_ETR_USB_CLK] =3D &gcc_qdss_etr_usb_clk.clkr, [WCSS_AHB_CLK_SRC] =3D &wcss_ahb_clk_src.clkr, + [GCC_Q6_AHB_CLK] =3D &gcc_q6_ahb_clk.clkr, + [GCC_Q6_AHB_S_CLK] =3D &gcc_q6_ahb_s_clk.clkr, + [GCC_WCSS_ECAHB_CLK] =3D &gcc_wcss_ecahb_clk.clkr, + [GCC_WCSS_ACMT_CLK] =3D &gcc_wcss_acmt_clk.clkr, + [GCC_WCSS_AHB_S_CLK] =3D &gcc_wcss_ahb_s_clk.clkr, + [GCC_SYS_NOC_WCSS_AHB_CLK] =3D &gcc_sys_noc_wcss_ahb_clk.clkr, [WCSS_AXI_M_CLK_SRC] =3D &wcss_axi_m_clk_src.clkr, + [GCC_WCSS_AXI_M_CLK] =3D &gcc_wcss_axi_m_clk.clkr, + [GCC_ANOC_WCSS_AXI_M_CLK] =3D &gcc_anoc_wcss_axi_m_clk.clkr, [QDSS_AT_CLK_SRC] =3D &qdss_at_clk_src.clkr, + [GCC_Q6SS_ATBM_CLK] =3D &gcc_q6ss_atbm_clk.clkr, + [GCC_WCSS_DBG_IFC_ATB_CLK] =3D &gcc_wcss_dbg_ifc_atb_clk.clkr, [GCC_NSSNOC_ATB_CLK] =3D &gcc_nssnoc_atb_clk.clkr, [GCC_QDSS_AT_CLK] =3D &gcc_qdss_at_clk.clkr, [GCC_SYS_NOC_AT_CLK] =3D &gcc_sys_noc_at_clk.clkr, @@ -3861,19 +4228,29 @@ static struct clk_regmap *gcc_ipq9574_clks[] =3D { [QDSS_TRACECLKIN_CLK_SRC] =3D &qdss_traceclkin_clk_src.clkr, [GCC_QDSS_TRACECLKIN_CLK] =3D &gcc_qdss_traceclkin_clk.clkr, [QDSS_TSCTR_CLK_SRC] =3D &qdss_tsctr_clk_src.clkr, + [GCC_Q6_TSCTR_1TO2_CLK] =3D &gcc_q6_tsctr_1to2_clk.clkr, + [GCC_WCSS_DBG_IFC_NTS_CLK] =3D &gcc_wcss_dbg_ifc_nts_clk.clkr, [GCC_QDSS_TSCTR_DIV2_CLK] =3D &gcc_qdss_tsctr_div2_clk.clkr, [GCC_QDSS_TS_CLK] =3D &gcc_qdss_ts_clk.clkr, [GCC_QDSS_TSCTR_DIV4_CLK] =3D &gcc_qdss_tsctr_div4_clk.clkr, [GCC_NSS_TS_CLK] =3D &gcc_nss_ts_clk.clkr, [GCC_QDSS_TSCTR_DIV8_CLK] =3D &gcc_qdss_tsctr_div8_clk.clkr, [GCC_QDSS_TSCTR_DIV16_CLK] =3D &gcc_qdss_tsctr_div16_clk.clkr, + [GCC_Q6SS_PCLKDBG_CLK] =3D &gcc_q6ss_pclkdbg_clk.clkr, + [GCC_Q6SS_TRIG_CLK] =3D &gcc_q6ss_trig_clk.clkr, + [GCC_WCSS_DBG_IFC_APB_CLK] =3D &gcc_wcss_dbg_ifc_apb_clk.clkr, + [GCC_WCSS_DBG_IFC_DAPBUS_CLK] =3D &gcc_wcss_dbg_ifc_dapbus_clk.clkr, [GCC_QDSS_DAP_CLK] =3D &gcc_qdss_dap_clk.clkr, [GCC_QDSS_APB2JTAG_CLK] =3D &gcc_qdss_apb2jtag_clk.clkr, [GCC_QDSS_TSCTR_DIV3_CLK] =3D &gcc_qdss_tsctr_div3_clk.clkr, [QPIC_IO_MACRO_CLK_SRC] =3D &qpic_io_macro_clk_src.clkr, [GCC_QPIC_IO_MACRO_CLK] =3D &gcc_qpic_io_macro_clk.clkr, [Q6_AXI_CLK_SRC] =3D &q6_axi_clk_src.clkr, + [GCC_Q6_AXIM_CLK] =3D &gcc_q6_axim_clk.clkr, + [GCC_WCSS_Q6_TBU_CLK] =3D &gcc_wcss_q6_tbu_clk.clkr, + [GCC_MEM_NOC_Q6_AXI_CLK] =3D &gcc_mem_noc_q6_axi_clk.clkr, [Q6_AXIM2_CLK_SRC] =3D &q6_axim2_clk_src.clkr, + [GCC_Q6_AXIM2_CLK] =3D &gcc_q6_axim2_clk.clkr, [NSSNOC_MEMNOC_BFDCD_CLK_SRC] =3D &nssnoc_memnoc_bfdcd_clk_src.clkr, [GCC_NSSNOC_MEMNOC_CLK] =3D &gcc_nssnoc_memnoc_clk.clkr, [GCC_NSSNOC_MEM_NOC_1_CLK] =3D &gcc_nssnoc_mem_noc_1_clk.clkr, @@ -3896,6 +4273,7 @@ static struct clk_regmap *gcc_ipq9574_clks[] =3D { [GCC_UNIPHY1_SYS_CLK] =3D &gcc_uniphy1_sys_clk.clkr, [GCC_UNIPHY2_SYS_CLK] =3D &gcc_uniphy2_sys_clk.clkr, [GCC_CMN_12GPLL_SYS_CLK] =3D &gcc_cmn_12gpll_sys_clk.clkr, + [GCC_Q6SS_BOOT_CLK] =3D &gcc_q6ss_boot_clk.clkr, [UNIPHY_SYS_CLK_SRC] =3D &uniphy_sys_clk_src.clkr, [NSS_TS_CLK_SRC] =3D &nss_ts_clk_src.clkr, [GCC_ANOC_PCIE0_1LANE_M_CLK] =3D &gcc_anoc_pcie0_1lane_m_clk.clkr, --=20 2.45.1 From nobody Sun Feb 8 02:21:45 2026 Received: from mail-oa1-f46.google.com (mail-oa1-f46.google.com [209.85.160.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F39D92550D5 for ; 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[98.57.15.22]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-3ffa515f4dasm6274421fac.21.2026.01.08.20.34.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 20:34:18 -0800 (PST) From: Alexandru Gagniuc To: andersson@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, linux-remoteproc@vger.kernel.org, Mathieu Poirier , Philipp Zabel Cc: robh@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Alexandru Gagniuc Subject: [PATCH v2 7/9] remoteproc: qcom_q6v5_wcss: support IPQ9574 Date: Thu, 8 Jan 2026 22:33:42 -0600 Message-ID: <20260109043352.3072933-8-mr.nuke.me@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20260109043352.3072933-1-mr.nuke.me@gmail.com> References: <20260109043352.3072933-1-mr.nuke.me@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Q6 based firmware loading is also present on IPQ9574, when coupled with a wifi-6 device, such as QCN5024. Populate driver data for IPQ9574 with values from the downstream 5.4 kerrnel. Add the new sequences for the WCSS reset and stop. The downstream 5.4 kernel calls these "Q6V7", so keep the name. This is still worth using with the "q6v5" driver because all other parts of the driver can be seamlessly reused. The IPQ9574 uses two sets of clocks. the first, dubbed "pre_boot_clks" must be enabled before the Q6 is started by writing the Q6SS_RST_EVB register. The second set of clocks, "clks" should only be enabled after the Q6 is placed out of reset. Otherwise, the host CPU core that tries to start the remoteproc will hang. The shutdown path requires a small delay between asserting the Q6 and WCSS resets. The delay is handled in q6v7_q6_powerdown(). Also add it in the error path of q6v5_wcss_start(). The downstream kernel had a funny comment, "Pray god and wait for reset to complete", which I decided to keep for entertainment value. Signed-off-by: Alexandru Gagniuc --- Changes since v1: - rename "q6_clks" to "pre_boot_clks" - drop step numbers from q6v7_wcss_reset() comments - disable clocks on init failures in q6v7_wcss_reset() - Add Q6SS_CBCR_CLKEN macro --- drivers/remoteproc/qcom_q6v5_wcss.c | 253 +++++++++++++++++++++++++++- 1 file changed, 246 insertions(+), 7 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_= q6v5_wcss.c index 07bba47eb084..ccf5fbc5be66 100644 --- a/drivers/remoteproc/qcom_q6v5_wcss.c +++ b/drivers/remoteproc/qcom_q6v5_wcss.c @@ -31,6 +31,9 @@ #define Q6SS_MEM_PWR_CTL 0x0B0 #define Q6SS_STRAP_ACC 0x110 #define Q6SS_CGC_OVERRIDE 0x034 +#define Q6SS_BOOT_CORE_START 0x400 +#define Q6SS_BOOT_CMD 0x404 +#define Q6SS_BOOT_STATUS 0x408 #define Q6SS_BCR_REG 0x6000 =20 /* AXI Halt Register Offsets */ @@ -48,7 +51,11 @@ /* Q6SS_BRC_RESET */ #define Q6SS_BRC_BLK_ARES BIT(0) =20 +/* QDSP6SS CBCR */ +#define Q6SS_CBCR_CLKEN BIT(0) + /* Q6SS_GFMUX_CTL */ +#define Q6SS_CLK_SRC_MUX BIT(0) #define Q6SS_CLK_ENABLE BIT(1) #define Q6SS_SWITCH_CLK_SRC BIT(8) =20 @@ -67,6 +74,7 @@ #define HALT_CHECK_MAX_LOOPS 200 #define Q6SS_XO_CBCR GENMASK(5, 3) #define Q6SS_SLEEP_CBCR GENMASK(5, 2) +#define Q6SS_CORE_CBCR BIT(5) =20 /* Q6SS config/status registers */ #define TCSR_GLOBAL_CFG0 0x0 @@ -77,9 +85,11 @@ #define Q6SS_RST_EVB 0x10 =20 #define BHS_EN_REST_ACK BIT(0) +#define WCSS_HM_RET BIT(1) #define SSCAON_ENABLE BIT(13) #define SSCAON_BUS_EN BIT(15) #define SSCAON_BUS_MUX_MASK GENMASK(18, 16) +#define SSCAON_MASK GENMASK(17, 15) =20 #define MEM_BANKS 19 #define TCSR_WCSS_CLK_MASK 0x1F @@ -88,6 +98,7 @@ #define MAX_HALT_REG 4 enum { WCSS_IPQ8074, + WCSS_IPQ9574, WCSS_QCS404, }; =20 @@ -125,6 +136,12 @@ struct q6v5_wcss { struct clk *qdsp6ss_abhm_cbcr; struct clk *qdsp6ss_axim_cbcr; struct clk *lcc_bcr_sleep; + struct clk_bulk_data *clks; + /* clocks that must be started before the Q6 is booted */ + struct clk_bulk_data *pre_boot_clks; + int num_clks; + int num_pre_boot_clks; + struct regulator *cx_supply; struct qcom_sysmon *sysmon; =20 @@ -233,6 +250,97 @@ static int q6v5_wcss_reset(struct q6v5_wcss *wcss) return 0; } =20 +static int q6v7_wcss_reset(struct q6v5_wcss *wcss, struct rproc *rproc) +{ + int ret; + u32 val; + + ret =3D regmap_update_bits(wcss->halt_map, + wcss->halt_nc + TCSR_GLOBAL_CFG1, + 0xff00, 0x1100); + if (ret) { + dev_err(wcss->dev, "TCSR_GLOBAL_CFG1 failed\n"); + return ret; + } + + ret =3D clk_bulk_prepare_enable(wcss->num_pre_boot_clks, + wcss->pre_boot_clks); + if (ret) { + dev_err(wcss->dev, "failed to enable clocks, err=3D%d\n", ret); + return ret; + }; + + /* Write bootaddr to Q6WCSS */ + writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB); + + /* Deassert AON Reset */ + ret =3D reset_control_deassert(wcss->wcss_aon_reset); + if (ret) { + dev_err(wcss->dev, "wcss_aon_reset failed\n"); + goto disable_pre_boot_clocks; + return ret; + } + + /* Set MPM configs*/ + /*set CFG[18:15]=3D1*/ + val =3D readl(wcss->rmb_base + SSCAON_CONFIG); + val &=3D ~SSCAON_MASK; + val |=3D SSCAON_BUS_EN; + writel(val, wcss->rmb_base + SSCAON_CONFIG); + + /* Wait for SSCAON_STATUS, up to 1 second */ + ret =3D readl_poll_timeout(wcss->rmb_base + SSCAON_STATUS, + val, (val & 0xffff) =3D=3D 0x10, 1000, 1000000); + if (ret) { + dev_err(wcss->dev, " Boot Error, SSCAON=3D0x%08X\n", val); + goto assert_aon_reset; + } + + /* BHS require xo cbcr to be enabled */ + val =3D readl(wcss->reg_base + Q6SS_XO_CBCR); + val |=3D Q6SS_CBCR_CLKEN; + writel(val, wcss->reg_base + Q6SS_XO_CBCR); + + /* Enable core cbcr */ + val =3D readl(wcss->reg_base + Q6SS_CORE_CBCR); + val |=3D Q6SS_CBCR_CLKEN; + writel(val, wcss->reg_base + Q6SS_CORE_CBCR); + + /* Enable sleep cbcr */ + val =3D readl(wcss->reg_base + Q6SS_SLEEP_CBCR); + val |=3D Q6SS_CBCR_CLKEN; + writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR); + + /* Boot core start */ + writel(0x1, wcss->reg_base + Q6SS_BOOT_CORE_START); + writel(0x1, wcss->reg_base + Q6SS_BOOT_CMD); + + /* Pray god and wait for reset to complete */ + ret =3D readl_poll_timeout(wcss->reg_base + Q6SS_BOOT_STATUS, val, + (val & BIT(0)), 1000, 20000); + if (ret) { + dev_err(wcss->dev, "WCSS boot timed out\n"); + ret =3D -ETIMEDOUT; + goto assert_aon_reset; + } + + /* Enable post-boot clocks */ + ret =3D clk_bulk_prepare_enable(wcss->num_clks, wcss->clks); + if (ret) { + dev_err(wcss->dev, "failed to enable clocks, err=3D%d\n", ret); + goto assert_aon_reset; + }; + + return 0; + +assert_aon_reset: + reset_control_assert(wcss->wcss_aon_reset); +disable_pre_boot_clocks: + clk_bulk_disable_unprepare(wcss->num_pre_boot_clks, + wcss->pre_boot_clks); + return ret; +} + static int q6v5_wcss_start(struct rproc *rproc) { struct q6v5_wcss *wcss =3D rproc->priv; @@ -267,10 +375,18 @@ static int q6v5_wcss_start(struct rproc *rproc) if (ret) goto wcss_q6_reset; =20 - /* Write bootaddr to EVB so that Q6WCSS will jump there after reset */ - writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB); + switch (wcss->version) { + case WCSS_QCS404: + case WCSS_IPQ8074: + /* Write bootaddr to Q6WCSS */ + writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB); + ret =3D q6v5_wcss_reset(wcss); + break; + case WCSS_IPQ9574: + ret =3D q6v7_wcss_reset(wcss, rproc); + break; + } =20 - ret =3D q6v5_wcss_reset(wcss); if (ret) goto wcss_q6_reset; =20 @@ -282,6 +398,7 @@ static int q6v5_wcss_start(struct rproc *rproc) =20 wcss_q6_reset: reset_control_assert(wcss->wcss_q6_reset); + usleep_range(1000, 2000); =20 wcss_reset: reset_control_assert(wcss->wcss_reset); @@ -635,6 +752,41 @@ static int q6v5_wcss_powerdown(struct q6v5_wcss *wcss) return 0; } =20 +static int q6v7_wcss_powerdown(struct q6v5_wcss *wcss) +{ + u32 val; + int ret; + + q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_wcss); + + val =3D readl(wcss->rmb_base + SSCAON_CONFIG); + val &=3D ~SSCAON_MASK; + val |=3D SSCAON_BUS_EN; + writel(val, wcss->rmb_base + SSCAON_CONFIG); + + val |=3D WCSS_HM_RET; + writel(val, wcss->rmb_base + SSCAON_CONFIG); + + ret =3D readl_poll_timeout(wcss->rmb_base + SSCAON_STATUS, + val, (val & 0xffff) =3D=3D 0x400, 1000, + HALT_CHECK_MAX_LOOPS); + if (ret) { + dev_err(wcss->dev, + "can't get SSCAON_STATUS rc:%d)\n", ret); + return ret; + } + + usleep_range(2000, 4000); + + reset_control_assert(wcss->wcss_aon_reset); + + val =3D readl(wcss->rmb_base + SSCAON_CONFIG); + val &=3D ~WCSS_HM_RET; + writel(val, wcss->rmb_base + SSCAON_CONFIG); + + return 0; +} + static int q6v5_q6_powerdown(struct q6v5_wcss *wcss) { int ret; @@ -702,6 +854,26 @@ static int q6v5_q6_powerdown(struct q6v5_wcss *wcss) return 0; } =20 +static void q6v7_q6_powerdown(struct q6v5_wcss *wcss) +{ + u32 val; + + q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_q6); + + /* Disable Q6 Core clock */ + val =3D readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); + val &=3D ~Q6SS_CLK_SRC_MUX; + writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); + + clk_bulk_disable_unprepare(wcss->num_clks, wcss->clks); + clk_bulk_disable_unprepare(wcss->num_pre_boot_clks, + wcss->pre_boot_clks); + + reset_control_assert(wcss->wcss_q6_reset); + usleep_range(1000, 2000); + reset_control_assert(wcss->wcss_reset); +} + static int q6v5_wcss_stop(struct rproc *rproc) { struct q6v5_wcss *wcss =3D rproc->priv; @@ -716,11 +888,21 @@ static int q6v5_wcss_stop(struct rproc *rproc) } } =20 - if (wcss->version =3D=3D WCSS_QCS404) { + switch (wcss->version) { + case WCSS_QCS404: ret =3D q6v5_qcs404_wcss_shutdown(wcss); if (ret) return ret; - } else { + break; + case WCSS_IPQ9574: + ret =3D q6v7_wcss_powerdown(wcss); + if (ret) + return ret; + + q6v7_q6_powerdown(wcss); + + break; + default: ret =3D q6v5_wcss_powerdown(wcss); if (ret) return ret; @@ -729,6 +911,7 @@ static int q6v5_wcss_stop(struct rproc *rproc) ret =3D q6v5_q6_powerdown(wcss); if (ret) return ret; + break; } =20 qcom_q6v5_unprepare(&wcss->q6v5); @@ -835,7 +1018,9 @@ static int q6v5_wcss_init_mmio(struct q6v5_wcss *wcss, if (!wcss->reg_base) return -ENOMEM; =20 - if (wcss->version =3D=3D WCSS_IPQ8074) { + switch (wcss->version) { + case WCSS_IPQ8074: + case WCSS_IPQ9574: wcss->rmb_base =3D devm_platform_ioremap_resource_byname(pdev, "rmb"); if (IS_ERR(wcss->rmb_base)) return PTR_ERR(wcss->rmb_base); @@ -962,6 +1147,43 @@ static int q6v5_wcss_init_regulator(struct q6v5_wcss = *wcss) return 0; } =20 +static int ipq9574_init_clocks(struct q6v5_wcss *wcss) +{ + static const char *const pre_boot_clks[] =3D { + "anoc_wcss_axi_m", "q6_ahb", "q6_ahb_s", "q6_axim", "q6ss_boot", + "mem_noc_q6_axi", "sys_noc_wcss_ahb", "wcss_acmt", "wcss_ecahb", + "wcss_q6_tbu" }; + static const char *const clks[] =3D { + "q6_axim2", "wcss_ahb_s", "wcss_axi_m" }; + int i, ret; + + wcss->num_clks =3D ARRAY_SIZE(clks); + wcss->num_pre_boot_clks =3D ARRAY_SIZE(pre_boot_clks); + + wcss->pre_boot_clks =3D devm_kcalloc(wcss->dev, wcss->num_pre_boot_clks, + sizeof(*wcss->pre_boot_clks), GFP_KERNEL); + if (!wcss->pre_boot_clks) + return -ENOMEM; + + wcss->clks =3D devm_kcalloc(wcss->dev, wcss->num_clks, + sizeof(*wcss->clks), GFP_KERNEL); + if (!wcss->clks) + return -ENOMEM; + + for (i =3D 0; i < wcss->num_pre_boot_clks; i++) + wcss->pre_boot_clks[i].id =3D pre_boot_clks[i]; + + for (i =3D 0; i < wcss->num_clks; i++) + wcss->clks[i].id =3D clks[i]; + + ret =3D devm_clk_bulk_get(wcss->dev, wcss->num_pre_boot_clks, + wcss->pre_boot_clks); + if (ret < 0) + return ret; + + return devm_clk_bulk_get(wcss->dev, wcss->num_clks, wcss->clks); +} + static int q6v5_wcss_probe(struct platform_device *pdev) { const struct wcss_data *desc; @@ -994,7 +1216,8 @@ static int q6v5_wcss_probe(struct platform_device *pde= v) if (ret) return ret; =20 - if (wcss->version =3D=3D WCSS_QCS404) { + switch (wcss->version) { + case WCSS_QCS404: ret =3D q6v5_wcss_init_clock(wcss); if (ret) return ret; @@ -1002,6 +1225,11 @@ static int q6v5_wcss_probe(struct platform_device *p= dev) ret =3D q6v5_wcss_init_regulator(wcss); if (ret) return ret; + break; + case WCSS_IPQ9574: + ret =3D ipq9574_init_clocks(wcss); + if (ret) + return ret; } =20 ret =3D q6v5_wcss_init_reset(wcss, desc); @@ -1064,6 +1292,16 @@ static const struct wcss_data wcss_ipq8074_res_init = =3D { .requires_force_stop =3D true, }; =20 +static const struct wcss_data wcss_ipq9574_res_init =3D { + .firmware_name =3D "IPQ9574/q6_fw.mdt", + .version =3D WCSS_IPQ9574, + .crash_reason_smem =3D WCSS_CRASH_REASON, + .aon_reset_required =3D true, + .ssr_name =3D "q6wcss", + .ops =3D &q6v5_wcss_ipq8074_ops, + .requires_force_stop =3D true, +}; + static const struct wcss_data wcss_qcs404_res_init =3D { .crash_reason_smem =3D WCSS_CRASH_REASON, .firmware_name =3D "wcnss.mdt", @@ -1079,6 +1317,7 @@ static const struct wcss_data wcss_qcs404_res_init = =3D { =20 static const struct of_device_id q6v5_wcss_of_match[] =3D { { .compatible =3D "qcom,ipq8074-wcss-pil", .data =3D &wcss_ipq8074_res_in= it }, + { .compatible =3D "qcom,ipq9574-wcss-pil", .data =3D &wcss_ipq9574_res_in= it }, { .compatible =3D "qcom,qcs404-wcss-pil", .data =3D &wcss_qcs404_res_init= }, { }, }; --=20 2.45.1 From nobody Sun Feb 8 02:21:45 2026 Received: from mail-oa1-f50.google.com (mail-oa1-f50.google.com [209.85.160.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE3192D8377 for ; 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[98.57.15.22]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-3ffa515f4dasm6274421fac.21.2026.01.08.20.34.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 20:34:20 -0800 (PST) From: Alexandru Gagniuc To: andersson@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, linux-remoteproc@vger.kernel.org, Mathieu Poirier Cc: robh@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, sboyd@kernel.org, p.zabel@pengutronix.de, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Alexandru Gagniuc Subject: [PATCH v2 8/9] remoteproc: qcom_q6v5_wcss: support m3 firmware Date: Thu, 8 Jan 2026 22:33:43 -0600 Message-ID: <20260109043352.3072933-9-mr.nuke.me@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20260109043352.3072933-1-mr.nuke.me@gmail.com> References: <20260109043352.3072933-1-mr.nuke.me@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" IPQ8074, IPQ6018, and IPQ9574 support an m3 firmware image in addtion to the q6 firmware. The firmware releases from qcom provide both q6 and m3 firmware for these SoCs. Support loading the m3 firmware image. Signed-off-by: Alexandru Gagniuc --- Changes since v1: - Check for -ENOENT from q6v5_wcss_load_aux() --- drivers/remoteproc/qcom_q6v5_wcss.c | 45 +++++++++++++++++++++++++---- 1 file changed, 40 insertions(+), 5 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_= q6v5_wcss.c index ccf5fbc5be66..2bb83e6afb6b 100644 --- a/drivers/remoteproc/qcom_q6v5_wcss.c +++ b/drivers/remoteproc/qcom_q6v5_wcss.c @@ -103,7 +103,8 @@ enum { }; =20 struct wcss_data { - const char *firmware_name; + const char *q6_firmware_name; + const char *m3_firmware_name; unsigned int crash_reason_smem; u32 version; bool aon_reset_required; @@ -160,6 +161,7 @@ struct q6v5_wcss { unsigned int crash_reason_smem; u32 version; bool requires_force_stop; + const char *m3_firmware_name; =20 struct qcom_rproc_glink glink_subdev; struct qcom_rproc_pdm pdm_subdev; @@ -931,11 +933,41 @@ static void *q6v5_wcss_da_to_va(struct rproc *rproc, = u64 da, size_t len, bool *i return wcss->mem_region + offset; } =20 +static int q6v5_wcss_load_aux(struct q6v5_wcss *wcss, const char *fw_name) +{ + const struct firmware *extra_fw; + int ret; + + dev_info(wcss->dev, "loading additional firmware image %s\n", fw_name); + + ret =3D request_firmware(&extra_fw, fw_name, wcss->dev); + if (ret) + return ret; + + ret =3D qcom_mdt_load_no_init(wcss->dev, extra_fw, fw_name, + wcss->mem_region, wcss->mem_phys, + wcss->mem_size, &wcss->mem_reloc); + + release_firmware(extra_fw); + + if (ret) + dev_err(wcss->dev, "can't load %s\n", fw_name); + + return ret; +} + static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw) { struct q6v5_wcss *wcss =3D rproc->priv; int ret; =20 + if (wcss->m3_firmware_name) { + ret =3D q6v5_wcss_load_aux(wcss, wcss->m3_firmware_name); + /* Continue if M3 firmware does not exist */ + if (ret && (ret !=3D -ENOENT)) + return ret; + } + ret =3D qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware, wcss->mem_region, wcss->mem_phys, wcss->mem_size, &wcss->mem_reloc); @@ -1196,7 +1228,7 @@ static int q6v5_wcss_probe(struct platform_device *pd= ev) return -EINVAL; =20 rproc =3D devm_rproc_alloc(&pdev->dev, pdev->name, desc->ops, - desc->firmware_name, sizeof(*wcss)); + desc->q6_firmware_name, sizeof(*wcss)); if (!rproc) { dev_err(&pdev->dev, "failed to allocate rproc\n"); return -ENOMEM; @@ -1207,6 +1239,7 @@ static int q6v5_wcss_probe(struct platform_device *pd= ev) =20 wcss->version =3D desc->version; wcss->requires_force_stop =3D desc->requires_force_stop; + wcss->m3_firmware_name =3D desc->m3_firmware_name; =20 ret =3D q6v5_wcss_init_mmio(wcss, pdev); if (ret) @@ -1284,7 +1317,8 @@ static void q6v5_wcss_remove(struct platform_device *= pdev) } =20 static const struct wcss_data wcss_ipq8074_res_init =3D { - .firmware_name =3D "IPQ8074/q6_fw.mdt", + .q6_firmware_name =3D "IPQ8074/q6_fw.mdt", + .m3_firmware_name =3D "IPQ8074/m3_fw.mdt", .crash_reason_smem =3D WCSS_CRASH_REASON, .aon_reset_required =3D true, .wcss_q6_reset_required =3D true, @@ -1293,7 +1327,8 @@ static const struct wcss_data wcss_ipq8074_res_init = =3D { }; =20 static const struct wcss_data wcss_ipq9574_res_init =3D { - .firmware_name =3D "IPQ9574/q6_fw.mdt", + .q6_firmware_name =3D "IPQ9574/q6_fw.mdt", + .m3_firmware_name =3D "IPQ9574/m3_fw.mdt", .version =3D WCSS_IPQ9574, .crash_reason_smem =3D WCSS_CRASH_REASON, .aon_reset_required =3D true, @@ -1304,7 +1339,7 @@ static const struct wcss_data wcss_ipq9574_res_init = =3D { =20 static const struct wcss_data wcss_qcs404_res_init =3D { .crash_reason_smem =3D WCSS_CRASH_REASON, - .firmware_name =3D "wcnss.mdt", + .q6_firmware_name =3D "wcnss.mdt", .version =3D WCSS_QCS404, .aon_reset_required =3D false, .wcss_q6_reset_required =3D false, --=20 2.45.1 From nobody Sun Feb 8 02:21:45 2026 Received: from mail-oa1-f45.google.com (mail-oa1-f45.google.com [209.85.160.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B7AF19309C for ; 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[98.57.15.22]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-3ffa515f4dasm6274421fac.21.2026.01.08.20.34.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 20:34:22 -0800 (PST) From: Alexandru Gagniuc To: andersson@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, linux-remoteproc@vger.kernel.org, Mathieu Poirier Cc: robh@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, sboyd@kernel.org, p.zabel@pengutronix.de, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Alexandru Gagniuc Subject: [PATCH v2 9/9] remoteproc: qcom_q6v5_wcss: use bulk clk API for q6 clocks in QCS404 Date: Thu, 8 Jan 2026 22:33:44 -0600 Message-ID: <20260109043352.3072933-10-mr.nuke.me@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20260109043352.3072933-1-mr.nuke.me@gmail.com> References: <20260109043352.3072933-1-mr.nuke.me@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Five of the clocks on QCS404 are consistently enabled and disabled together. Use the bulk clock API to get and enable them. They are enabled after the Q6 reset is deasserted, implying that pre_boot is not the appropriate designator. Store them in wcss->clks. Signed-off-by: Alexandru Gagniuc --- Changes since v1: - Use wcss->clks, since wcss->q6_clks has been renamed. --- drivers/remoteproc/qcom_q6v5_wcss.c | 99 ++++++++--------------------- 1 file changed, 28 insertions(+), 71 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_= q6v5_wcss.c index 2bb83e6afb6b..3c1794fde3f0 100644 --- a/drivers/remoteproc/qcom_q6v5_wcss.c +++ b/drivers/remoteproc/qcom_q6v5_wcss.c @@ -128,14 +128,9 @@ struct q6v5_wcss { u32 halt_nc; =20 struct clk *xo; - struct clk *ahbfabric_cbcr_clk; struct clk *gcc_abhs_cbcr; struct clk *gcc_axim_cbcr; - struct clk *lcc_csr_cbcr; struct clk *ahbs_cbcr; - struct clk *tcm_slave_cbcr; - struct clk *qdsp6ss_abhm_cbcr; - struct clk *qdsp6ss_axim_cbcr; struct clk *lcc_bcr_sleep; struct clk_bulk_data *clks; /* clocks that must be started before the Q6 is booted */ @@ -427,35 +422,16 @@ static int q6v5_wcss_qcs404_power_on(struct q6v5_wcss= *wcss) /* Remove reset to the WCNSS QDSP6SS */ reset_control_deassert(wcss->wcss_q6_bcr_reset); =20 - /* Enable Q6SSTOP_AHBFABRIC_CBCR clock */ - ret =3D clk_prepare_enable(wcss->ahbfabric_cbcr_clk); - if (ret) + ret =3D clk_bulk_prepare_enable(wcss->num_clks, wcss->clks); + if (ret) { + dev_err(wcss->dev, "failed to enable q6 clocks, err=3D%d\n", ret); goto disable_gcc_abhs_cbcr_clk; - - /* Enable the LCCCSR CBC clock, Q6SSTOP_Q6SSTOP_LCC_CSR_CBCR clock */ - ret =3D clk_prepare_enable(wcss->lcc_csr_cbcr); - if (ret) - goto disable_ahbfabric_cbcr_clk; + }; =20 /* Enable the Q6AHBS CBC, Q6SSTOP_Q6SS_AHBS_CBCR clock */ ret =3D clk_prepare_enable(wcss->ahbs_cbcr); if (ret) - goto disable_csr_cbcr_clk; - - /* Enable the TCM slave CBC, Q6SSTOP_Q6SS_TCM_SLAVE_CBCR clock */ - ret =3D clk_prepare_enable(wcss->tcm_slave_cbcr); - if (ret) - goto disable_ahbs_cbcr_clk; - - /* Enable the Q6SS AHB master CBC, Q6SSTOP_Q6SS_AHBM_CBCR clock */ - ret =3D clk_prepare_enable(wcss->qdsp6ss_abhm_cbcr); - if (ret) - goto disable_tcm_slave_cbcr_clk; - - /* Enable the Q6SS AXI master CBC, Q6SSTOP_Q6SS_AXIM_CBCR clock */ - ret =3D clk_prepare_enable(wcss->qdsp6ss_axim_cbcr); - if (ret) - goto disable_abhm_cbcr_clk; + goto disable_clks; =20 /* Enable the Q6SS XO CBC */ val =3D readl(wcss->reg_base + Q6SS_XO_CBCR); @@ -538,17 +514,9 @@ static int q6v5_wcss_qcs404_power_on(struct q6v5_wcss = *wcss) val =3D readl(wcss->reg_base + Q6SS_XO_CBCR); val &=3D ~Q6SS_CLK_ENABLE; writel(val, wcss->reg_base + Q6SS_XO_CBCR); - clk_disable_unprepare(wcss->qdsp6ss_axim_cbcr); -disable_abhm_cbcr_clk: - clk_disable_unprepare(wcss->qdsp6ss_abhm_cbcr); -disable_tcm_slave_cbcr_clk: - clk_disable_unprepare(wcss->tcm_slave_cbcr); -disable_ahbs_cbcr_clk: clk_disable_unprepare(wcss->ahbs_cbcr); -disable_csr_cbcr_clk: - clk_disable_unprepare(wcss->lcc_csr_cbcr); -disable_ahbfabric_cbcr_clk: - clk_disable_unprepare(wcss->ahbfabric_cbcr_clk); +disable_clks: + clk_bulk_disable_unprepare(wcss->num_clks, wcss->clks); disable_gcc_abhs_cbcr_clk: clk_disable_unprepare(wcss->gcc_abhs_cbcr); =20 @@ -666,11 +634,7 @@ static int q6v5_qcs404_wcss_shutdown(struct q6v5_wcss = *wcss) val &=3D ~Q6SS_BHS_ON; writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); =20 - clk_disable_unprepare(wcss->ahbfabric_cbcr_clk); - clk_disable_unprepare(wcss->lcc_csr_cbcr); - clk_disable_unprepare(wcss->tcm_slave_cbcr); - clk_disable_unprepare(wcss->qdsp6ss_abhm_cbcr); - clk_disable_unprepare(wcss->qdsp6ss_axim_cbcr); + clk_bulk_disable_unprepare(wcss->num_clks, wcss->clks); =20 val =3D readl(wcss->reg_base + Q6SS_SLEEP_CBCR); val &=3D ~BIT(0); @@ -1112,6 +1076,20 @@ static int q6v5_alloc_memory_region(struct q6v5_wcss= *wcss) =20 static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss) { + static const char *const bulk_clks[] =3D { + "lcc_ahbfabric_cbc", "tcsr_lcc_cbc", "lcc_tcm_slave_cbc", + "lcc_abhm_cbc", "lcc_axim_cbc" }; + int ret, i; + + wcss->num_clks =3D ARRAY_SIZE(bulk_clks); + wcss->clks =3D devm_kcalloc(wcss->dev, wcss->num_clks, + sizeof(*wcss->clks), GFP_KERNEL); + if (!wcss->clks) + return -ENOMEM; + + for (i =3D 0; i < wcss->num_clks; i++) + wcss->clks[i].id =3D bulk_clks[i]; + wcss->xo =3D devm_clk_get(wcss->dev, "xo"); if (IS_ERR(wcss->xo)) return dev_err_probe(wcss->dev, PTR_ERR(wcss->xo), @@ -1127,44 +1105,23 @@ static int q6v5_wcss_init_clock(struct q6v5_wcss *w= css) return dev_err_probe(wcss->dev, PTR_ERR(wcss->gcc_axim_cbcr), "failed to get gcc axim clock\n"); =20 - wcss->ahbfabric_cbcr_clk =3D devm_clk_get(wcss->dev, - "lcc_ahbfabric_cbc"); - if (IS_ERR(wcss->ahbfabric_cbcr_clk)) - return dev_err_probe(wcss->dev, PTR_ERR(wcss->ahbfabric_cbcr_clk), - "failed to get ahbfabric clock\n"); - - wcss->lcc_csr_cbcr =3D devm_clk_get(wcss->dev, "tcsr_lcc_cbc"); - if (IS_ERR(wcss->lcc_csr_cbcr)) - return dev_err_probe(wcss->dev, PTR_ERR(wcss->lcc_csr_cbcr), - "failed to get csr cbcr clk\n"); - wcss->ahbs_cbcr =3D devm_clk_get(wcss->dev, "lcc_abhs_cbc"); if (IS_ERR(wcss->ahbs_cbcr)) return dev_err_probe(wcss->dev, PTR_ERR(wcss->ahbs_cbcr), "failed to get ahbs_cbcr clk\n"); =20 - wcss->tcm_slave_cbcr =3D devm_clk_get(wcss->dev, - "lcc_tcm_slave_cbc"); - if (IS_ERR(wcss->tcm_slave_cbcr)) - return dev_err_probe(wcss->dev, PTR_ERR(wcss->tcm_slave_cbcr), - "failed to get tcm cbcr clk\n"); - - wcss->qdsp6ss_abhm_cbcr =3D devm_clk_get(wcss->dev, "lcc_abhm_cbc"); - if (IS_ERR(wcss->qdsp6ss_abhm_cbcr)) - return dev_err_probe(wcss->dev, PTR_ERR(wcss->qdsp6ss_abhm_cbcr), - "failed to get abhm cbcr clk\n"); - - wcss->qdsp6ss_axim_cbcr =3D devm_clk_get(wcss->dev, "lcc_axim_cbc"); - if (IS_ERR(wcss->qdsp6ss_axim_cbcr)) - return dev_err_probe(wcss->dev, PTR_ERR(wcss->qdsp6ss_axim_cbcr), - "failed to get axim cbcr clk\n"); - wcss->lcc_bcr_sleep =3D devm_clk_get(wcss->dev, "lcc_bcr_sleep"); if (IS_ERR(wcss->lcc_bcr_sleep)) return dev_err_probe(wcss->dev, PTR_ERR(wcss->lcc_bcr_sleep), "failed to get bcr cbcr clk\n"); =20 + ret =3D devm_clk_bulk_get(wcss->dev, wcss->num_clks, wcss->clks); + if (ret < 0) { + return dev_err_probe(wcss->dev, ret, + "failed to bulk get q6 clocks\n"); + } + return 0; } =20 --=20 2.45.1