From nobody Sun Feb 8 00:11:34 2026 Received: from mail-dl1-f41.google.com (mail-dl1-f41.google.com [74.125.82.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C3512877DA for ; Fri, 9 Jan 2026 04:08:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.82.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767931709; cv=none; b=aUzcGc1D02GiIgcSL70mVTwbZE8cHkuXIDwkh76AXO2k6zKtmapY5u9BXSzAtZ/XmEawywAEQEmsQOOvPFVo+aAVgS7X+o8Asa0vr0FhKRZz2Q3h1O+sw6GGnctfyF2e04kTKUmtPTIKcJATZK/F8b6+JjV9J6bbAtyf/Ge0kOw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767931709; c=relaxed/simple; bh=2mcRdk8NIW4UsXr59JY8Y3kTFZlEmbKvPrEyHwut2sM=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=f6V9k/2A62Xb2S0mbTYjWHoOWT4ZF/QJae6JMru2EiiiOZ8n++AQDGFT7f9sM29sv9nGDOnDOMJGbYojkffvSa548LyxQykxb9BYTTI2C4kbLvD0x1rp4Weallv42pHid8igJBPbotc4qA3/kC2Dx2laFhuDz3rxl7A5Swu2ykU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=CQs0BSM0; arc=none smtp.client-ip=74.125.82.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="CQs0BSM0" Received: by mail-dl1-f41.google.com with SMTP id a92af1059eb24-121b251438eso1602433c88.0 for ; Thu, 08 Jan 2026 20:08:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1767931707; x=1768536507; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=EDDoKbdnv2trjkmUU76X6syGqHliuOylCy3tou2sxDA=; b=CQs0BSM0x5ruIDzfr10tqUzYXPrloRdEoczmHeusM//rh4RchUVwfQkxmK6BU1I1C3 ZuRmvx3AR+KmNsgbu1UqlP1+GFH6ehSOBq4TOV0/5DWuejxwzvfma3Pazy/M4qi+qQKa Psl0dG/0bhsiZePXCV26haeI2mgMpjq7is9ApPGLRKD+EG0qkJ6U/VN/O0P2rb9YL7ld aqUWqfLgDIHsvBn25BXYHT8qS+GjgGoSMTEH2NzrPDeueW9YfMAGfRIC8ddnMuWpvhKI QSHX4x+Cj5PNiFl75HCZjGJv46iGP0UAqdxvV1bbTtqlbDccF9xgpJS6Juv8i648towK 6gyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767931707; x=1768536507; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=EDDoKbdnv2trjkmUU76X6syGqHliuOylCy3tou2sxDA=; b=bz63WYkfRF739kFe1tdOqfMr5nvS36aBYpU2Di5YFJ1caq1GaOfqy1BxUNVlkACtNc eqhjbG24rpaoi+kO0crvWJRG71CTMY3TF6JlBi5luBpve02RCmRIJW96jsHOArYNtSWF EFv0nIeKDUKZvnrx1S43mX7UbTBQ46AOLTA5Ac9+1KUdR5lJOvX58TmNFh4+YhHSqyFR RZLiaf090cXMs58t1fwIMmcedCiWKdCADp04mAUwGNTdOij0ybpJmFlwApxgAUZqeqUL pUG+Fz6a44vj2SeaDc4h0YJZFB1NVY0POmRySjhxjnhFrem4gkdb0/Di081bZIDJl6ej ut1g== X-Forwarded-Encrypted: i=1; AJvYcCUFpRD3Lh3lkIAQsnfjEIPFneVYzzYTDW7m2OZGD1jnK/Mi8oJCwwz1dKVkCO9EUHcbFrBqxVdb1HjLnOw=@vger.kernel.org X-Gm-Message-State: AOJu0YxRkwLAunHVHGktl8I0GnK0Uwg52Iz8XEw3EszzEvTVGak1ARhr ornovQPK3UVoHKf175i2V/84+48zhTs7fsiaV86DmTv8MBeQMptaFK5K X-Gm-Gg: AY/fxX57jTwOvkSUJeFLh5EtV3q/gwSY/mTc1mGAomJDEsgZSV0DclMXp98lufic70v JlS7vgAF7FiMNDS0q7Fl3CP6HUrdPZ5JyzWpQaYtlV9oszAMG40HTAGZcFdJ/X0xHPHWd3irAVQ SbAvJHeY0doGlz30zTfYsnNy9sxtq3bw3WfaVcuEOcjzdtAnwGJ2iuQFkQ/vywxnep186d+hEMh Ujo/SLrYwPAG6XzTKJLAXUCEftHGjP0Cg9DS5JeK++FFrIXKtFpX1NA1wMHgDNRah/A/dyRWdhv TZkuVeD6DC8ki6pcVyc7bsA0Ko9ARpz6ltMcWFR9iTkqQd7SCIWnvKsWmv9B+Curdj37Z/eAS6q fbOofHPlbJ57iiv5aVb7adku9s1wF+zeYU/UrqJksKUsARhXxFDDP0JFPZ8aa/aERyA04Xc/9LO qe+c5l0vofnQ== X-Google-Smtp-Source: AGHT+IHYEyj9/7o+tBP0yDD4Xk/5DkC3757Xe2hVibZ6VY5BlbkB0VR0LKgl6GAvoD4FVDJZvGGtvQ== X-Received: by 2002:a05:7022:3d04:b0:119:e569:f86a with SMTP id a92af1059eb24-121f85f242fmr7240325c88.7.1767931707386; Thu, 08 Jan 2026 20:08:27 -0800 (PST) Received: from localhost ([2001:19f0:ac00:4eb8:5400:5ff:fe30:7df3]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-121f248c239sm12869881c88.9.2026.01.08.20.08.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 20:08:26 -0800 (PST) From: Inochi Amaoto To: Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Chen Wang , Inochi Amaoto Cc: Han Gao , linux-pci@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, Yixun Lan , Longbin Li , Han Gao Subject: [PATCH] PCI/sophgo: Avoid L0s and L1 on Sophgo 2044 PCIe Root Ports Date: Fri, 9 Jan 2026 12:07:53 +0800 Message-ID: <20260109040756.731169-1-inochiama@gmail.com> X-Mailer: git-send-email 2.52.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree platforms") force enable ASPM on all device tree platform, the SG2044 root port breaks as it advertises L0s and L1 capabilities without supporting it. Mask the L0s and L1 Support advertised in Link Capabilities in the LINKCAP register SG2044 Root Ports, so the framework won't try to enable those states. Fixes: 3309df45e6b5 ("riscv: dts: sophgo: sg2044: add PCIe device support f= or SG2044") Signed-off-by: Inochi Amaoto Tested-by: Han Gao --- Change from original patch: 1. use driver to mask the ASPM advertisement Separate from the folloing patch - https://lore.kernel.org/all/20251225100530.1301625-1-inochiama@gmail.com --- drivers/pci/controller/dwc/pcie-sophgo.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-sophgo.c b/drivers/pci/control= ler/dwc/pcie-sophgo.c index ad4baaa34ffa..044088898819 100644 --- a/drivers/pci/controller/dwc/pcie-sophgo.c +++ b/drivers/pci/controller/dwc/pcie-sophgo.c @@ -161,6 +161,22 @@ static void sophgo_pcie_msi_enable(struct dw_pcie_rp *= pp) raw_spin_unlock_irqrestore(&pp->lock, flags); } +static void sophgo_pcie_disable_l0s_l1(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + u32 offset, val; + + offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + + dw_pcie_dbi_ro_wr_en(pci); + + val =3D dw_pcie_readl_dbi(pci, PCI_EXP_LNKCAP + offset); + val &=3D ~(PCI_EXP_LNKCAP_ASPM_L0S | PCI_EXP_LNKCAP_ASPM_L1); + dw_pcie_writel_dbi(pci, PCI_EXP_LNKCAP + offset, val); + + dw_pcie_dbi_ro_wr_dis(pci); +} + static int sophgo_pcie_host_init(struct dw_pcie_rp *pp) { int irq; @@ -171,6 +187,8 @@ static int sophgo_pcie_host_init(struct dw_pcie_rp *pp) irq_set_chained_handler_and_data(irq, sophgo_pcie_intx_handler, pp); + sophgo_pcie_disable_l0s_l1(pp); + sophgo_pcie_msi_enable(pp); return 0; -- 2.52.0