From nobody Sat Feb 7 08:44:22 2026 Received: from mail-pf1-f178.google.com (mail-pf1-f178.google.com [209.85.210.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19B0D1AF4D5 for ; Fri, 9 Jan 2026 02:53:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767927206; cv=none; b=V76PpWfH4bKNwThMtnAULj+Bpq+ECuv5C4lFHqeoXgrlE2ATKl6xmQkr/TJBZWVXlFNti8SOx/wc/r02dT4Of8bjsFxqZeWQprlxRQh95mGf+5n4r+BeazVBuxp1w+5ozvNGBAmEJIkbb0lGauOzvRifLWNDfd82k45pHTRleJY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767927206; c=relaxed/simple; bh=jlDI4QhjXX0sm+AzlIRpnFAmVKzlWGzF2ws15pSU3dA=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=O+t1QiEY6ijAu8xa+SOB/DiOyTLutMOAH2nPKvEvl5T6OPNYjRrnyiASObNPwM8TtU02/7L7QGtQksvlFJqPqy9K2b0FDtSQRVsZw3V41LfF1Q/W6oRGqD64lEYb9S12UFMvmaBqzuuNfaQcoBw+uZw63y5pncieZS1W9AygMnw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=bytefly.space; spf=pass smtp.mailfrom=bytefly.space; dkim=pass (2048-bit key) header.d=bytefly-space.20230601.gappssmtp.com header.i=@bytefly-space.20230601.gappssmtp.com header.b=jvoAaAAt; arc=none smtp.client-ip=209.85.210.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=bytefly.space Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bytefly.space Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bytefly-space.20230601.gappssmtp.com header.i=@bytefly-space.20230601.gappssmtp.com header.b="jvoAaAAt" Received: by mail-pf1-f178.google.com with SMTP id d2e1a72fcca58-81df6a302b1so395588b3a.2 for ; Thu, 08 Jan 2026 18:53:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytefly-space.20230601.gappssmtp.com; s=20230601; t=1767927204; x=1768532004; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=uUXH7ztgyQ+0f072AQRkPa8ArAP5onIH7wP+MjdfZtU=; b=jvoAaAAt1xXUeol5vazK4wXa1DorGiUoHumw2S3f3yjQkzF2IAzn+HQ7+NAKtYBpVW QR0ySO8SQV+9MgRUGy5o8xXAvwGgSRGk/ehtS1wsgFiKBZ10hVLcO3OI60Vh50fGYU7j inMoTqhJUqcjPPullTK0veJ93P7l6BpYpYSgFwjx7/QJRInmemBSMD5P8Gn9IFzJg8oS Sm16ZjQdgSopo/2u9WMQjHOshP0I36U9Y66Fls9Ef0hfPR9hesHh5HDo2XWuLn30kfCH /hKXWcjQzLZ1gCt1vZLEhczKRApYoN9jbCbKHqLjtRkQ3b/810+rxGnTKKpuYxkrAop6 jdLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767927204; x=1768532004; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=uUXH7ztgyQ+0f072AQRkPa8ArAP5onIH7wP+MjdfZtU=; b=FO2bhPcK9wVvH48klsTKCMjEpUWNOxfSQ+WH/L/4GMg7gK5Y3ep7OuXzA5wEVU+JH+ 7S9CzmlntsTOG5fbRHPpf9EU5OhOsreos+n/3uXNoKSkesAAvELpELS4aZpLx0n6EXTX +OxCrstFF06SeMO19SgBzgmvWOjnfjs3c3pwyY6OY/kiEK0QxWGI7ghtmbQ1dDbZax8v VvRYICOMoNMP9+DJnylwT97XCN0i2HoqrG7J9Z/CVzrhU3UYveA3BIYmBX8PT66/ldQl 6431oO22xQe4aHmptug1bYa+WfyHMFTcf1mulJIZj4QAUxWPtSqGZCeYNi4G26XaYGjx YnEA== X-Forwarded-Encrypted: i=1; AJvYcCUsIJ5RDLr0IOhX6zK74QUg7Woh3MapGYRUoK/BMKNKcBKZSvKuc+4v0hCJDPXPgwYYOASniyHCIcDOZ40=@vger.kernel.org X-Gm-Message-State: AOJu0YyXAy97Xti6U6R54bUWmVFV+11H7s1VD7FwySJFXHcasN/9zgHZ 1/K5/W1mUMC87O6aKLe9YCKnZxlubXmbcnWuN1l1Txpnd+htfzypn81tCMI0yTsDohI= X-Gm-Gg: AY/fxX5o7X/xuRZRVSnNtpnVoRJFdrCreqjhZQximezcf0QK+PPGWpdND9vczXpkH2f Yrxm3HkjtQXBtUrwROWuVk0cAKZ0hAB51J0ptJ1pr6+17qbYivdWTyauVkRIXi3x/pHmmobXMXQ W7swGB+RV0s3AoZXCiL2Zec29pfQ5wVY7j6CHaxnpidTtPq2IKru/yZ2OnVaizR1tijTfMDRZU1 tL6KLg+iv2l8RduDpzDwpmZdEfdJ/vyacT/P5keWX8f1tiMYPqCGLwBPMHY/jxUVMeegdXyBchk WSnYun7+5R2Owou0zPsMfNbf6kTSgNVLVB2ClCidHInAVCO8KFmX9Dy9QCWbpnosqhq5+be2L9r rqeioCCVJdXakWlmTv7PfAtxtB6fjPErgQyyneIw3oh5vgWiTAgrLQXkr78cq6eCPYrW8sSI+bi rIJw== X-Google-Smtp-Source: AGHT+IH0HUr0MdRXguipbzsaEA/OlWzBSmlBph10zKzEYjFwr3gALLho1tjkPB9DgVkeAspeCEoTkg== X-Received: by 2002:a05:6a00:1c9e:b0:7fb:eb9c:66a7 with SMTP id d2e1a72fcca58-81b7f3f2282mr6338630b3a.36.1767927204353; Thu, 08 Jan 2026 18:53:24 -0800 (PST) Received: from xpc ([2400:8902:e002:dec2:6246:24bc:b792:73cd]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c4cc9e7e824sm9069051a12.30.2026.01.08.18.53.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 18:53:23 -0800 (PST) From: Lisa Robinson To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Huacai Chen Cc: Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , WANG Xuerui , dapeng1.mi@linux.intel.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Lisa Robinson Subject: [PATCH v3] LoongArch: Fix PMU counter allocation for mixed-type event groups Date: Fri, 9 Jan 2026 10:53:12 +0800 Message-ID: <20260109025312.226700-1-lisa@bytefly.space> X-Mailer: git-send-email 2.52.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When validating a perf event group, validate_group() unconditionally attempts to allocate hardware PMU counters for the leader, sibling events and the new event being added. This is incorrect for mixed-type groups. If a PERF_TYPE_SOFTWARE event is part of the group, the current code still tries to allocate a hardware PMU counter for it, which can wrongly consume hardware PMU resources and cause spurious allocation failures. Fix this by only allocating PMU counters for hardware events during group validation, and skipping software events. A trimmed down reproducer is as simple as this: #include #include #include #include #include #include int main (int argc, char *argv[]) { struct perf_event_attr attr =3D { 0 }; int fds[5]; attr.disabled =3D 1; attr.exclude_kernel =3D 1; attr.exclude_hv =3D 1; attr.read_format =3D PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_TOTAL_TIME_RUNNING | PERF_FORMAT_ID | PERF_FORMAT_GROUP; attr.size =3D sizeof (attr); attr.type =3D PERF_TYPE_SOFTWARE; attr.config =3D PERF_COUNT_SW_DUMMY; fds[0] =3D syscall (SYS_perf_event_open, &attr, 0, -1, -1, 0); assert (fds[0] >=3D 0); attr.type =3D PERF_TYPE_HARDWARE; attr.config =3D PERF_COUNT_HW_CPU_CYCLES; fds[1] =3D syscall (SYS_perf_event_open, &attr, 0, -1, fds[0], 0); assert (fds[1] >=3D 0); attr.type =3D PERF_TYPE_HARDWARE; attr.config =3D PERF_COUNT_HW_INSTRUCTIONS; fds[2] =3D syscall (SYS_perf_event_open, &attr, 0, -1, fds[0], 0); assert (fds[2] >=3D 0); attr.type =3D PERF_TYPE_HARDWARE; attr.config =3D PERF_COUNT_HW_BRANCH_MISSES; fds[3] =3D syscall (SYS_perf_event_open, &attr, 0, -1, fds[0], 0); assert (fds[3] >=3D 0); attr.type =3D PERF_TYPE_HARDWARE; attr.config =3D PERF_COUNT_HW_CACHE_REFERENCES; fds[4] =3D syscall (SYS_perf_event_open, &attr, 0, -1, fds[0], 0); assert (fds[4] >=3D 0); printf ("PASSED\n"); return 0; } Fixes: b37042b2bb7c ("LoongArch: Add perf events support") Signed-off-by: Lisa Robinson --- Changes in v3: - Fix typo. Changes in v2: - Factor out duplicated perf event type checks into an inline helper. --- arch/loongarch/kernel/perf_event.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/arch/loongarch/kernel/perf_event.c b/arch/loongarch/kernel/per= f_event.c index 9d257c8519c9..e34a6fb33e11 100644 --- a/arch/loongarch/kernel/perf_event.c +++ b/arch/loongarch/kernel/perf_event.c @@ -626,6 +626,18 @@ static const struct loongarch_perf_event *loongarch_pm= u_map_cache_event(u64 conf return pev; } =20 +static inline bool loongarch_pmu_event_requires_counter(const struct perf_= event *event) +{ + switch (event->attr.type) { + case PERF_TYPE_HARDWARE: + case PERF_TYPE_HW_CACHE: + case PERF_TYPE_RAW: + return true; + default: + return false; + } +} + static int validate_group(struct perf_event *event) { struct cpu_hw_events fake_cpuc; @@ -633,15 +645,18 @@ static int validate_group(struct perf_event *event) =20 memset(&fake_cpuc, 0, sizeof(fake_cpuc)); =20 - if (loongarch_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0) + if (loongarch_pmu_event_requires_counter(leader) && + loongarch_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0) return -EINVAL; =20 for_each_sibling_event(sibling, leader) { - if (loongarch_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0) + if (loongarch_pmu_event_requires_counter(sibling) && + loongarch_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0) return -EINVAL; } =20 - if (loongarch_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0) + if (loongarch_pmu_event_requires_counter(event) && + loongarch_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0) return -EINVAL; =20 return 0; --=20 2.52.0