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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b1707d76aasm9459111eec.33.2026.01.08.18.12.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 18:12:11 -0800 (PST) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, mike.leach@linaro.org, suzuki.poulose@arm.com, james.clark@arm.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org Subject: [PATCH v10 4/7] qcom-tgu: Add TGU decode support Date: Thu, 8 Jan 2026 18:11:38 -0800 Message-Id: <20260109021141.3778421-5-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260109021141.3778421-1-songwei.chai@oss.qualcomm.com> References: <20260109021141.3778421-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=M45A6iws c=1 sm=1 tr=0 ts=696063fd cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=17ZuibbC0m_VACr_8A0A:9 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-ORIG-GUID: arQMilZA6HTASqPk8YHFoU3yTr2P-Xih X-Proofpoint-GUID: arQMilZA6HTASqPk8YHFoU3yTr2P-Xih X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA5MDAxMiBTYWx0ZWRfX3j24oJosIYWP Sl9lB1PheKQC6acz6iT0PXGcQhRsMGYmAd6pBJRNCxtuYTVSj5S+0JdE2BYfUFSvpaireNUBNPb jNjGGxX5QVK1dSh21MwOJCzJtG/xtkRHbwRpX3X7T3xCrT+h/hNiBG+kSA/OmqYary9Fse9iZi/ yysXzEy6N40uwSsJI0+Z+GTYOfeq84SRYicjJlBOEVrmcx743cxqyw0/5Hb7AVkQiG/FC48DL+p jWWrl9QdzqrbpSCRUKQ9DHUJjM+il/HkGEqvY33IpQfzZQZdZyCT0IMQBmR8w1/WAEFGZo2t0IL Klsigrni/c5rvUImbcsn8+3Y2RFUqnLJXIcNbZdmVIUxavbMXkYZg/BY7uwpUJGMArv0ZfvOdfl sYFfLXpJvmiJGO567U9A0fWZipojJspsq0KJa2qlhzucWfaermcOW8eG1PI43zTNgaOitdOLyJ3 c4Kv40m8Wwh82KVYuLg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-09_01,2026-01-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 suspectscore=0 clxscore=1015 spamscore=0 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601090012 Content-Type: text/plain; charset="utf-8" Decoding is when all the potential pieces for creating a trigger are brought together for a given step. Example - there may be a counter keeping track of some occurrences and a priority-group that is being used to detect a pattern on the sense inputs. These 2 inputs to condition_decode must be programmed, for a given step, to establish the condition for the trigger, or movement to another steps. Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 7 + drivers/hwtracing/qcom/tgu.c | 162 ++++++++++++++++-- drivers/hwtracing/qcom/tgu.h | 27 +++ 3 files changed, 177 insertions(+), 19 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documen= tation/ABI/testing/sysfs-bus-amba-devices-tgu index ec630e6ff2ee..4efa36a11d8e 100644 --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -14,3 +14,10 @@ KernelVersion 6.19 Contact: Jinlong Mao , Songwei Chai Description: (RW) Set/Get the sensed signal with specific step and priority for TGU. + +What: /sys/bus/amba/devices//step[0:7]_condition_decode/reg[0:3] +Date: January 2026 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the decode mode with specific step for TGU. diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c index f8870766d624..39301d35ee9d 100644 --- a/drivers/hwtracing/qcom/tgu.c +++ b/drivers/hwtracing/qcom/tgu.c @@ -18,8 +18,36 @@ static int calculate_array_location(struct tgu_drvdata *= drvdata, int step_index, int operation_index, int reg_index) { - return operation_index * (drvdata->max_step) * (drvdata->max_reg) + - step_index * (drvdata->max_reg) + reg_index; + int ret =3D -EINVAL; + + switch (operation_index) { + case TGU_PRIORITY0: + case TGU_PRIORITY1: + case TGU_PRIORITY2: + case TGU_PRIORITY3: + ret =3D operation_index * (drvdata->max_step) * + (drvdata->max_reg) + + step_index * (drvdata->max_reg) + reg_index; + break; + case TGU_CONDITION_DECODE: + ret =3D step_index * (drvdata->max_condition_decode) + + reg_index; + break; + default: + break; + } + return ret; +} + +static int check_array_location(struct tgu_drvdata *drvdata, int step, + int ops, int reg) +{ + int result =3D calculate_array_location(drvdata, step, ops, reg); + + if (result =3D=3D -EINVAL) + dev_err(drvdata->dev, "%s - Fail\n", __func__); + + return result; } =20 static ssize_t tgu_dataset_show(struct device *dev, @@ -30,12 +58,26 @@ static ssize_t tgu_dataset_show(struct device *dev, container_of(attr, struct tgu_attribute, attr); int index; =20 - index =3D calculate_array_location(drvdata, tgu_attr->step_index, - tgu_attr->operation_index, - tgu_attr->reg_num); - - return sysfs_emit(buf, "0x%x\n", - drvdata->value_table->priority[index]); + index =3D check_array_location(drvdata, tgu_attr->step_index, + tgu_attr->operation_index, tgu_attr->reg_num); + + if (index =3D=3D -EINVAL) + return index; + + switch (tgu_attr->operation_index) { + case TGU_PRIORITY0: + case TGU_PRIORITY1: + case TGU_PRIORITY2: + case TGU_PRIORITY3: + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->priority[index]); + case TGU_CONDITION_DECODE: + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->condition_decode[index]); + default: + break; + } + return -EINVAL; } =20 static ssize_t tgu_dataset_store(struct device *dev, @@ -47,18 +89,37 @@ static ssize_t tgu_dataset_store(struct device *dev, container_of(attr, struct tgu_attribute, attr); unsigned long val; int index; + int ret; =20 ret =3D kstrtoul(buf, 0, &val); if (ret) return ret; =20 guard(spinlock)(&tgu_drvdata->lock); - index =3D calculate_array_location(tgu_drvdata, tgu_attr->step_index, + index =3D check_array_location(tgu_drvdata, tgu_attr->step_index, tgu_attr->operation_index, tgu_attr->reg_num); =20 - tgu_drvdata->value_table->priority[index] =3D val; - return size; + if (index =3D=3D -EINVAL) + return -EINVAL; + + switch (tgu_attr->operation_index) { + case TGU_PRIORITY0: + case TGU_PRIORITY1: + case TGU_PRIORITY2: + case TGU_PRIORITY3: + tgu_drvdata->value_table->priority[index] =3D val; + ret =3D size; + break; + case TGU_CONDITION_DECODE: + tgu_drvdata->value_table->condition_decode[index] =3D val; + ret =3D size; + break; + default: + ret =3D -EINVAL; + break; + } + return ret; } =20 static umode_t tgu_node_visible(struct kobject *kobject, @@ -74,13 +135,27 @@ static umode_t tgu_node_visible(struct kobject *kobjec= t, int ret =3D SYSFS_GROUP_INVISIBLE; =20 if (tgu_attr->step_index < drvdata->max_step) { - ret =3D (tgu_attr->reg_num < drvdata->max_reg) ? - attr->mode : 0; + switch (tgu_attr->operation_index) { + case TGU_PRIORITY0: + case TGU_PRIORITY1: + case TGU_PRIORITY2: + case TGU_PRIORITY3: + ret =3D (tgu_attr->reg_num < drvdata->max_reg) ? + attr->mode : 0; + break; + case TGU_CONDITION_DECODE: + ret =3D (tgu_attr->reg_num < + drvdata->max_condition_decode) ? + attr->mode : 0; + break; + default: + break; + } } return ret; } =20 -static void tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) +static ssize_t tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) { int i, j, k, index; =20 @@ -88,8 +163,10 @@ static void tgu_write_all_hw_regs(struct tgu_drvdata *d= rvdata) for (i =3D 0; i < drvdata->max_step; i++) { for (j =3D 0; j < MAX_PRIORITY; j++) { for (k =3D 0; k < drvdata->max_reg; k++) { - index =3D calculate_array_location( + index =3D check_array_location( drvdata, i, j, k); + if (index =3D=3D -EINVAL) + goto exit; =20 writel(drvdata->value_table->priority[index], drvdata->base + @@ -97,9 +174,23 @@ static void tgu_write_all_hw_regs(struct tgu_drvdata *d= rvdata) } } } + + for (i =3D 0; i < drvdata->max_step; i++) { + for (j =3D 0; j < drvdata->max_condition_decode; j++) { + index =3D check_array_location(drvdata, i, + TGU_CONDITION_DECODE, j); + if (index =3D=3D -EINVAL) + goto exit; + + writel(drvdata->value_table->condition_decode[index], + drvdata->base + CONDITION_DECODE_STEP(i, j)); + } + } /* Enable TGU to program the triggers */ writel(1, drvdata->base + TGU_CONTROL); +exit: TGU_LOCK(drvdata->base); + return index >=3D 0 ? 0 : -EINVAL; } =20 static void tgu_set_reg_number(struct tgu_drvdata *drvdata) @@ -128,18 +219,32 @@ static void tgu_set_steps(struct tgu_drvdata *drvdata) drvdata->max_step =3D TGU_DEVID_STEPS(devid); } =20 +static void tgu_set_conditions(struct tgu_drvdata *drvdata) +{ + u32 devid; + + devid =3D readl(drvdata->base + TGU_DEVID); + drvdata->max_condition_decode =3D TGU_DEVID_CONDITIONS(devid); +} + static int tgu_enable(struct device *dev) { struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); + int ret =3D 0; =20 guard(spinlock)(&drvdata->lock); if (drvdata->enable) return -EBUSY; =20 - tgu_write_all_hw_regs(drvdata); + ret =3D tgu_write_all_hw_regs(drvdata); + + if (ret =3D=3D -EINVAL) + goto exit; + drvdata->enable =3D true; =20 - return 0; +exit: + return ret; } =20 static void tgu_disable(struct device *dev) @@ -243,6 +348,14 @@ static const struct attribute_group *tgu_attr_groups[]= =3D { PRIORITY_ATTRIBUTE_GROUP_INIT(7, 1), PRIORITY_ATTRIBUTE_GROUP_INIT(7, 2), PRIORITY_ATTRIBUTE_GROUP_INIT(7, 3), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(0), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(1), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(2), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(3), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(4), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(5), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(6), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(7), NULL, }; =20 @@ -250,8 +363,8 @@ static int tgu_probe(struct amba_device *adev, const st= ruct amba_id *id) { struct device *dev =3D &adev->dev; struct tgu_drvdata *drvdata; - size_t priority_size; - unsigned int *priority; + size_t priority_size, condition_size; + unsigned int *priority, *condition; int ret; =20 drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); @@ -269,6 +382,7 @@ static int tgu_probe(struct amba_device *adev, const st= ruct amba_id *id) =20 tgu_set_reg_number(drvdata); tgu_set_steps(drvdata); + tgu_set_conditions(drvdata); =20 ret =3D sysfs_create_groups(&dev->kobj, tgu_attr_groups); if (ret) { @@ -292,6 +406,16 @@ static int tgu_probe(struct amba_device *adev, const s= truct amba_id *id) =20 drvdata->value_table->priority =3D priority; =20 + condition_size =3D drvdata->max_condition_decode * + drvdata->max_step * + sizeof(*(drvdata->value_table->condition_decode)); + + condition =3D devm_kzalloc(dev, condition_size, GFP_KERNEL); + + if (!condition) + return -ENOMEM; + + drvdata->value_table->condition_decode =3D condition; =20 drvdata->enable =3D false; =20 diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h index f54cea01e427..0d058663aca5 100644 --- a/drivers/hwtracing/qcom/tgu.h +++ b/drivers/hwtracing/qcom/tgu.h @@ -15,6 +15,7 @@ #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) #define TGU_DEVID_SENSE_INPUT(devid_val) ((int) BMVAL(devid_val, 10, 17)) #define TGU_DEVID_STEPS(devid_val) ((int)BMVAL(devid_val, 3, 6)) +#define TGU_DEVID_CONDITIONS(devid_val) ((int)BMVAL(devid_val, 0, 2)) #define NUMBER_BITS_EACH_SIGNAL 4 #define LENGTH_REGISTER 32 =20 @@ -48,6 +49,7 @@ */ #define STEP_OFFSET 0x1D8 #define PRIORITY_START_OFFSET 0x0074 +#define CONDITION_DECODE_OFFSET 0x0050 #define PRIORITY_OFFSET 0x60 #define REG_OFFSET 0x4 =20 @@ -56,6 +58,9 @@ (PRIORITY_START_OFFSET + PRIORITY_OFFSET * priority +\ REG_OFFSET * reg + STEP_OFFSET * step) =20 +#define CONDITION_DECODE_STEP(step, decode) \ + (CONDITION_DECODE_OFFSET + REG_OFFSET * decode + STEP_OFFSET * step) + #define tgu_dataset_rw(name, step_index, type, reg_num) \ (&((struct tgu_attribute[]){ { \ __ATTR(name, 0644, tgu_dataset_show, tgu_dataset_store), \ @@ -68,6 +73,9 @@ tgu_dataset_rw(reg##reg_num, step_index, TGU_PRIORITY##priority, \ reg_num) =20 +#define STEP_DECODE(step_index, reg_num) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_DECODE, reg_num) + #define STEP_PRIORITY_LIST(step_index, priority) \ {STEP_PRIORITY(step_index, 0, priority), \ STEP_PRIORITY(step_index, 1, priority), \ @@ -90,6 +98,14 @@ NULL \ } =20 +#define STEP_DECODE_LIST(n) \ + {STEP_DECODE(n, 0), \ + STEP_DECODE(n, 1), \ + STEP_DECODE(n, 2), \ + STEP_DECODE(n, 3), \ + NULL \ + } + #define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\ (&(const struct attribute_group){\ .attrs =3D (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\ @@ -97,11 +113,19 @@ .name =3D "step" #step "_priority" #priority \ }) =20 +#define CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(step)\ + (&(const struct attribute_group){\ + .attrs =3D (struct attribute*[])STEP_DECODE_LIST(step),\ + .is_visible =3D tgu_node_visible,\ + .name =3D "step" #step "_condition_decode" \ + }) + enum operation_index { TGU_PRIORITY0, TGU_PRIORITY1, TGU_PRIORITY2, TGU_PRIORITY3, + TGU_CONDITION_DECODE, }; =20 /* Maximum priority that TGU supports */ @@ -116,6 +140,7 @@ struct tgu_attribute { =20 struct value_table { unsigned int *priority; + unsigned int *condition_decode; }; =20 static inline void TGU_LOCK(void __iomem *addr) @@ -145,6 +170,7 @@ static inline void TGU_UNLOCK(void __iomem *addr) * @value_table: Store given value based on relevant parameters. * @max_reg: Maximum number of registers * @max_step: Maximum step size + * @max_condition_decode: Maximum number of condition_decode * * This structure defines the data associated with a TGU device, * including its base address, device pointers, clock, spinlock for @@ -159,6 +185,7 @@ struct tgu_drvdata { struct value_table *value_table; int max_reg; int max_step; + int max_condition_decode; }; =20 #endif --=20 2.34.1