From nobody Mon Feb 9 17:58:25 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8820B26F29C for ; Fri, 9 Jan 2026 02:12:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767924736; cv=none; b=WftB1T6JSXn0cPlISUZcaEO7KHYT+UxMkGXbuLLdK6RmJnMn6RPZXaXeIbcevUDOQ79sGobbltXZdwmzhmppYBLWjhcsB+n47oelTjP6XGRzoNepL/Oxg5t6ECe+8X9SREJK/uTtxssKD+NAhf1BVmXFFv7fvFtFBaH82Jwu4QE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767924736; c=relaxed/simple; bh=EEkNfbmQBN+8dnYOxY65nW4ZVEiCodIqcZ8MJeoNU6Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=CbajfimQ+ZxNYUzSAn4lQetyoYs+eGYQOXJfxNI2Q2g/krY2U/xqj7XD6lojNxCa07o5MO6eHQfOK2SIRtvaDITiBhTHDywKhT3zCw2pZNtxgZFJzQJsfynWbdGgFwrrP3nrrCnPtOmw8Xsw+xZrEJaiQZT8RgGmLfV+YReeN/E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=D1n92uk4; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=KzsvfI3J; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="D1n92uk4"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="KzsvfI3J" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 608Hk2FD1701969 for ; Fri, 9 Jan 2026 02:12:11 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=l8ZUSHgXPwx I60cMjU2VQsRQlj6MWG27O1WOHBdsivk=; b=D1n92uk4Xuz6NJo5ZjVbZwac/CL NDQZhMPTufFo+Sasuv4EKbMKGui54p5pPcuFDdZWuwW6dXdpjAydlrdoPYphU5FA KiCjrkzuJoRY+6558EG/XuSm5wdzWdTdpywYzsCEtqXMsuNKqvYbwSYlc1gyEiut Dk1ii7llcboGL1Lcj3RsODXD7BLv9WIeOSs003/HUlK4+56p9yqQD9FbVfMNJWL9 zPXK3ZDrgKmG+862xglhG7EPVIjwKSQfpLbONKuhghBrRufefCK5fDKCtOLEhPYX S3QpDZUbQVmIlAIf0Y3rzjfRTeUQuHF+RJZhxGH0wxg7wYgy6YxNskVNfRg== Received: from mail-dy1-f199.google.com (mail-dy1-f199.google.com [74.125.82.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bjfda9n32-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 09 Jan 2026 02:12:11 +0000 (GMT) Received: by mail-dy1-f199.google.com with SMTP id 5a478bee46e88-2b0531e07e3so3222658eec.1 for ; Thu, 08 Jan 2026 18:12:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1767924731; x=1768529531; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=l8ZUSHgXPwxI60cMjU2VQsRQlj6MWG27O1WOHBdsivk=; b=KzsvfI3JBVRMIQcDZv5US+eN3IgaXIP2CDyLmxPpWLbD+gC/bp4TJdQCAJugaVA9VH n4s4/8lkPjCYX6zQrVrKVtUx9z2GQXOG3xOyEgVkyl3gAGERpm/mVf5OX4rLu8B6XWfq qFGFLuK40gqfBYSfGqwn5S8fCBvW+X9rfSBOfR+Bc04/200fpbeIthDboBypoBjPOt9h 33BmNREmDCeMMz/89CbUWT6Yy9WVvPDiAivewuX5Sss+XEAHbnEUtJSxgGspClEX6f7u cqoP6fEp1kJbg3XDUFs8n2aMT/ld1kISWpyBgGG7WxHj8oOGL9QQiGkKrLD4QSfl03f7 XFsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767924731; x=1768529531; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=l8ZUSHgXPwxI60cMjU2VQsRQlj6MWG27O1WOHBdsivk=; b=q16EkLTNRLs2k7Fx4T5S35DuNkH5FXHS7fz9Gw8cMUazVPh44oyk1wdLUz3hsKgxhv SbBV1gu74slSzEtGFE8mQvVPcNKqAvioGdvKhTg3mqPW1dGN/vSu+hTk4WeZce5bZlFd gC2vopVuPB++USTnpMGM0z894fI4ieWJ6i5RVwHJgoTDWZ8vD6psvOuVfZc53oFdffe1 WgqNVrujhzY3Deynlf5DVPA34LTstWN+CY3F8ipgbMGbEV6+qvQ+cPrN6ZN0WH3tzIwN sPBbi08aDYqP7fh+j/W5kdrWGE6geSMX6ICjS4+Z2qLDgXG35Qc4Hg+ZA6kJnz5hwBWU xupQ== X-Forwarded-Encrypted: i=1; AJvYcCXPHK7N6RtyNa7oZahuAIgSYlBekIdTBVxWvpiCEoCCbkmGs56KQCPhghKVEXVJvpcz1ASFwClhHlxUfLo=@vger.kernel.org X-Gm-Message-State: AOJu0YwVPGNJXXh0VcBxRHNJVt31c9gOE+xOlPEI5p0VjLVXctLXwr85 PMmAty8am5rUQXw1uMyJVJqcAhScUGMbSQnjIbIW4Z2B1lBk8sEB2JxfBgxu0Gq4uV57pNqqyOk s4xIvlU1MuJwvjf0P2iNuYMaAyfEsL+ClFxt8dh96XMf7rBB1k/hpFXEY1x7pVofWwAk= X-Gm-Gg: AY/fxX55LbULzO28vcNKNB5TCkmM/TNM63saIXd3sX6Zk4b9cnzLJ9wq0G3cMLhBAms v6KbrEH81bx/TcOrjnCe+vGqbtNfo9zeG3kga4plQfwGNPYFWvwJlXUnw5qKsI2RKe5W7nvbYBR pHHHzYQkqxs7JLOeVFgqqonaQqf9MM/zjR4RvWkqg/9szBujPJjsbuTIOQyi/dQL2vOvCK5MXdG 30NCJ5dOZbuq0JU9j6kV4rfkB9aaH+rusywzLiwBM6+d1H2+SzMSCh1VDKeDFrpbHWoc/ASaDVV CgTZzh30B6wtXEXdxG+hZ+NcphYwN0APWxdJ5qM7aRqHCUmg4vxDIn0mCsO+soEYWCZDQv9DUpy uROKS9iAw+EKh1bFCyKAazKXEWOlHBLvSU79o+84qb227yD/U0vdQ/Mje7YkHX6o/ X-Received: by 2002:a05:7300:fb09:b0:2a4:3593:466d with SMTP id 5a478bee46e88-2b17d226c06mr5084510eec.9.1767924730245; Thu, 08 Jan 2026 18:12:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IHvY/KIw1x5A1D0EeHpkihkYg3QpZfby76yqehvPy8YBwjD2Fqm89ZI+vwkayOWry45JN4POg== X-Received: by 2002:a05:7300:fb09:b0:2a4:3593:466d with SMTP id 5a478bee46e88-2b17d226c06mr5084502eec.9.1767924729642; Thu, 08 Jan 2026 18:12:09 -0800 (PST) Received: from hu-songchai-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b1707d76aasm9459111eec.33.2026.01.08.18.12.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 18:12:09 -0800 (PST) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, mike.leach@linaro.org, suzuki.poulose@arm.com, james.clark@arm.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org Subject: [PATCH v10 3/7] qcom-tgu: Add signal priority support Date: Thu, 8 Jan 2026 18:11:37 -0800 Message-Id: <20260109021141.3778421-4-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260109021141.3778421-1-songwei.chai@oss.qualcomm.com> References: <20260109021141.3778421-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=Ue1ciaSN c=1 sm=1 tr=0 ts=696063fb cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=aHbVEu0FunmFpxPyS6YA:9 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-ORIG-GUID: UpGLuCsCySR08evwONQ_OIu_UWNIV25w X-Proofpoint-GUID: UpGLuCsCySR08evwONQ_OIu_UWNIV25w X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA5MDAxMiBTYWx0ZWRfXw+RN/TRhjsxx WI2VYBeTur8NO3uUSHyascOuY3yNX9F/z0egy72yvI9VciCPrXH4F/39IfMx5scRkTqQoWS2lvd 9mH6i7QDs9dZI2vkJsFXqER2+hu7ufyUqjSlmj6SJvx64bz+1KW8uhrTgGpuBrXkY20zyWCJSw9 D1bMlRc8y8kPSwqF3nybW5WqrN6BiHtp38oYEXoBL8VaazXHY/JCsiiHSUl73/NK1j2TvWQaqOf p8YSinf0ecxdqS5A8N4HOsAx3fJwR5DRH5YikxhUuoVenuQxEwmRpqstw8Zi5xzsBQ6pC0MEbP+ khkM1WmlJB38Cc6VYUDeydOvvJi4dPyECxbNxO4jB1r9P9WB34SvDoGKrH+E66BW+xpRdctyXAW zvY3d6GfmHmNk2WVXxnJCeK3xr2c/1WQtTiXWWmy8J+5gL7Yrpxm5gxWvoA5m7xpN6xjwhLH9JT 8ia63q4tIkhzSEM8DiQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-09_01,2026-01-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 suspectscore=0 phishscore=0 spamscore=0 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601090012 Content-Type: text/plain; charset="utf-8" Like circuit of a Logic analyzer, in TGU, the requirement could be configured in each step and the trigger will be created once the requirements are met. Add priority functionality here to sort the signals into different priorities. The signal which is wanted could be configured in each step's priority node, the larger number means the higher priority and the signal with higher priority will be sensed more preferentially. Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 7 + drivers/hwtracing/qcom/tgu.c | 160 ++++++++++++++++++ drivers/hwtracing/qcom/tgu.h | 113 +++++++++++++ 3 files changed, 280 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documen= tation/ABI/testing/sysfs-bus-amba-devices-tgu index 56ec3f5ab5d6..ec630e6ff2ee 100644 --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -7,3 +7,10 @@ Description: Accepts only one of the 2 values - 0 or 1. 0 : disable TGU. 1 : enable TGU. + +What: /sys/bus/amba/devices//step[0:7]_priority[0:3]/reg[0:17] +Date: January 2026 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the sensed signal with specific step and priority for TGU. diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c index c5b2b384e6ae..f8870766d624 100644 --- a/drivers/hwtracing/qcom/tgu.c +++ b/drivers/hwtracing/qcom/tgu.c @@ -14,14 +14,120 @@ =20 #include "tgu.h" =20 +static int calculate_array_location(struct tgu_drvdata *drvdata, + int step_index, int operation_index, + int reg_index) +{ + return operation_index * (drvdata->max_step) * (drvdata->max_reg) + + step_index * (drvdata->max_reg) + reg_index; +} + +static ssize_t tgu_dataset_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); + struct tgu_attribute *tgu_attr =3D + container_of(attr, struct tgu_attribute, attr); + int index; + + index =3D calculate_array_location(drvdata, tgu_attr->step_index, + tgu_attr->operation_index, + tgu_attr->reg_num); + + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->priority[index]); +} + +static ssize_t tgu_dataset_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct tgu_drvdata *tgu_drvdata =3D dev_get_drvdata(dev); + struct tgu_attribute *tgu_attr =3D + container_of(attr, struct tgu_attribute, attr); + unsigned long val; + int index; + + ret =3D kstrtoul(buf, 0, &val); + if (ret) + return ret; + + guard(spinlock)(&tgu_drvdata->lock); + index =3D calculate_array_location(tgu_drvdata, tgu_attr->step_index, + tgu_attr->operation_index, + tgu_attr->reg_num); + + tgu_drvdata->value_table->priority[index] =3D val; + return size; +} + +static umode_t tgu_node_visible(struct kobject *kobject, + struct attribute *attr, + int n) +{ + struct device *dev =3D kobj_to_dev(kobject); + struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); + struct device_attribute *dev_attr =3D + container_of(attr, struct device_attribute, attr); + struct tgu_attribute *tgu_attr =3D + container_of(dev_attr, struct tgu_attribute, attr); + int ret =3D SYSFS_GROUP_INVISIBLE; + + if (tgu_attr->step_index < drvdata->max_step) { + ret =3D (tgu_attr->reg_num < drvdata->max_reg) ? + attr->mode : 0; + } + return ret; +} + static void tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) { + int i, j, k, index; + TGU_UNLOCK(drvdata->base); + for (i =3D 0; i < drvdata->max_step; i++) { + for (j =3D 0; j < MAX_PRIORITY; j++) { + for (k =3D 0; k < drvdata->max_reg; k++) { + index =3D calculate_array_location( + drvdata, i, j, k); + + writel(drvdata->value_table->priority[index], + drvdata->base + + PRIORITY_REG_STEP(i, j, k)); + } + } + } /* Enable TGU to program the triggers */ writel(1, drvdata->base + TGU_CONTROL); TGU_LOCK(drvdata->base); } =20 +static void tgu_set_reg_number(struct tgu_drvdata *drvdata) +{ + int num_sense_input; + int num_reg; + u32 devid; + + devid =3D readl(drvdata->base + TGU_DEVID); + + num_sense_input =3D TGU_DEVID_SENSE_INPUT(devid); + if (((num_sense_input * NUMBER_BITS_EACH_SIGNAL) % LENGTH_REGISTER) =3D= =3D 0) + num_reg =3D (num_sense_input * NUMBER_BITS_EACH_SIGNAL) / LENGTH_REGISTE= R; + else + num_reg =3D ((num_sense_input * NUMBER_BITS_EACH_SIGNAL) / LENGTH_REGIST= ER) + 1; + drvdata->max_reg =3D num_reg; + +} + +static void tgu_set_steps(struct tgu_drvdata *drvdata) +{ + u32 devid; + + devid =3D readl(drvdata->base + TGU_DEVID); + + drvdata->max_step =3D TGU_DEVID_STEPS(devid); +} + static int tgu_enable(struct device *dev) { struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); @@ -105,6 +211,38 @@ static const struct attribute_group tgu_common_grp =3D= { =20 static const struct attribute_group *tgu_attr_groups[] =3D { &tgu_common_grp, + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 3), NULL, }; =20 @@ -112,6 +250,8 @@ static int tgu_probe(struct amba_device *adev, const st= ruct amba_id *id) { struct device *dev =3D &adev->dev; struct tgu_drvdata *drvdata; + size_t priority_size; + unsigned int *priority; int ret; =20 drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); @@ -127,12 +267,32 @@ static int tgu_probe(struct amba_device *adev, const = struct amba_id *id) =20 spin_lock_init(&drvdata->lock); =20 + tgu_set_reg_number(drvdata); + tgu_set_steps(drvdata); + ret =3D sysfs_create_groups(&dev->kobj, tgu_attr_groups); if (ret) { dev_err(dev, "failed to create sysfs groups: %d\n", ret); return ret; } =20 + drvdata->value_table =3D + devm_kzalloc(dev, sizeof(*drvdata->value_table), GFP_KERNEL); + if (!drvdata->value_table) + return -ENOMEM; + + priority_size =3D MAX_PRIORITY * drvdata->max_reg * + drvdata->max_step * + sizeof(*(drvdata->value_table->priority)); + + priority =3D devm_kzalloc(dev, priority_size, GFP_KERNEL); + + if (!priority) + return -ENOMEM; + + drvdata->value_table->priority =3D priority; + + drvdata->enable =3D false; =20 pm_runtime_put(&adev->dev); diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h index b11cfb28261d..f54cea01e427 100644 --- a/drivers/hwtracing/qcom/tgu.h +++ b/drivers/hwtracing/qcom/tgu.h @@ -10,6 +10,113 @@ #define TGU_CONTROL 0x0000 #define TGU_LAR 0xfb0 #define TGU_UNLOCK_OFFSET 0xc5acce55 +#define TGU_DEVID 0xfc8 + +#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) +#define TGU_DEVID_SENSE_INPUT(devid_val) ((int) BMVAL(devid_val, 10, 17)) +#define TGU_DEVID_STEPS(devid_val) ((int)BMVAL(devid_val, 3, 6)) +#define NUMBER_BITS_EACH_SIGNAL 4 +#define LENGTH_REGISTER 32 + +/* + * TGU configuration space Step configuration + * offset table space layout + * x-------------------------x$ x-------------x$ + * | |$ | |$ + * | | | reserve |$ + * | | | |$ + * |coresight management | |-------------|ba= se+n*0x1D8+0x1F4$ + * | registe | |---> |prioroty[3] |$ + * | | | |-------------|ba= se+n*0x1D8+0x194$ + * | | | |prioroty[2] |$ + * |-------------------------| | |-------------|ba= se+n*0x1D8+0x134$ + * | | | |prioroty[1] |$ + * | step[7] | | |-------------|ba= se+n*0x1D8+0xD4$ + * |-------------------------|->base+0x40+7*0x1D8 | |prioroty[0] |$ + * | | | |-------------|ba= se+n*0x1D8+0x74$ + * | ... | | | condition |$ + * | | | | select |$ + * |-------------------------|->base+0x40+1*0x1D8 | |-------------|ba= se+n*0x1D8+0x60$ + * | | | | condition |$ + * | step[0] |--------------------> | decode |$ + * |-------------------------|-> base+0x40 |-------------|ba= se+n*0x1D8+0x50$ + * | | | |$ + * | Control and status space| |Timer/Counter|$ + * | space | | |$ + * x-------------------------x->base x-------------x b= ase+n*0x1D8+0x40$ + * + */ +#define STEP_OFFSET 0x1D8 +#define PRIORITY_START_OFFSET 0x0074 +#define PRIORITY_OFFSET 0x60 +#define REG_OFFSET 0x4 + +/* Calculate compare step addresses */ +#define PRIORITY_REG_STEP(step, priority, reg)\ + (PRIORITY_START_OFFSET + PRIORITY_OFFSET * priority +\ + REG_OFFSET * reg + STEP_OFFSET * step) + +#define tgu_dataset_rw(name, step_index, type, reg_num) \ + (&((struct tgu_attribute[]){ { \ + __ATTR(name, 0644, tgu_dataset_show, tgu_dataset_store), \ + step_index, \ + type, \ + reg_num, \ + } })[0].attr.attr) + +#define STEP_PRIORITY(step_index, reg_num, priority) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_PRIORITY##priority, \ + reg_num) + +#define STEP_PRIORITY_LIST(step_index, priority) \ + {STEP_PRIORITY(step_index, 0, priority), \ + STEP_PRIORITY(step_index, 1, priority), \ + STEP_PRIORITY(step_index, 2, priority), \ + STEP_PRIORITY(step_index, 3, priority), \ + STEP_PRIORITY(step_index, 4, priority), \ + STEP_PRIORITY(step_index, 5, priority), \ + STEP_PRIORITY(step_index, 6, priority), \ + STEP_PRIORITY(step_index, 7, priority), \ + STEP_PRIORITY(step_index, 8, priority), \ + STEP_PRIORITY(step_index, 9, priority), \ + STEP_PRIORITY(step_index, 10, priority), \ + STEP_PRIORITY(step_index, 11, priority), \ + STEP_PRIORITY(step_index, 12, priority), \ + STEP_PRIORITY(step_index, 13, priority), \ + STEP_PRIORITY(step_index, 14, priority), \ + STEP_PRIORITY(step_index, 15, priority), \ + STEP_PRIORITY(step_index, 16, priority), \ + STEP_PRIORITY(step_index, 17, priority), \ + NULL \ + } + +#define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\ + (&(const struct attribute_group){\ + .attrs =3D (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\ + .is_visible =3D tgu_node_visible,\ + .name =3D "step" #step "_priority" #priority \ + }) + +enum operation_index { + TGU_PRIORITY0, + TGU_PRIORITY1, + TGU_PRIORITY2, + TGU_PRIORITY3, +}; + +/* Maximum priority that TGU supports */ +#define MAX_PRIORITY 4 + +struct tgu_attribute { + struct device_attribute attr; + u32 step_index; + enum operation_index operation_index; + u32 reg_num; +}; + +struct value_table { + unsigned int *priority; +}; =20 static inline void TGU_LOCK(void __iomem *addr) { @@ -35,6 +142,9 @@ static inline void TGU_UNLOCK(void __iomem *addr) * @dev: Pointer to the associated device structure * @lock: Spinlock for handling concurrent access * @enable: Flag indicating whether the TGU device is enabled + * @value_table: Store given value based on relevant parameters. + * @max_reg: Maximum number of registers + * @max_step: Maximum step size * * This structure defines the data associated with a TGU device, * including its base address, device pointers, clock, spinlock for @@ -46,6 +156,9 @@ struct tgu_drvdata { struct device *dev; spinlock_t lock; bool enable; + struct value_table *value_table; + int max_reg; + int max_step; }; =20 #endif --=20 2.34.1