From nobody Sun Feb 8 19:56:19 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2DB4E35966 for ; Fri, 9 Jan 2026 02:12:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767924729; cv=none; b=AnycOpQHzQlJpxifmd0TAQ+bteGUGchRJfbJXwaTyrHCvofroucWfFW5Z8tyqOlWJa0UW2JmYn+KlMxFAsaZPx8VHNdUYiHjofTjYd+8oioXtobmSnWN8UqFVoPefuk9PxeN7LSahLl+w5IrrUXVsbcHKQWtqtDDSZY8yXidVZw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767924729; c=relaxed/simple; bh=6VY87t9VghiDLhppTTyGc/EGkt+kVJvSCivK71N+61o=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YdTTP5Qyrjg7RqrLLSWGAksw3Wfy3cuDHEpQoW4xeMprMeJKmqWzbTtxHUMo3hMq0GgdQEkPpb3jDUFHMmuwCWsqe0OTjHOQi3aiT/UANcHqq+VfkUs6vXfQcyjRRTbk/EA6B5mDkHmAbztMY2fyLC0RKPdpHKHwiJ+EnqNBED0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=L7AIir4P; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=a3UHkiqm; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="L7AIir4P"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="a3UHkiqm" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 608MpeWM3393674 for ; Fri, 9 Jan 2026 02:12:07 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=+nWc4h1iM5D mFVSbqSbzqsFj4rfaS5ymL17azyq0Eek=; b=L7AIir4POjTyxQCYaktvTprAb2n aN6m50RPWJ1AHDfXQTZ9rLkBwVX78uejRA5LSdTgxNJ7JjDxrehmLoqHfR1FMEBH r8zMv+MGJJeHrDfEiv8MCnTORPFMdYq7rWW+ocwh0i4DDlTSeFqDMEwhglRBGDpA mYWmNyx75TxOn01MKDZqbJEaQtoHGbSjL4UNuqcyv4W+xTRbneS5GMq+D+b9+OMU iOaveqW9n5myQ7pn1bJTGbC4GifULfU6ECSqg4MRUOFr2cnWs6cvYEM8KsZ4bIg9 8+glFFFTAtsp+Zky9B9czk0ndOJ3zmONgpyb2itMw5/VwnOlXag8J3tf/CQ== Received: from mail-dy1-f198.google.com (mail-dy1-f198.google.com [74.125.82.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bjfejsmw9-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 09 Jan 2026 02:12:07 +0000 (GMT) Received: by mail-dy1-f198.google.com with SMTP id 5a478bee46e88-2b0751d8de7so4743221eec.1 for ; Thu, 08 Jan 2026 18:12:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1767924726; x=1768529526; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+nWc4h1iM5DmFVSbqSbzqsFj4rfaS5ymL17azyq0Eek=; b=a3UHkiqmSlJ5m6raNf0Yme6qkRSRzp9uD7bO6EMExFmo85uyKmXZPJStGSXE2TIJA3 sffkXgKK3v5tV1WcI0OYjdTP14R1zykFSNTtQke9yu3+ZbDOXM1sOzPlTuYqpLplCVQh fBn2yubmKLCRzlfMKt5dKD7RBaarBmj9ZBn23LEUC1Z/7vKvBUvTEn5ywmcuewfqB/C2 HfQRWHvmnhqVs9ygcW0iCQ0WJJOipcDFH0U+LlwjCq4RQlxjW6pArYuLgmlg2yJjrc9i mJ3c8PwfHbKsg0Q9obano8NpaWW8QOSNYIeaaoca4r3X4s605or1qf0agIaWdXmGCXyZ XWWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767924726; x=1768529526; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=+nWc4h1iM5DmFVSbqSbzqsFj4rfaS5ymL17azyq0Eek=; b=IkPt0SxJun6lCe9s1STY4pEQLmvZ1mu3BUrfNEOihylnTGTS2nIvfBBo5XjVG2GLIe 3yiw5fHighiXrtHJhaVBKEEUVNTZzVsIlNSCrn+wiRvmq5hGzAtfJh6lTIKu2CmHvShQ 9urNv+ntERsQnVqZ5W1bny2wmCmF7M8Hsdwa7qzoN0KCZkCT/RVJ7IVburrE52EW2ftF KD+6w2EX7FJ6rHe4jY9Y7jjIr2LY1u/orTmB/IPd34cH5GIV+/NAxB2v1Z6TvvkFPEOS 4LEsNlvK1ZFe8Y6srr0mhR94N25NMUZ+d0klrzF7MdR6sjAvg9h7DzuXUgmARYxxv25F 0rug== X-Forwarded-Encrypted: i=1; AJvYcCXOreTFtdp5/fZkie2TVCG8zzpAOWyJB9i3sKrVnNEX9aNkvY9nuJ7otI4j0487WROC6BSOmM0b5UB3XxU=@vger.kernel.org X-Gm-Message-State: AOJu0YwZeOG8puWx4h+XOl6yqAXOtNmHfEUaw9Xm2yWzUCpbclNEbqJh i2NGl1FdwIrDvgJoDfmZjk/UsjTg7O4QrAU182N5VrSe4nv9evtJizX7r5u1Z/gswm1eGZmQau8 7x+RZSxj0B9KI6Ru020p6AR4X4X7WeRNcEy3dPAKw92zc5dgmUa5GhFLjVUcg0/fKD8A= X-Gm-Gg: AY/fxX5zmiHcO6hYjivu70ZLrcUivZrybfZzYwhGbPVXtCoOqCnXK8h/dcdMXSFjTbE OM1916G5VpP1yw69/plEzRD4QPDud09ZdynLwjZ5WfGScEtS8pTLgUumQKJdraiFLYZSshwAuTu KaCbKnCnI72w01lCdp57xDlLe4DkdemmdQVZL0lJZAJ4KusOeuAQHVR+3Rv8opT11fjWLchKEIP dXUK+KGPW0CSzxsL8L2exB1xOhIxyGiIPNtVOtom+/6MQrGXEwT/qA/CKdk6+Ov9ktGZCc2HJ53 0enmd0zlVP4nfrsSokVu8tfVQ6y3hIFN2ELZB9zBFVdvSPdPiwYZE9bgXd6fzJz862putwoXG1S eKCnvI/Q93QTpEgYWX/VpriCGvIMRXjLtYuCo8oEtc4W2WReqsRTUTSV3VoHaXI9f X-Received: by 2002:a05:7300:8aa4:b0:2a4:3592:c612 with SMTP id 5a478bee46e88-2b17d2d6606mr4790660eec.35.1767924726011; Thu, 08 Jan 2026 18:12:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IFgy6sYHhmXV0R+HsajFHl/JVX2fDprTnrm3I/yjxtsb+PByjDHZjVHQYgqLNx+6k5UNumKGw== X-Received: by 2002:a05:7300:8aa4:b0:2a4:3592:c612 with SMTP id 5a478bee46e88-2b17d2d6606mr4790641eec.35.1767924725322; Thu, 08 Jan 2026 18:12:05 -0800 (PST) Received: from hu-songchai-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b1707d76aasm9459111eec.33.2026.01.08.18.12.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 18:12:04 -0800 (PST) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, mike.leach@linaro.org, suzuki.poulose@arm.com, james.clark@arm.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org, Rob Herring Subject: [PATCH v10 1/7] dt-bindings: arm: Add support for Qualcomm TGU trace Date: Thu, 8 Jan 2026 18:11:35 -0800 Message-Id: <20260109021141.3778421-2-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260109021141.3778421-1-songwei.chai@oss.qualcomm.com> References: <20260109021141.3778421-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: yI2xBD5gRKPwIfKRVk35WJQyivZmPLkB X-Proofpoint-GUID: yI2xBD5gRKPwIfKRVk35WJQyivZmPLkB X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA5MDAxMiBTYWx0ZWRfX/v4WhvBxPcId 1OBGiejxYj8/271aR8lPggWnIr92YvfPPtsdCJuZkqUPuHlAE+DtMSUMzHRU+EjwMEOTN4pTXfQ XRi4VnSHfJdB23a4Xc7rnyCreEAsXvHwl2uQ1Rb/MMtiweoZAnT5+wSBGxzb8G78zGOBmgwd4aZ KZQQoENMqaoE3DWG/9SjLbX94aYva3exD80QA61igNKVThDEPJSblNXuJA62omUi2i8Gi+QiEVP 4hOCXBZgLVcjA5x+a0+CT/gdgvh+AG202UZzXavagL9tshAeD4QOnDesZVKUSUBZUJ+J3GQJSxH 3kgTZJ/fQFX3xtQey/nHmtiLSPN5lXfJU6yp+pSl9fiQKzj11HFHtZb3/zi5JKy+8+j87TTT4Sf 2Zou5soeTNd0GT+Mqn6rdz/rTuFSepE4Zek+cLhwld/cMS1NT4oUhGGdATJOJ/MNK11E9l/YemX GVfz0T5g0lvzyUF2z6g== X-Authority-Analysis: v=2.4 cv=ZfAQ98VA c=1 sm=1 tr=0 ts=696063f7 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gEfo2CItAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=N3VNWiZ0WD7Ir0aJMQYA:9 a=bBxd6f-gb0O0v-kibOvt:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-09_01,2026-01-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 suspectscore=0 impostorscore=0 phishscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601090012 Content-Type: text/plain; charset="utf-8" The Trigger Generation Unit (TGU) is designed to detect patterns or sequences within a specific region of the System on Chip (SoC). Once configured and activated, it monitors sense inputs and can detect a pre-programmed state or sequence across clock cycles, subsequently producing a trigger. TGU configuration space offset table x-------------------------x | | | | | | Step configuration | | space layout | coresight management | x-------------x | registers | |---> | | | | | | reserve | | | | | | |-------------------------| | |-------------| | | | | priority[3] | | step[7] |<-- | |-------------| |-------------------------| | | | priority[2] | | | | | |-------------| | ... | |Steps region | | priority[1] | | | | | |-------------| |-------------------------| | | | priority[0] | | |<-- | |-------------| | step[0] |--------------------> | | |-------------------------| | condition | | | | | | control and status | x-------------x | space | | | x-------------------------x |Timer/Counter| | | x-------------x TGU Configuration in Hardware The TGU provides a step region for user configuration, similar to a flow chart. Each step region consists of three register clusters: 1.Priority Region: Sets the required signals with priority. 2.Condition Region: Defines specific requirements (e.g., signal A reaches three times) and the subsequent action once the requirement is met. 3.Timer/Counter (Optional): Provides timing or counting functionality. Add a new tgu.yaml file to describe the bindings required to define the TGU in the device trees. Reviewed-by: Rob Herring (Arm) Signed-off-by: Songwei Chai --- .../devicetree/bindings/arm/qcom,tgu.yaml | 92 +++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/qcom,tgu.yaml diff --git a/Documentation/devicetree/bindings/arm/qcom,tgu.yaml b/Document= ation/devicetree/bindings/arm/qcom,tgu.yaml new file mode 100644 index 000000000000..5b6a58ebe691 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,tgu.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +# Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,tgu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Trigger Generation Unit - TGU + +description: | + The Trigger Generation Unit (TGU) is a Data Engine which can be utilized + to sense a plurality of signals and create a trigger into the CTI or + generate interrupts to processors. The TGU is like the trigger circuit + of a Logic Analyzer. The corresponding trigger logic can be realized by + configuring the conditions for each step after sensing the signal. + Once setup and enabled, it will observe sense inputs and based upon + the activity of those inputs, even over clock cycles, may detect a + preprogrammed state/sequence and then produce a trigger or interrupt. + + The primary use case of the TGU is to detect patterns or sequences on a + given set of signals within some region to identify the issue in time + once there is abnormal behavior in the subsystem. + +maintainers: + - Mao Jinlong + - Songwei Chai + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + enum: + - qcom,tgu + required: + - compatible + +properties: + compatible: + items: + - const: qcom,tgu + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb_pclk + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: + The port mechanism here ensures the relationship between TGU and + TPDM, as TPDM is one of the inputs for TGU. It will allow TGU to + function as TPDM's helper and enable TGU when the connected + TPDM is enabled. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + tgu@10b0e000 { + compatible =3D "qcom,tgu", "arm,primecell"; + reg =3D <0x10b0e000 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + tgu_in_tpdm_swao: endpoint{ + remote-endpoint =3D <&tpdm_swao_out_tgu>; + }; + }; + }; + }; +... --=20 2.34.1 From nobody Sun Feb 8 19:56:19 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4DB9526ED3D for ; Fri, 9 Jan 2026 02:12:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767924734; cv=none; b=NU3cF/lLYG1MbGO0D3kzTNE1xBYmXtltWeCGrL/aBxsbE+M1u0UZEtUmo2z2wLZf+abr/jkI3c/xZJb4UMcJw0z1c1sJPJbDTMv/NBamG36z42uXTl/sCPjqOzWMeoXAjBFGcVhzDTnNXOIa592gl1/7o06Gvs50zJj37MDpz2Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767924734; c=relaxed/simple; bh=Rowm9zTzZd7jesJkLKCtr441qAQBYmk3KmDiCL7ueII=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=iuKhweEBE0+SJFAXmYqrwlzyspdIbjXkpS83ZSNFIJyLZ5O/Pz0ortydx1hE8UVT1bfyFTK0brbN8K9z4qwh1wvvCMg5AZYPmFJleTdHprj8Aqg80vGowooujq0OE2yYgi36pDEArvv5DB9BsFatO7aSalCALrJWByoq/qYmilg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=clPwd6/j; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=PdTpVKk5; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="clPwd6/j"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="PdTpVKk5" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 608MnKiW3625832 for ; Fri, 9 Jan 2026 02:12:09 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=DjHq4ZWbcdh EjTc1QLjuBRN0uHmH39hKhk5mtr7alUE=; b=clPwd6/jgzzD+uPfxtp4JrDVC1q cYFw+saXREJDGqa91ZdYEUsAMtWIs12nwmRU/W2QlcabZ2Clhu1Z8Sd2FeWjupYV xsBEInPeMccCbUT5zSDGNJ7kNXLf2DC+C32hNrMGlbaPHtfCWMVjnjkqxytnMRqZ 0jTu4hcW7LgP7IbAabDYopvzvcbP1jyLczuChOrLheXMSaQzh5YVXgErMuWOCiqI vQPILW+GZ0IKENUjNd9WU6SgzIaNXiYa6/siKJOB+FWc3SpklpukRKeGj/dKJJJI LQiVjF0lowNbnJ9/KeKh/TDPgarYK74K7Pm/zqyTbt1VC5Av3Guc8bp1eRw== Received: from mail-dy1-f198.google.com (mail-dy1-f198.google.com [74.125.82.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bjj8j0yd4-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 09 Jan 2026 02:12:09 +0000 (GMT) Received: by mail-dy1-f198.google.com with SMTP id 5a478bee46e88-2b0530846d3so3158539eec.0 for ; Thu, 08 Jan 2026 18:12:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1767924728; x=1768529528; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DjHq4ZWbcdhEjTc1QLjuBRN0uHmH39hKhk5mtr7alUE=; b=PdTpVKk5EVpZdBKhl/pPyJxx3fP7D2i+Gfh8kAlDkTvspJpBA7UvGpW0xxBTRb4DpU 1XR2sKFL8o3KFoOxTVB4Z/4Dc6Q888SceLvACKuGh7PXBE+kKvcX8dp2Yp4jtpICL0H/ tIZqqKNW52pzMLsVkJcnLRRGIGxFhLlYAAvHmnFxPo2vBv/Ly0HGigNy5T9Ln2feJ3L9 xBah88oD+dphX2mJ1dqIuPVqJouSVHBUPUCeTN05pFNlBw3gkTs3AeHFDkYCMTIaRvoI lnOR7yEQIJN3rTsqq3LzUJdda8WpTMw+Moh6O66CDyz8+DVv7rHlRTTs6uo8FJIK/ys2 wA3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767924728; x=1768529528; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=DjHq4ZWbcdhEjTc1QLjuBRN0uHmH39hKhk5mtr7alUE=; b=tvGawZiYIpDVEulmOr0Ymqzi5XkK6Z0WmP4jmfSItqtE02bIb/CIPqDE+Ns3tfBlEG y4lRwN8ZnGXzL3+VJXwnJdMh6w6x8+e5TqdA813Rygxzxfho1IfSXpnjpllqhSDx1WsN fH8jHaD1FGE8Fj4mZTqcSHKRgcZ7aoqW2HmPdHcOwX2qHTW36IZDzDSIY5m/kuo3wRc/ WTF9kROhcXF3AXBx+5a2/vL2KyUNtPsZgjiUvqrdWJo8zYRnammUsMEWFdWED/pJ5I5Q 6/gHa0voc9jKstpIfhSXkur2BooOw54Mvuv7XnJUaCqtLh3LpBDofFRNwt2QdedgOsj1 c7Rw== X-Forwarded-Encrypted: i=1; AJvYcCXvoPCsot91bXkafbWpcgu6qWpQVk2wG1d0qnQmkgDCRnfK8DusIyfVCHIhIioLd78aToqt1Jt1D1vK1ZM=@vger.kernel.org X-Gm-Message-State: AOJu0YyF8ZPi2yQNUCBNq3Kct0V0mXbPUKhc/9Kugx8ndRZyVFwJ5Etl ejc90LfDKiSprs4S6tRaYM+fzczR6Yhb73b5OzJTivuHC8mJPyaRyfa+SPIwtDvy9RjKLRdP7Q7 u3rmj+Mdxj67RNTFBLuDlFDedq5QQhq4MwDl20N0McXTya2v+yDdvhONgUhTyfRJDIkg= X-Gm-Gg: AY/fxX5tIXSs64F5toGNF6l1p+OjWI1as9DauQWqFwi70W1u/WEMcU6gjdpj4ob57L8 igV3O9C2u/jiXViEp6UkeUP/sQ2dGlMAp4DxBzmj6OvxMoAtaSoMv0/8LqOkSAeOCXEsX8Cxrua JOQ+gbRhDUo0A47vBlUPii1O3IlYvyEp8/2c8caqM5h5GFqlTfyQ6gcp+aqDmJ9gPh/IHZUve+r T6/5IcdQFp5x1J9Tm69w+ozBqEaHRFbAphW9M3n9tgpbqtfdPtZuJ8wF8TRveOycnhhvMyAqVHS 7VJHFPN+U0YjOYpWdVOSYnkLC7W2rsZeQkRxUrhdp4wOf2858eS3Qu7/lJM6JW/v9Vh71OzFexH Qmed0WFRYs+bK+dmvl/qRxXhoHdukkhaolOi9Z8pwbFq62crA8Lz+SM7hTs0tXqqL X-Received: by 2002:a05:693c:4143:10b0:2a4:7cb9:b7da with SMTP id 5a478bee46e88-2b17d2aa0ffmr6543978eec.25.1767924728072; Thu, 08 Jan 2026 18:12:08 -0800 (PST) X-Google-Smtp-Source: AGHT+IEduvwLb5uIwn75t/emerE+73GzcjtqDlkmld1CqwFACGdsJBfZbUUotBYC5bj9Y4HLVZ00BQ== X-Received: by 2002:a05:693c:4143:10b0:2a4:7cb9:b7da with SMTP id 5a478bee46e88-2b17d2aa0ffmr6543939eec.25.1767924727243; Thu, 08 Jan 2026 18:12:07 -0800 (PST) Received: from hu-songchai-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b1707d76aasm9459111eec.33.2026.01.08.18.12.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 18:12:06 -0800 (PST) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, mike.leach@linaro.org, suzuki.poulose@arm.com, james.clark@arm.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org Subject: [PATCH v10 2/7] qcom-tgu: Add TGU driver Date: Thu, 8 Jan 2026 18:11:36 -0800 Message-Id: <20260109021141.3778421-3-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260109021141.3778421-1-songwei.chai@oss.qualcomm.com> References: <20260109021141.3778421-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA5MDAxMiBTYWx0ZWRfX24NMbFyy8eph Sbm52PclTDgRTmGDNRv+LzQTfgBKsP6XnnIziT/ZcvS3JyrVvde0lWKRWCN51N46cTeBgRscUdb dYEkZ9zgzF0PP4DVeryk7pwdpbKmH8wwiF4f1aUEstlrtU+0RE+Bmh3mHjEgIljGKD04ULPrPwf k12QxGQaky9GDp/XK5BZ3VNKJSlPFvlYWLinjR05JwDvQ8/DKHXSK+0bxQGIufOYp9ifu20qW4t gwGyQDZywddBV5gJ6BcXFFLsKX6scngs23y/VhYSaXcQ9kYm2CTEAvh0mhlvNPWcAu2v4h2okhl KIFEvtrkW8toFwQajtzCCXld//tf7FhzB3qfQ2FiPyb6+j4YRntZAdaJuWxFPtK4yiM6ybE/xB3 rR6oFPct4jhLaiD7T67sIroB1o1S4TqbFtgb6Vq5e2AyZ2XuGHWtQxSxhHdmy8oLAO/2xP92NCu KYkBZUw90eNG6CchqPA== X-Authority-Analysis: v=2.4 cv=JIs2csKb c=1 sm=1 tr=0 ts=696063f9 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=h99DN6MNysFgGb7_OMAA:9 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-GUID: BRK4mwb3ZKauH2NK5m5cbT_lQfcmF7jV X-Proofpoint-ORIG-GUID: BRK4mwb3ZKauH2NK5m5cbT_lQfcmF7jV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-09_01,2026-01-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 bulkscore=0 adultscore=0 spamscore=0 clxscore=1015 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601090012 Content-Type: text/plain; charset="utf-8" Add driver to support device TGU (Trigger Generation Unit). TGU is a Data Engine which can be utilized to sense a plurality of signals and create a trigger into the CTI or generate interrupts to processors. Add probe/enable/disable functions for tgu. Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 9 + drivers/Makefile | 1 + drivers/hwtracing/Kconfig | 2 + drivers/hwtracing/qcom/Kconfig | 18 ++ drivers/hwtracing/qcom/Makefile | 3 + drivers/hwtracing/qcom/tgu.c | 176 ++++++++++++++++++ drivers/hwtracing/qcom/tgu.h | 51 +++++ 7 files changed, 260 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-amba-devices-tgu create mode 100644 drivers/hwtracing/qcom/Kconfig create mode 100644 drivers/hwtracing/qcom/Makefile create mode 100644 drivers/hwtracing/qcom/tgu.c create mode 100644 drivers/hwtracing/qcom/tgu.h diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documen= tation/ABI/testing/sysfs-bus-amba-devices-tgu new file mode 100644 index 000000000000..56ec3f5ab5d6 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -0,0 +1,9 @@ +What: /sys/bus/amba/devices//enable_tgu +Date: January 2026 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the enable/disable status of TGU + Accepts only one of the 2 values - 0 or 1. + 0 : disable TGU. + 1 : enable TGU. diff --git a/drivers/Makefile b/drivers/Makefile index ccc05f1eae3e..9608a3debb1f 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -177,6 +177,7 @@ obj-$(CONFIG_RAS) +=3D ras/ obj-$(CONFIG_USB4) +=3D thunderbolt/ obj-$(CONFIG_CORESIGHT) +=3D hwtracing/coresight/ obj-y +=3D hwtracing/intel_th/ +obj-y +=3D hwtracing/qcom/ obj-$(CONFIG_STM) +=3D hwtracing/stm/ obj-$(CONFIG_HISI_PTT) +=3D hwtracing/ptt/ obj-y +=3D android/ diff --git a/drivers/hwtracing/Kconfig b/drivers/hwtracing/Kconfig index 911ee977103c..8a640218eed8 100644 --- a/drivers/hwtracing/Kconfig +++ b/drivers/hwtracing/Kconfig @@ -7,4 +7,6 @@ source "drivers/hwtracing/intel_th/Kconfig" =20 source "drivers/hwtracing/ptt/Kconfig" =20 +source "drivers/hwtracing/qcom/Kconfig" + endmenu diff --git a/drivers/hwtracing/qcom/Kconfig b/drivers/hwtracing/qcom/Kconfig new file mode 100644 index 000000000000..d6f6d4b0f28e --- /dev/null +++ b/drivers/hwtracing/qcom/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# QCOM specific hwtracing drivers +# +menu "Qualcomm specific hwtracing drivers" + +config QCOM_TGU + tristate "QCOM Trigger Generation Unit driver" + help + This driver provides support for Trigger Generation Unit that is + used to detect patterns or sequences on a given set of signals. + TGU is used to monitor a particular bus within a given region to + detect illegal transaction sequences or slave responses. It is also + used to monitor a data stream to detect protocol violations and to + provide a trigger point for centering data around a specific event + within the trace data buffer. + +endmenu diff --git a/drivers/hwtracing/qcom/Makefile b/drivers/hwtracing/qcom/Makef= ile new file mode 100644 index 000000000000..5a0a868c1ea0 --- /dev/null +++ b/drivers/hwtracing/qcom/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_QCOM_TGU) +=3D tgu.o diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c new file mode 100644 index 000000000000..c5b2b384e6ae --- /dev/null +++ b/drivers/hwtracing/qcom/tgu.c @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tgu.h" + +static void tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) +{ + TGU_UNLOCK(drvdata->base); + /* Enable TGU to program the triggers */ + writel(1, drvdata->base + TGU_CONTROL); + TGU_LOCK(drvdata->base); +} + +static int tgu_enable(struct device *dev) +{ + struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); + + guard(spinlock)(&drvdata->lock); + if (drvdata->enable) + return -EBUSY; + + tgu_write_all_hw_regs(drvdata); + drvdata->enable =3D true; + + return 0; +} + +static void tgu_disable(struct device *dev) +{ + struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); + + guard(spinlock)(&drvdata->lock); + if (drvdata->enable) { + TGU_UNLOCK(drvdata->base); + writel(0, drvdata->base + TGU_CONTROL); + TGU_LOCK(drvdata->base); + + drvdata->enable =3D false; + } +} + +static ssize_t enable_tgu_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); + bool enabled; + + guard(spinlock)(&drvdata->lock); + enabled =3D drvdata->enable; + + return sysfs_emit(buf, "%d\n", enabled ? 1 : 0); +} + +/* enable_tgu_store - Configure Trace and Gating Unit (TGU) triggers. */ +static ssize_t enable_tgu_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + unsigned long val; + int ret =3D 0; + + ret =3D kstrtoul(buf, 0, &val); + if (ret) + return ret; + + if (val) { + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return ret; + ret =3D tgu_enable(dev); + if (ret) { + pm_runtime_put(dev); + return ret; + } + } else { + tgu_disable(dev); + pm_runtime_put(dev); + } + + return size; +} +static DEVICE_ATTR_RW(enable_tgu); + +static struct attribute *tgu_common_attrs[] =3D { + &dev_attr_enable_tgu.attr, + NULL, +}; + +static const struct attribute_group tgu_common_grp =3D { + .attrs =3D tgu_common_attrs, + NULL, +}; + +static const struct attribute_group *tgu_attr_groups[] =3D { + &tgu_common_grp, + NULL, +}; + +static int tgu_probe(struct amba_device *adev, const struct amba_id *id) +{ + struct device *dev =3D &adev->dev; + struct tgu_drvdata *drvdata; + int ret; + + drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->dev =3D &adev->dev; + dev_set_drvdata(dev, drvdata); + + drvdata->base =3D devm_ioremap_resource(dev, &adev->res); + if (IS_ERR(drvdata->base)) + return PTR_ERR(drvdata->base); + + spin_lock_init(&drvdata->lock); + + ret =3D sysfs_create_groups(&dev->kobj, tgu_attr_groups); + if (ret) { + dev_err(dev, "failed to create sysfs groups: %d\n", ret); + return ret; + } + + drvdata->enable =3D false; + + pm_runtime_put(&adev->dev); + return 0; +} + +static void tgu_remove(struct amba_device *adev) +{ + struct device *dev =3D &adev->dev; + + sysfs_remove_groups(&dev->kobj, tgu_attr_groups); + + tgu_disable(dev); +} + +static const struct amba_id tgu_ids[] =3D { + { + .id =3D 0x000f0e00, + .mask =3D 0x000fffff, + }, + { 0, 0, NULL }, +}; + +MODULE_DEVICE_TABLE(amba, tgu_ids); + +static struct amba_driver tgu_driver =3D { + .drv =3D { + .name =3D "qcom-tgu", + .suppress_bind_attrs =3D true, + }, + .probe =3D tgu_probe, + .remove =3D tgu_remove, + .id_table =3D tgu_ids, +}; + +module_amba_driver(tgu_driver); + +MODULE_AUTHOR("Songwei Chai "); +MODULE_AUTHOR("Jinlong Mao "); +MODULE_DESCRIPTION("Qualcomm Trigger Generation Unit driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h new file mode 100644 index 000000000000..b11cfb28261d --- /dev/null +++ b/drivers/hwtracing/qcom/tgu.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _QCOM_TGU_H +#define _QCOM_TGU_H + +/* Register addresses */ +#define TGU_CONTROL 0x0000 +#define TGU_LAR 0xfb0 +#define TGU_UNLOCK_OFFSET 0xc5acce55 + +static inline void TGU_LOCK(void __iomem *addr) +{ + do { + /* Wait for things to settle */ + mb(); + writel_relaxed(0x0, addr + TGU_LAR); + } while (0); +} + +static inline void TGU_UNLOCK(void __iomem *addr) +{ + do { + writel_relaxed(TGU_UNLOCK_OFFSET, addr + TGU_LAR); + /* Make sure everyone has seen this */ + mb(); + } while (0); +} + +/** + * struct tgu_drvdata - Data structure for a TGU (Trigger Generator Unit) + * @base: Memory-mapped base address of the TGU device + * @dev: Pointer to the associated device structure + * @lock: Spinlock for handling concurrent access + * @enable: Flag indicating whether the TGU device is enabled + * + * This structure defines the data associated with a TGU device, + * including its base address, device pointers, clock, spinlock for + * synchronization, trigger data pointers, maximum limits for various + * trigger-related parameters, and enable status. + */ +struct tgu_drvdata { + void __iomem *base; + struct device *dev; + spinlock_t lock; + bool enable; +}; + +#endif --=20 2.34.1 From nobody Sun Feb 8 19:56:19 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8820B26F29C for ; Fri, 9 Jan 2026 02:12:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767924736; cv=none; b=WftB1T6JSXn0cPlISUZcaEO7KHYT+UxMkGXbuLLdK6RmJnMn6RPZXaXeIbcevUDOQ79sGobbltXZdwmzhmppYBLWjhcsB+n47oelTjP6XGRzoNepL/Oxg5t6ECe+8X9SREJK/uTtxssKD+NAhf1BVmXFFv7fvFtFBaH82Jwu4QE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767924736; c=relaxed/simple; bh=EEkNfbmQBN+8dnYOxY65nW4ZVEiCodIqcZ8MJeoNU6Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=CbajfimQ+ZxNYUzSAn4lQetyoYs+eGYQOXJfxNI2Q2g/krY2U/xqj7XD6lojNxCa07o5MO6eHQfOK2SIRtvaDITiBhTHDywKhT3zCw2pZNtxgZFJzQJsfynWbdGgFwrrP3nrrCnPtOmw8Xsw+xZrEJaiQZT8RgGmLfV+YReeN/E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=D1n92uk4; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=KzsvfI3J; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="D1n92uk4"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="KzsvfI3J" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 608Hk2FD1701969 for ; Fri, 9 Jan 2026 02:12:11 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=l8ZUSHgXPwx I60cMjU2VQsRQlj6MWG27O1WOHBdsivk=; b=D1n92uk4Xuz6NJo5ZjVbZwac/CL NDQZhMPTufFo+Sasuv4EKbMKGui54p5pPcuFDdZWuwW6dXdpjAydlrdoPYphU5FA KiCjrkzuJoRY+6558EG/XuSm5wdzWdTdpywYzsCEtqXMsuNKqvYbwSYlc1gyEiut Dk1ii7llcboGL1Lcj3RsODXD7BLv9WIeOSs003/HUlK4+56p9yqQD9FbVfMNJWL9 zPXK3ZDrgKmG+862xglhG7EPVIjwKSQfpLbONKuhghBrRufefCK5fDKCtOLEhPYX S3QpDZUbQVmIlAIf0Y3rzjfRTeUQuHF+RJZhxGH0wxg7wYgy6YxNskVNfRg== Received: from mail-dy1-f199.google.com (mail-dy1-f199.google.com [74.125.82.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bjfda9n32-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 09 Jan 2026 02:12:11 +0000 (GMT) Received: by mail-dy1-f199.google.com with SMTP id 5a478bee46e88-2b0531e07e3so3222658eec.1 for ; Thu, 08 Jan 2026 18:12:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1767924731; x=1768529531; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=l8ZUSHgXPwxI60cMjU2VQsRQlj6MWG27O1WOHBdsivk=; b=KzsvfI3JBVRMIQcDZv5US+eN3IgaXIP2CDyLmxPpWLbD+gC/bp4TJdQCAJugaVA9VH n4s4/8lkPjCYX6zQrVrKVtUx9z2GQXOG3xOyEgVkyl3gAGERpm/mVf5OX4rLu8B6XWfq qFGFLuK40gqfBYSfGqwn5S8fCBvW+X9rfSBOfR+Bc04/200fpbeIthDboBypoBjPOt9h 33BmNREmDCeMMz/89CbUWT6Yy9WVvPDiAivewuX5Sss+XEAHbnEUtJSxgGspClEX6f7u cqoP6fEp1kJbg3XDUFs8n2aMT/ld1kISWpyBgGG7WxHj8oOGL9QQiGkKrLD4QSfl03f7 XFsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767924731; x=1768529531; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=l8ZUSHgXPwxI60cMjU2VQsRQlj6MWG27O1WOHBdsivk=; b=q16EkLTNRLs2k7Fx4T5S35DuNkH5FXHS7fz9Gw8cMUazVPh44oyk1wdLUz3hsKgxhv SbBV1gu74slSzEtGFE8mQvVPcNKqAvioGdvKhTg3mqPW1dGN/vSu+hTk4WeZce5bZlFd gC2vopVuPB++USTnpMGM0z894fI4ieWJ6i5RVwHJgoTDWZ8vD6psvOuVfZc53oFdffe1 WgqNVrujhzY3Deynlf5DVPA34LTstWN+CY3F8ipgbMGbEV6+qvQ+cPrN6ZN0WH3tzIwN sPBbi08aDYqP7fh+j/W5kdrWGE6geSMX6ICjS4+Z2qLDgXG35Qc4Hg+ZA6kJnz5hwBWU xupQ== X-Forwarded-Encrypted: i=1; AJvYcCXPHK7N6RtyNa7oZahuAIgSYlBekIdTBVxWvpiCEoCCbkmGs56KQCPhghKVEXVJvpcz1ASFwClhHlxUfLo=@vger.kernel.org X-Gm-Message-State: AOJu0YwVPGNJXXh0VcBxRHNJVt31c9gOE+xOlPEI5p0VjLVXctLXwr85 PMmAty8am5rUQXw1uMyJVJqcAhScUGMbSQnjIbIW4Z2B1lBk8sEB2JxfBgxu0Gq4uV57pNqqyOk s4xIvlU1MuJwvjf0P2iNuYMaAyfEsL+ClFxt8dh96XMf7rBB1k/hpFXEY1x7pVofWwAk= X-Gm-Gg: AY/fxX55LbULzO28vcNKNB5TCkmM/TNM63saIXd3sX6Zk4b9cnzLJ9wq0G3cMLhBAms v6KbrEH81bx/TcOrjnCe+vGqbtNfo9zeG3kga4plQfwGNPYFWvwJlXUnw5qKsI2RKe5W7nvbYBR pHHHzYQkqxs7JLOeVFgqqonaQqf9MM/zjR4RvWkqg/9szBujPJjsbuTIOQyi/dQL2vOvCK5MXdG 30NCJ5dOZbuq0JU9j6kV4rfkB9aaH+rusywzLiwBM6+d1H2+SzMSCh1VDKeDFrpbHWoc/ASaDVV CgTZzh30B6wtXEXdxG+hZ+NcphYwN0APWxdJ5qM7aRqHCUmg4vxDIn0mCsO+soEYWCZDQv9DUpy uROKS9iAw+EKh1bFCyKAazKXEWOlHBLvSU79o+84qb227yD/U0vdQ/Mje7YkHX6o/ X-Received: by 2002:a05:7300:fb09:b0:2a4:3593:466d with SMTP id 5a478bee46e88-2b17d226c06mr5084510eec.9.1767924730245; Thu, 08 Jan 2026 18:12:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IHvY/KIw1x5A1D0EeHpkihkYg3QpZfby76yqehvPy8YBwjD2Fqm89ZI+vwkayOWry45JN4POg== X-Received: by 2002:a05:7300:fb09:b0:2a4:3593:466d with SMTP id 5a478bee46e88-2b17d226c06mr5084502eec.9.1767924729642; Thu, 08 Jan 2026 18:12:09 -0800 (PST) Received: from hu-songchai-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b1707d76aasm9459111eec.33.2026.01.08.18.12.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 18:12:09 -0800 (PST) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, mike.leach@linaro.org, suzuki.poulose@arm.com, james.clark@arm.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org Subject: [PATCH v10 3/7] qcom-tgu: Add signal priority support Date: Thu, 8 Jan 2026 18:11:37 -0800 Message-Id: <20260109021141.3778421-4-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260109021141.3778421-1-songwei.chai@oss.qualcomm.com> References: <20260109021141.3778421-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=Ue1ciaSN c=1 sm=1 tr=0 ts=696063fb cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=aHbVEu0FunmFpxPyS6YA:9 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-ORIG-GUID: UpGLuCsCySR08evwONQ_OIu_UWNIV25w X-Proofpoint-GUID: UpGLuCsCySR08evwONQ_OIu_UWNIV25w X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA5MDAxMiBTYWx0ZWRfXw+RN/TRhjsxx WI2VYBeTur8NO3uUSHyascOuY3yNX9F/z0egy72yvI9VciCPrXH4F/39IfMx5scRkTqQoWS2lvd 9mH6i7QDs9dZI2vkJsFXqER2+hu7ufyUqjSlmj6SJvx64bz+1KW8uhrTgGpuBrXkY20zyWCJSw9 D1bMlRc8y8kPSwqF3nybW5WqrN6BiHtp38oYEXoBL8VaazXHY/JCsiiHSUl73/NK1j2TvWQaqOf p8YSinf0ecxdqS5A8N4HOsAx3fJwR5DRH5YikxhUuoVenuQxEwmRpqstw8Zi5xzsBQ6pC0MEbP+ khkM1WmlJB38Cc6VYUDeydOvvJi4dPyECxbNxO4jB1r9P9WB34SvDoGKrH+E66BW+xpRdctyXAW zvY3d6GfmHmNk2WVXxnJCeK3xr2c/1WQtTiXWWmy8J+5gL7Yrpxm5gxWvoA5m7xpN6xjwhLH9JT 8ia63q4tIkhzSEM8DiQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-09_01,2026-01-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 suspectscore=0 phishscore=0 spamscore=0 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601090012 Content-Type: text/plain; charset="utf-8" Like circuit of a Logic analyzer, in TGU, the requirement could be configured in each step and the trigger will be created once the requirements are met. Add priority functionality here to sort the signals into different priorities. The signal which is wanted could be configured in each step's priority node, the larger number means the higher priority and the signal with higher priority will be sensed more preferentially. Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 7 + drivers/hwtracing/qcom/tgu.c | 160 ++++++++++++++++++ drivers/hwtracing/qcom/tgu.h | 113 +++++++++++++ 3 files changed, 280 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documen= tation/ABI/testing/sysfs-bus-amba-devices-tgu index 56ec3f5ab5d6..ec630e6ff2ee 100644 --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -7,3 +7,10 @@ Description: Accepts only one of the 2 values - 0 or 1. 0 : disable TGU. 1 : enable TGU. + +What: /sys/bus/amba/devices//step[0:7]_priority[0:3]/reg[0:17] +Date: January 2026 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the sensed signal with specific step and priority for TGU. diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c index c5b2b384e6ae..f8870766d624 100644 --- a/drivers/hwtracing/qcom/tgu.c +++ b/drivers/hwtracing/qcom/tgu.c @@ -14,14 +14,120 @@ =20 #include "tgu.h" =20 +static int calculate_array_location(struct tgu_drvdata *drvdata, + int step_index, int operation_index, + int reg_index) +{ + return operation_index * (drvdata->max_step) * (drvdata->max_reg) + + step_index * (drvdata->max_reg) + reg_index; +} + +static ssize_t tgu_dataset_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); + struct tgu_attribute *tgu_attr =3D + container_of(attr, struct tgu_attribute, attr); + int index; + + index =3D calculate_array_location(drvdata, tgu_attr->step_index, + tgu_attr->operation_index, + tgu_attr->reg_num); + + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->priority[index]); +} + +static ssize_t tgu_dataset_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct tgu_drvdata *tgu_drvdata =3D dev_get_drvdata(dev); + struct tgu_attribute *tgu_attr =3D + container_of(attr, struct tgu_attribute, attr); + unsigned long val; + int index; + + ret =3D kstrtoul(buf, 0, &val); + if (ret) + return ret; + + guard(spinlock)(&tgu_drvdata->lock); + index =3D calculate_array_location(tgu_drvdata, tgu_attr->step_index, + tgu_attr->operation_index, + tgu_attr->reg_num); + + tgu_drvdata->value_table->priority[index] =3D val; + return size; +} + +static umode_t tgu_node_visible(struct kobject *kobject, + struct attribute *attr, + int n) +{ + struct device *dev =3D kobj_to_dev(kobject); + struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); + struct device_attribute *dev_attr =3D + container_of(attr, struct device_attribute, attr); + struct tgu_attribute *tgu_attr =3D + container_of(dev_attr, struct tgu_attribute, attr); + int ret =3D SYSFS_GROUP_INVISIBLE; + + if (tgu_attr->step_index < drvdata->max_step) { + ret =3D (tgu_attr->reg_num < drvdata->max_reg) ? + attr->mode : 0; + } + return ret; +} + static void tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) { + int i, j, k, index; + TGU_UNLOCK(drvdata->base); + for (i =3D 0; i < drvdata->max_step; i++) { + for (j =3D 0; j < MAX_PRIORITY; j++) { + for (k =3D 0; k < drvdata->max_reg; k++) { + index =3D calculate_array_location( + drvdata, i, j, k); + + writel(drvdata->value_table->priority[index], + drvdata->base + + PRIORITY_REG_STEP(i, j, k)); + } + } + } /* Enable TGU to program the triggers */ writel(1, drvdata->base + TGU_CONTROL); TGU_LOCK(drvdata->base); } =20 +static void tgu_set_reg_number(struct tgu_drvdata *drvdata) +{ + int num_sense_input; + int num_reg; + u32 devid; + + devid =3D readl(drvdata->base + TGU_DEVID); + + num_sense_input =3D TGU_DEVID_SENSE_INPUT(devid); + if (((num_sense_input * NUMBER_BITS_EACH_SIGNAL) % LENGTH_REGISTER) =3D= =3D 0) + num_reg =3D (num_sense_input * NUMBER_BITS_EACH_SIGNAL) / LENGTH_REGISTE= R; + else + num_reg =3D ((num_sense_input * NUMBER_BITS_EACH_SIGNAL) / LENGTH_REGIST= ER) + 1; + drvdata->max_reg =3D num_reg; + +} + +static void tgu_set_steps(struct tgu_drvdata *drvdata) +{ + u32 devid; + + devid =3D readl(drvdata->base + TGU_DEVID); + + drvdata->max_step =3D TGU_DEVID_STEPS(devid); +} + static int tgu_enable(struct device *dev) { struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); @@ -105,6 +211,38 @@ static const struct attribute_group tgu_common_grp =3D= { =20 static const struct attribute_group *tgu_attr_groups[] =3D { &tgu_common_grp, + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 3), NULL, }; =20 @@ -112,6 +250,8 @@ static int tgu_probe(struct amba_device *adev, const st= ruct amba_id *id) { struct device *dev =3D &adev->dev; struct tgu_drvdata *drvdata; + size_t priority_size; + unsigned int *priority; int ret; =20 drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); @@ -127,12 +267,32 @@ static int tgu_probe(struct amba_device *adev, const = struct amba_id *id) =20 spin_lock_init(&drvdata->lock); =20 + tgu_set_reg_number(drvdata); + tgu_set_steps(drvdata); + ret =3D sysfs_create_groups(&dev->kobj, tgu_attr_groups); if (ret) { dev_err(dev, "failed to create sysfs groups: %d\n", ret); return ret; } =20 + drvdata->value_table =3D + devm_kzalloc(dev, sizeof(*drvdata->value_table), GFP_KERNEL); + if (!drvdata->value_table) + return -ENOMEM; + + priority_size =3D MAX_PRIORITY * drvdata->max_reg * + drvdata->max_step * + sizeof(*(drvdata->value_table->priority)); + + priority =3D devm_kzalloc(dev, priority_size, GFP_KERNEL); + + if (!priority) + return -ENOMEM; + + drvdata->value_table->priority =3D priority; + + drvdata->enable =3D false; =20 pm_runtime_put(&adev->dev); diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h index b11cfb28261d..f54cea01e427 100644 --- a/drivers/hwtracing/qcom/tgu.h +++ b/drivers/hwtracing/qcom/tgu.h @@ -10,6 +10,113 @@ #define TGU_CONTROL 0x0000 #define TGU_LAR 0xfb0 #define TGU_UNLOCK_OFFSET 0xc5acce55 +#define TGU_DEVID 0xfc8 + +#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) +#define TGU_DEVID_SENSE_INPUT(devid_val) ((int) BMVAL(devid_val, 10, 17)) +#define TGU_DEVID_STEPS(devid_val) ((int)BMVAL(devid_val, 3, 6)) +#define NUMBER_BITS_EACH_SIGNAL 4 +#define LENGTH_REGISTER 32 + +/* + * TGU configuration space Step configuration + * offset table space layout + * x-------------------------x$ x-------------x$ + * | |$ | |$ + * | | | reserve |$ + * | | | |$ + * |coresight management | |-------------|ba= se+n*0x1D8+0x1F4$ + * | registe | |---> |prioroty[3] |$ + * | | | |-------------|ba= se+n*0x1D8+0x194$ + * | | | |prioroty[2] |$ + * |-------------------------| | |-------------|ba= se+n*0x1D8+0x134$ + * | | | |prioroty[1] |$ + * | step[7] | | |-------------|ba= se+n*0x1D8+0xD4$ + * |-------------------------|->base+0x40+7*0x1D8 | |prioroty[0] |$ + * | | | |-------------|ba= se+n*0x1D8+0x74$ + * | ... | | | condition |$ + * | | | | select |$ + * |-------------------------|->base+0x40+1*0x1D8 | |-------------|ba= se+n*0x1D8+0x60$ + * | | | | condition |$ + * | step[0] |--------------------> | decode |$ + * |-------------------------|-> base+0x40 |-------------|ba= se+n*0x1D8+0x50$ + * | | | |$ + * | Control and status space| |Timer/Counter|$ + * | space | | |$ + * x-------------------------x->base x-------------x b= ase+n*0x1D8+0x40$ + * + */ +#define STEP_OFFSET 0x1D8 +#define PRIORITY_START_OFFSET 0x0074 +#define PRIORITY_OFFSET 0x60 +#define REG_OFFSET 0x4 + +/* Calculate compare step addresses */ +#define PRIORITY_REG_STEP(step, priority, reg)\ + (PRIORITY_START_OFFSET + PRIORITY_OFFSET * priority +\ + REG_OFFSET * reg + STEP_OFFSET * step) + +#define tgu_dataset_rw(name, step_index, type, reg_num) \ + (&((struct tgu_attribute[]){ { \ + __ATTR(name, 0644, tgu_dataset_show, tgu_dataset_store), \ + step_index, \ + type, \ + reg_num, \ + } })[0].attr.attr) + +#define STEP_PRIORITY(step_index, reg_num, priority) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_PRIORITY##priority, \ + reg_num) + +#define STEP_PRIORITY_LIST(step_index, priority) \ + {STEP_PRIORITY(step_index, 0, priority), \ + STEP_PRIORITY(step_index, 1, priority), \ + STEP_PRIORITY(step_index, 2, priority), \ + STEP_PRIORITY(step_index, 3, priority), \ + STEP_PRIORITY(step_index, 4, priority), \ + STEP_PRIORITY(step_index, 5, priority), \ + STEP_PRIORITY(step_index, 6, priority), \ + STEP_PRIORITY(step_index, 7, priority), \ + STEP_PRIORITY(step_index, 8, priority), \ + STEP_PRIORITY(step_index, 9, priority), \ + STEP_PRIORITY(step_index, 10, priority), \ + STEP_PRIORITY(step_index, 11, priority), \ + STEP_PRIORITY(step_index, 12, priority), \ + STEP_PRIORITY(step_index, 13, priority), \ + STEP_PRIORITY(step_index, 14, priority), \ + STEP_PRIORITY(step_index, 15, priority), \ + STEP_PRIORITY(step_index, 16, priority), \ + STEP_PRIORITY(step_index, 17, priority), \ + NULL \ + } + +#define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\ + (&(const struct attribute_group){\ + .attrs =3D (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\ + .is_visible =3D tgu_node_visible,\ + .name =3D "step" #step "_priority" #priority \ + }) + +enum operation_index { + TGU_PRIORITY0, + TGU_PRIORITY1, + TGU_PRIORITY2, + TGU_PRIORITY3, +}; + +/* Maximum priority that TGU supports */ +#define MAX_PRIORITY 4 + +struct tgu_attribute { + struct device_attribute attr; + u32 step_index; + enum operation_index operation_index; + u32 reg_num; +}; + +struct value_table { + unsigned int *priority; +}; =20 static inline void TGU_LOCK(void __iomem *addr) { @@ -35,6 +142,9 @@ static inline void TGU_UNLOCK(void __iomem *addr) * @dev: Pointer to the associated device structure * @lock: Spinlock for handling concurrent access * @enable: Flag indicating whether the TGU device is enabled + * @value_table: Store given value based on relevant parameters. + * @max_reg: Maximum number of registers + * @max_step: Maximum step size * * This structure defines the data associated with a TGU device, * including its base address, device pointers, clock, spinlock for @@ -46,6 +156,9 @@ struct tgu_drvdata { struct device *dev; spinlock_t lock; bool enable; + struct value_table *value_table; + int max_reg; + int max_step; }; =20 #endif --=20 2.34.1 From nobody Sun Feb 8 19:56:19 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38D38267714 for ; Fri, 9 Jan 2026 02:12:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767924735; cv=none; b=bzLgXezvZQu0L0uEOIEiIhIYlik7HUVFxwOEWzm0AAyXJ+JpWQ5hc2zVYAiHmEhdujzoafGaY/H1Y40ZqZ/VwDVlUjG7M+S/Bh1LDX6MmtungxP4t01a3Kpj5JEdHWCLnHby95xrMWUpXQimuqGXGR9wTmBXugMamDlo1/RX0xg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767924735; c=relaxed/simple; bh=B237vHjES8RwVgLyKAaKUbj6JuBQtmyK5uR4oO8lk0k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EJAM8iQkNbmCgeGC6J1epRsvgy6ZXhmIzciT3Jsgp1GsgsuG0ZR9cCjQ0qzf9scaF7piesQpeXWN3DRcgCH6p7v4wynGCXEO3GOwqDJq9hCZ1Wb444L3vrMrfsuIJhUmyS9CdzN4WN3H4Ntydw+1omEt5a+dMBVYj2r6EIND42Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=C7WIvEGd; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=JEdmNygb; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="C7WIvEGd"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="JEdmNygb" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 608Hk8R03165833 for ; Fri, 9 Jan 2026 02:12:13 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=5WVO73lg8H3 MqrdW6UnPUf0qCgX6e5vtCpaCq604azc=; b=C7WIvEGd05Nt3zR9fkNuoeMLDJq 5ajka8PevZmCOjads3pfvv6b9rIRUbBJ31/ZEvl/cR8VtFYgWuHVm5AyHrZqR8R+ UDiIw5T35I1mIyr459lajbNH7ADLWXTIbLL1VJSC+trE02wqHI3ooTZtGdhLCl0s oCnpZ3/GyDvqMCjwEX1U5JFQa2UhYa1rWhGFzQKVPSiQvgiTP2A7dUBU/L/oapOS 3kq4yAj5tA3WTM2L3DbZI9+5zbErYpXamlbMsK3m4N3MbJntRwCEDOiORHf03dc/ 2hDypJJa8n3TIsS79SM/I++eQnlU/P7rNQJ872hDW7maBZcY0PWLLRwjUdA== Received: from mail-dy1-f199.google.com (mail-dy1-f199.google.com [74.125.82.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bj8923609-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 09 Jan 2026 02:12:13 +0000 (GMT) Received: by mail-dy1-f199.google.com with SMTP id 5a478bee46e88-2b062c1aa44so5420913eec.0 for ; Thu, 08 Jan 2026 18:12:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1767924733; x=1768529533; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5WVO73lg8H3MqrdW6UnPUf0qCgX6e5vtCpaCq604azc=; b=JEdmNygbV43xqK2tn8rh5bIVObDu0DRUnBt560UZ8ALwYGS90sg+J1/WLFuYFpM6Ny FjMsRlEjxSSU5WvGDXECuYVnsa54PCrIdCgoiuAPbFDgsyfJSSpsDQhjEtRBZf26l3zb 56zCtU1iojJUwYn0/Ma0USQZxrWaPTzmaAk33VFiNkkto2hxD7Lsn+v6x9vLX/bdvdjN kKSiT/DuIN0tzgJe0KBxeZPByz/HQOTrguVsp92XpQwRja5rNn8dnBmosxI5p+Zi7XNe Bb/3inWDxuFDAiPoDhi7F9KlZClWUiiRMdthqgGlDHFyoZDHIJRoiWVVCAiu6U3VwYOf ihkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767924733; x=1768529533; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=5WVO73lg8H3MqrdW6UnPUf0qCgX6e5vtCpaCq604azc=; b=WUBBYh0hQ+ligBizmPgfR8yEClk/Bmz/ileCpVALv0tiZ7Kbtlrjo0Hg9cCiOTIxzH 3DXT26Z1Tip7OrIaFmNN9kukEdPtovtk0UTY0BN0VHvycatHiNEKrgG+EuFlxNGFbPjj ayrpEPPRLcRiZotMF21AjCCaax4FWuAFnQtZ+/ldWjjgLrTEVDNXhlCL5tlZIBgF2beX arxLNg/teJV3dgifXXBHsExCXjXmmA8FUrhh+kiH4aNJgOQOJ5NpHIwL755E9Pa7GQH1 xFpcWkcvqjKbGo8nwbXbtx+Yja+FfBvcAtP6JU3M805JDDSxOi4uL5uAlxLNg+1suRGU ShiA== X-Forwarded-Encrypted: i=1; AJvYcCXH3bShckFWNN+fgEz4iRfvVDFGv7QOTuNkoMYLS8gdJoTI7MMdJQUmzPQlHPEsVGy4Kw8hU/9666wgTWg=@vger.kernel.org X-Gm-Message-State: AOJu0Yw6Q5QJRFuipYXJJQtoVBDtlFukO6sAuVh+JO8QtKseRJZ0N5vb STqzWGGSugv2rjLiIpUUyV4Yyx6YoLyZ6CINJpuQiWgXcoH6CzB1cWbsojL7iUIK/9LBTRDPVAp b6VvJOfGfsnY99RhQyKO1CTAqDp+JVHbjEMqCLzT+srC7Lfvsouj04KJmNqiwELCr/Og= X-Gm-Gg: AY/fxX4IQx4E4QR7PSQJz65qP+K2OdrE+/92JEZX7bOJU68zhV/6oY0bkY1HHtSbPPD 5iuk3sPZRUROIOI7SOwaNUsNDYzvMQPPsSu0tcWLQYiGsA78IYZxWODAzBZGBRdRhF1kDHkPIEe CrddJVPwjADHmtlvFt0+aNRIxMv3EO0yWj2O4E+dRzcQWaerIA6uLvQngeTw9EwOqdc80l7QimL oeZRokvDCr6OuZ64cRV8cYVOBKkqXdtxPdRClC4x4Qzwo+6UPT/xYGRPD8/nf4TLmyx9Un60Laf /fHSlLnhWITKIZCK2B4wsmcIu2yDIcrlU0STZIwAdhrKQBYM4kRK3nYNwXq+P8g372N+UyTOdw8 SbeJeVpD3C7JCBpe10w4Bp1EanlqjPt7/XyvoYjSqNJQwRk4UmVoA252fsTssnbHN X-Received: by 2002:a05:7301:5f0b:b0:2a4:3593:9695 with SMTP id 5a478bee46e88-2b17d23527emr5326608eec.18.1767924732362; Thu, 08 Jan 2026 18:12:12 -0800 (PST) X-Google-Smtp-Source: AGHT+IHUu2PFxFOXUcj+EWrOOh50w4JB2Xz1rrSqKPrl6QbYgC/sAP0pFru4LiT+M4Q8VUJfQBSsNg== X-Received: by 2002:a05:7301:5f0b:b0:2a4:3593:9695 with SMTP id 5a478bee46e88-2b17d23527emr5326591eec.18.1767924731791; Thu, 08 Jan 2026 18:12:11 -0800 (PST) Received: from hu-songchai-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b1707d76aasm9459111eec.33.2026.01.08.18.12.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 18:12:11 -0800 (PST) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, mike.leach@linaro.org, suzuki.poulose@arm.com, james.clark@arm.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org Subject: [PATCH v10 4/7] qcom-tgu: Add TGU decode support Date: Thu, 8 Jan 2026 18:11:38 -0800 Message-Id: <20260109021141.3778421-5-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260109021141.3778421-1-songwei.chai@oss.qualcomm.com> References: <20260109021141.3778421-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=M45A6iws c=1 sm=1 tr=0 ts=696063fd cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=17ZuibbC0m_VACr_8A0A:9 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-ORIG-GUID: arQMilZA6HTASqPk8YHFoU3yTr2P-Xih X-Proofpoint-GUID: arQMilZA6HTASqPk8YHFoU3yTr2P-Xih X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA5MDAxMiBTYWx0ZWRfX3j24oJosIYWP Sl9lB1PheKQC6acz6iT0PXGcQhRsMGYmAd6pBJRNCxtuYTVSj5S+0JdE2BYfUFSvpaireNUBNPb jNjGGxX5QVK1dSh21MwOJCzJtG/xtkRHbwRpX3X7T3xCrT+h/hNiBG+kSA/OmqYary9Fse9iZi/ yysXzEy6N40uwSsJI0+Z+GTYOfeq84SRYicjJlBOEVrmcx743cxqyw0/5Hb7AVkQiG/FC48DL+p jWWrl9QdzqrbpSCRUKQ9DHUJjM+il/HkGEqvY33IpQfzZQZdZyCT0IMQBmR8w1/WAEFGZo2t0IL Klsigrni/c5rvUImbcsn8+3Y2RFUqnLJXIcNbZdmVIUxavbMXkYZg/BY7uwpUJGMArv0ZfvOdfl sYFfLXpJvmiJGO567U9A0fWZipojJspsq0KJa2qlhzucWfaermcOW8eG1PI43zTNgaOitdOLyJ3 c4Kv40m8Wwh82KVYuLg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-09_01,2026-01-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 suspectscore=0 clxscore=1015 spamscore=0 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601090012 Content-Type: text/plain; charset="utf-8" Decoding is when all the potential pieces for creating a trigger are brought together for a given step. Example - there may be a counter keeping track of some occurrences and a priority-group that is being used to detect a pattern on the sense inputs. These 2 inputs to condition_decode must be programmed, for a given step, to establish the condition for the trigger, or movement to another steps. Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 7 + drivers/hwtracing/qcom/tgu.c | 162 ++++++++++++++++-- drivers/hwtracing/qcom/tgu.h | 27 +++ 3 files changed, 177 insertions(+), 19 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documen= tation/ABI/testing/sysfs-bus-amba-devices-tgu index ec630e6ff2ee..4efa36a11d8e 100644 --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -14,3 +14,10 @@ KernelVersion 6.19 Contact: Jinlong Mao , Songwei Chai Description: (RW) Set/Get the sensed signal with specific step and priority for TGU. + +What: /sys/bus/amba/devices//step[0:7]_condition_decode/reg[0:3] +Date: January 2026 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the decode mode with specific step for TGU. diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c index f8870766d624..39301d35ee9d 100644 --- a/drivers/hwtracing/qcom/tgu.c +++ b/drivers/hwtracing/qcom/tgu.c @@ -18,8 +18,36 @@ static int calculate_array_location(struct tgu_drvdata *= drvdata, int step_index, int operation_index, int reg_index) { - return operation_index * (drvdata->max_step) * (drvdata->max_reg) + - step_index * (drvdata->max_reg) + reg_index; + int ret =3D -EINVAL; + + switch (operation_index) { + case TGU_PRIORITY0: + case TGU_PRIORITY1: + case TGU_PRIORITY2: + case TGU_PRIORITY3: + ret =3D operation_index * (drvdata->max_step) * + (drvdata->max_reg) + + step_index * (drvdata->max_reg) + reg_index; + break; + case TGU_CONDITION_DECODE: + ret =3D step_index * (drvdata->max_condition_decode) + + reg_index; + break; + default: + break; + } + return ret; +} + +static int check_array_location(struct tgu_drvdata *drvdata, int step, + int ops, int reg) +{ + int result =3D calculate_array_location(drvdata, step, ops, reg); + + if (result =3D=3D -EINVAL) + dev_err(drvdata->dev, "%s - Fail\n", __func__); + + return result; } =20 static ssize_t tgu_dataset_show(struct device *dev, @@ -30,12 +58,26 @@ static ssize_t tgu_dataset_show(struct device *dev, container_of(attr, struct tgu_attribute, attr); int index; =20 - index =3D calculate_array_location(drvdata, tgu_attr->step_index, - tgu_attr->operation_index, - tgu_attr->reg_num); - - return sysfs_emit(buf, "0x%x\n", - drvdata->value_table->priority[index]); + index =3D check_array_location(drvdata, tgu_attr->step_index, + tgu_attr->operation_index, tgu_attr->reg_num); + + if (index =3D=3D -EINVAL) + return index; + + switch (tgu_attr->operation_index) { + case TGU_PRIORITY0: + case TGU_PRIORITY1: + case TGU_PRIORITY2: + case TGU_PRIORITY3: + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->priority[index]); + case TGU_CONDITION_DECODE: + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->condition_decode[index]); + default: + break; + } + return -EINVAL; } =20 static ssize_t tgu_dataset_store(struct device *dev, @@ -47,18 +89,37 @@ static ssize_t tgu_dataset_store(struct device *dev, container_of(attr, struct tgu_attribute, attr); unsigned long val; int index; + int ret; =20 ret =3D kstrtoul(buf, 0, &val); if (ret) return ret; =20 guard(spinlock)(&tgu_drvdata->lock); - index =3D calculate_array_location(tgu_drvdata, tgu_attr->step_index, + index =3D check_array_location(tgu_drvdata, tgu_attr->step_index, tgu_attr->operation_index, tgu_attr->reg_num); =20 - tgu_drvdata->value_table->priority[index] =3D val; - return size; + if (index =3D=3D -EINVAL) + return -EINVAL; + + switch (tgu_attr->operation_index) { + case TGU_PRIORITY0: + case TGU_PRIORITY1: + case TGU_PRIORITY2: + case TGU_PRIORITY3: + tgu_drvdata->value_table->priority[index] =3D val; + ret =3D size; + break; + case TGU_CONDITION_DECODE: + tgu_drvdata->value_table->condition_decode[index] =3D val; + ret =3D size; + break; + default: + ret =3D -EINVAL; + break; + } + return ret; } =20 static umode_t tgu_node_visible(struct kobject *kobject, @@ -74,13 +135,27 @@ static umode_t tgu_node_visible(struct kobject *kobjec= t, int ret =3D SYSFS_GROUP_INVISIBLE; =20 if (tgu_attr->step_index < drvdata->max_step) { - ret =3D (tgu_attr->reg_num < drvdata->max_reg) ? - attr->mode : 0; + switch (tgu_attr->operation_index) { + case TGU_PRIORITY0: + case TGU_PRIORITY1: + case TGU_PRIORITY2: + case TGU_PRIORITY3: + ret =3D (tgu_attr->reg_num < drvdata->max_reg) ? + attr->mode : 0; + break; + case TGU_CONDITION_DECODE: + ret =3D (tgu_attr->reg_num < + drvdata->max_condition_decode) ? + attr->mode : 0; + break; + default: + break; + } } return ret; } =20 -static void tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) +static ssize_t tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) { int i, j, k, index; =20 @@ -88,8 +163,10 @@ static void tgu_write_all_hw_regs(struct tgu_drvdata *d= rvdata) for (i =3D 0; i < drvdata->max_step; i++) { for (j =3D 0; j < MAX_PRIORITY; j++) { for (k =3D 0; k < drvdata->max_reg; k++) { - index =3D calculate_array_location( + index =3D check_array_location( drvdata, i, j, k); + if (index =3D=3D -EINVAL) + goto exit; =20 writel(drvdata->value_table->priority[index], drvdata->base + @@ -97,9 +174,23 @@ static void tgu_write_all_hw_regs(struct tgu_drvdata *d= rvdata) } } } + + for (i =3D 0; i < drvdata->max_step; i++) { + for (j =3D 0; j < drvdata->max_condition_decode; j++) { + index =3D check_array_location(drvdata, i, + TGU_CONDITION_DECODE, j); + if (index =3D=3D -EINVAL) + goto exit; + + writel(drvdata->value_table->condition_decode[index], + drvdata->base + CONDITION_DECODE_STEP(i, j)); + } + } /* Enable TGU to program the triggers */ writel(1, drvdata->base + TGU_CONTROL); +exit: TGU_LOCK(drvdata->base); + return index >=3D 0 ? 0 : -EINVAL; } =20 static void tgu_set_reg_number(struct tgu_drvdata *drvdata) @@ -128,18 +219,32 @@ static void tgu_set_steps(struct tgu_drvdata *drvdata) drvdata->max_step =3D TGU_DEVID_STEPS(devid); } =20 +static void tgu_set_conditions(struct tgu_drvdata *drvdata) +{ + u32 devid; + + devid =3D readl(drvdata->base + TGU_DEVID); + drvdata->max_condition_decode =3D TGU_DEVID_CONDITIONS(devid); +} + static int tgu_enable(struct device *dev) { struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); + int ret =3D 0; =20 guard(spinlock)(&drvdata->lock); if (drvdata->enable) return -EBUSY; =20 - tgu_write_all_hw_regs(drvdata); + ret =3D tgu_write_all_hw_regs(drvdata); + + if (ret =3D=3D -EINVAL) + goto exit; + drvdata->enable =3D true; =20 - return 0; +exit: + return ret; } =20 static void tgu_disable(struct device *dev) @@ -243,6 +348,14 @@ static const struct attribute_group *tgu_attr_groups[]= =3D { PRIORITY_ATTRIBUTE_GROUP_INIT(7, 1), PRIORITY_ATTRIBUTE_GROUP_INIT(7, 2), PRIORITY_ATTRIBUTE_GROUP_INIT(7, 3), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(0), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(1), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(2), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(3), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(4), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(5), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(6), + CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(7), NULL, }; =20 @@ -250,8 +363,8 @@ static int tgu_probe(struct amba_device *adev, const st= ruct amba_id *id) { struct device *dev =3D &adev->dev; struct tgu_drvdata *drvdata; - size_t priority_size; - unsigned int *priority; + size_t priority_size, condition_size; + unsigned int *priority, *condition; int ret; =20 drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); @@ -269,6 +382,7 @@ static int tgu_probe(struct amba_device *adev, const st= ruct amba_id *id) =20 tgu_set_reg_number(drvdata); tgu_set_steps(drvdata); + tgu_set_conditions(drvdata); =20 ret =3D sysfs_create_groups(&dev->kobj, tgu_attr_groups); if (ret) { @@ -292,6 +406,16 @@ static int tgu_probe(struct amba_device *adev, const s= truct amba_id *id) =20 drvdata->value_table->priority =3D priority; =20 + condition_size =3D drvdata->max_condition_decode * + drvdata->max_step * + sizeof(*(drvdata->value_table->condition_decode)); + + condition =3D devm_kzalloc(dev, condition_size, GFP_KERNEL); + + if (!condition) + return -ENOMEM; + + drvdata->value_table->condition_decode =3D condition; =20 drvdata->enable =3D false; =20 diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h index f54cea01e427..0d058663aca5 100644 --- a/drivers/hwtracing/qcom/tgu.h +++ b/drivers/hwtracing/qcom/tgu.h @@ -15,6 +15,7 @@ #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) #define TGU_DEVID_SENSE_INPUT(devid_val) ((int) BMVAL(devid_val, 10, 17)) #define TGU_DEVID_STEPS(devid_val) ((int)BMVAL(devid_val, 3, 6)) +#define TGU_DEVID_CONDITIONS(devid_val) ((int)BMVAL(devid_val, 0, 2)) #define NUMBER_BITS_EACH_SIGNAL 4 #define LENGTH_REGISTER 32 =20 @@ -48,6 +49,7 @@ */ #define STEP_OFFSET 0x1D8 #define PRIORITY_START_OFFSET 0x0074 +#define CONDITION_DECODE_OFFSET 0x0050 #define PRIORITY_OFFSET 0x60 #define REG_OFFSET 0x4 =20 @@ -56,6 +58,9 @@ (PRIORITY_START_OFFSET + PRIORITY_OFFSET * priority +\ REG_OFFSET * reg + STEP_OFFSET * step) =20 +#define CONDITION_DECODE_STEP(step, decode) \ + (CONDITION_DECODE_OFFSET + REG_OFFSET * decode + STEP_OFFSET * step) + #define tgu_dataset_rw(name, step_index, type, reg_num) \ (&((struct tgu_attribute[]){ { \ __ATTR(name, 0644, tgu_dataset_show, tgu_dataset_store), \ @@ -68,6 +73,9 @@ tgu_dataset_rw(reg##reg_num, step_index, TGU_PRIORITY##priority, \ reg_num) =20 +#define STEP_DECODE(step_index, reg_num) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_DECODE, reg_num) + #define STEP_PRIORITY_LIST(step_index, priority) \ {STEP_PRIORITY(step_index, 0, priority), \ STEP_PRIORITY(step_index, 1, priority), \ @@ -90,6 +98,14 @@ NULL \ } =20 +#define STEP_DECODE_LIST(n) \ + {STEP_DECODE(n, 0), \ + STEP_DECODE(n, 1), \ + STEP_DECODE(n, 2), \ + STEP_DECODE(n, 3), \ + NULL \ + } + #define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\ (&(const struct attribute_group){\ .attrs =3D (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\ @@ -97,11 +113,19 @@ .name =3D "step" #step "_priority" #priority \ }) =20 +#define CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(step)\ + (&(const struct attribute_group){\ + .attrs =3D (struct attribute*[])STEP_DECODE_LIST(step),\ + .is_visible =3D tgu_node_visible,\ + .name =3D "step" #step "_condition_decode" \ + }) + enum operation_index { TGU_PRIORITY0, TGU_PRIORITY1, TGU_PRIORITY2, TGU_PRIORITY3, + TGU_CONDITION_DECODE, }; =20 /* Maximum priority that TGU supports */ @@ -116,6 +140,7 @@ struct tgu_attribute { =20 struct value_table { unsigned int *priority; + unsigned int *condition_decode; }; =20 static inline void TGU_LOCK(void __iomem *addr) @@ -145,6 +170,7 @@ static inline void TGU_UNLOCK(void __iomem *addr) * @value_table: Store given value based on relevant parameters. * @max_reg: Maximum number of registers * @max_step: Maximum step size + * @max_condition_decode: Maximum number of condition_decode * * This structure defines the data associated with a TGU device, * including its base address, device pointers, clock, spinlock for @@ -159,6 +185,7 @@ struct tgu_drvdata { struct value_table *value_table; int max_reg; int max_step; + int max_condition_decode; }; =20 #endif --=20 2.34.1 From nobody Sun Feb 8 19:56:19 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B5DE27B348 for ; Fri, 9 Jan 2026 02:12:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767924744; cv=none; b=WRoVjUP/jhyE4YZKUqBgjVt8W8rVHeIosyAUXL5GSiii9kQCFEbLq0EKifFuWyEsDND7hCLf8TO/08TwB8UhUrV9bQX8PXfxPUk26mlJZWjaa9km5PnrFHn1r9lTfzD/FN+YimpPNUU2IbpZvNCT9/oqelRz/x9BWsNrERCRvhg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767924744; c=relaxed/simple; bh=2W0HlvZ4Kc5fyudXSSocWCz1uUDaBFXgLVleyOVI8do=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=lc2g+zmgXg6tlUkTLUgDES0JabXt9Ty+gQBNIPjZ22cKNGolkyUFwzzbp3EhIWgQKgQzHyJXYAXaGjshczo4p+kqhQ+lYhiruJwIPhssTM8rhXr5IGS6XmDQGaGoyPO0MbR6mmNHLyNkop6VFOrbvycUp7qhdoYy2ySFBXyum0o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=MX2oC+At; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=gEfwbz9Z; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="MX2oC+At"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="gEfwbz9Z" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 608IrDQ53142604 for ; Fri, 9 Jan 2026 02:12:16 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=N+myu6Q3Uz3 7abbv2+ZhB/G75uimUCatGO2AyT4TJwg=; b=MX2oC+AtAfwgmCPJG5xQWDNJ91i DIiDusEJrCumSG7XTZ83lSU9WwMbmX+dg2fawscZnIODTNVzdvoL5S3uupicvnph va1Bm7AshKUxaCmtRpjg3vc/NBI5A3coEouzILYh8MiEF73Fbdd0ya9DBbzXlxea aDbaQo1pBPhZ2g5QuOiVGQX2ijinuK/tELSGMvYPFW/HADyqsdcY0vdyk9tovaml bnx6iLk4nNIp20wPQwmY/TbqR2p9Omt2AQBIO/sfjUcxF8qXowA76NI0JdJk4Q0j c2YuSMbxSMMbLC8PkEwN9yiIj/RhFQnYfZNLM6PjJegnvHgu68Il7puh1tg== Received: from mail-dy1-f199.google.com (mail-dy1-f199.google.com [74.125.82.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bjj8j0ydk-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 09 Jan 2026 02:12:16 +0000 (GMT) Received: by mail-dy1-f199.google.com with SMTP id 5a478bee46e88-2ae25c02e7bso10001144eec.0 for ; Thu, 08 Jan 2026 18:12:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1767924736; x=1768529536; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N+myu6Q3Uz37abbv2+ZhB/G75uimUCatGO2AyT4TJwg=; b=gEfwbz9ZFdjckW9r9UUCly3YonK3vdrsLzhDpHFPTXXG9fW8DEB8DaEVBDyKpFXUF5 5X+Jffr8uM8Ci4mE4CeFMTmq1BLBHQ7EjFjqr2OV5wF5bv5ma3c9BhYI9cIH4D0j/xYq BRwFF40X70UhF1I5tMo2jke0kJZknsT4kuFRAk498LjQ6KvesMHBEzWPlECidGUfnlaE qFJCi4/Ygk7q7aNJFQ6Q3KWhluPjGW+GDSmEeDtJ5KSYrZM7JQIf+tg85ngJseSLK2IY Nnf3U3hjXe49L2+J2FHpdvrhxcWXILxQTTHsDl3w3GC4WIoupSycRtKnuKi/3Ip72ocA srow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767924736; x=1768529536; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=N+myu6Q3Uz37abbv2+ZhB/G75uimUCatGO2AyT4TJwg=; b=n2bu8/98moqIaLWyTTARzyvCS3KfmstqCjfT3t3yuJJH00fXgQRMJCMWS8Sajv75f9 m5atml/eZoFN963suWLRlDQxsvbNLH5s8Cvl8oK5meVrCQri/M7mAJNpCYzuUj8XuTaf 5NNs/gHa0wBahx1J9lRr+Jrzeg4TznlO//GB+OaBeVErPzJ2qmYLIZQvecg3JEMHsFee 1fLvvqOUoNZsKYfGlAqMioZc9rmCuvkkMhLqYxlEvlQej8UXd3/fSxEBRg1EEu/33jzV 74UDNoi+7GTdtFJBcHG7hYhLBb1QM3x68irr3GQ0HCDxNcwoljnkscBXwSwOQeaz62mA Arhg== X-Forwarded-Encrypted: i=1; AJvYcCUvGCGru9XlUAj1xTenOHA0SXPdKVlEeX/ewIIgkGqJeNSklhtnlW2ebx0XsVR+YdVOmuq+Q8zUQ9pRcCc=@vger.kernel.org X-Gm-Message-State: AOJu0Yyu4MkdG8pkwlF/Zp1XIczXaZ2Dze/DdxSuYNP/VnKRnTdtJL6m xxO+XHtM6F3xZ/j0Q6k+biHOo3Wz/UUKAhKlrO6fbTe8PXQb5Cr5Wyi+QdYLlkUHSDuCTV89FUD cTxRNw0kA3L+5MHBlxtiNbtgS+eMB6EGtqVLWs7emVPZNpruoxpSLuXId2ZgNqvVd5bE= X-Gm-Gg: AY/fxX4c5JI6pi54s3VR4XoE+llMFmyTF7TTGaynxB+BPOzCGzBGqjTvdrTbua12tp6 z34NhJGaO/wxEhWjH7Y3SQdqfa+q5aYNqh129ChDAggzQ2lnZ868k5Kkogy5yKfpk+OfZyVLW4r 6r7Ji5hn6hV3EtLftsQl5K8TJ+AaU/WMnt4Z1JGpOhY3JwjUN4QyqUC3nfno5F5TJzSKHjAfW7K qhn47uZrF8Dsx5w0/0/3ksm8r76IyXd/AMlnuKD0U1raa0UR6jMPXT39cmHKEGs8tyilhQmiCd9 4clTzM7J5ckPfyJFdwyuKKiAo793o8NYnYxQbEj0wotw1fHNPExl2CNLXO12ysslGm51619T0R9 S2nzePgwyqRGezj/Wfhf3gyN8OAhpHRSKpm5CMjHoKWgM/4eGpci5k607OmyEcadQ X-Received: by 2002:a05:7301:3c0d:b0:2ae:53da:9787 with SMTP id 5a478bee46e88-2b17d341ae8mr6720527eec.40.1767924735555; Thu, 08 Jan 2026 18:12:15 -0800 (PST) X-Google-Smtp-Source: AGHT+IEKFgWsIT72dZ/Xuo5XHw8dLQ7t1LZ0LXIEV72FJw3uERtVeUXXDTK+zXUN1oaEW4j99yYURA== X-Received: by 2002:a05:7301:3c0d:b0:2ae:53da:9787 with SMTP id 5a478bee46e88-2b17d341ae8mr6720498eec.40.1767924734978; Thu, 08 Jan 2026 18:12:14 -0800 (PST) Received: from hu-songchai-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b1707d76aasm9459111eec.33.2026.01.08.18.12.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 18:12:14 -0800 (PST) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, mike.leach@linaro.org, suzuki.poulose@arm.com, james.clark@arm.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org Subject: [PATCH v10 5/7] qcom-tgu: Add support to configure next action Date: Thu, 8 Jan 2026 18:11:39 -0800 Message-Id: <20260109021141.3778421-6-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260109021141.3778421-1-songwei.chai@oss.qualcomm.com> References: <20260109021141.3778421-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA5MDAxMiBTYWx0ZWRfX0YcK+1oppalz dT4d5RYcv3m4b6DOEdVcNHRLpQ00pjbm+sFpsS91VYLKO4l4Do9er/q/fGM+mZ8PH9VhIzQkJPF hJ30DFImWlc6Pc07v1nZoK/U0onm/QdNGKxMvX6Ih2sEZau8WW0aNyAlogSP9uWgU0HR7vbIDVd rl76S5pgWkxUhCTYsTC72034mLOaf61PDgpwvsEdSb21os5nRwNeGlEyEUkX+BEzKOgMB7/LfWv ClNMkLfCRXYpIORDnPVF7lEMBMJB8H/dBixAIkZv0q20NWNGALJ4Z6V//KRZbG8oCSw1FyIdHzv 2TublQsYtuE1ZBVFJXMP9yUjCFcEEIiSOZptfzX1qrRRWHg+kELSI/ihO/TXuA84nEy61nU9dzi GqZzq02JRXxMxJeFYiAQPjXd9Js+9IAo6sPqh+912F5o5DkBunYVXrw7hpOJkgnuJyzETH2ZnJB kAz39xEanCQcfJfwnQA== X-Authority-Analysis: v=2.4 cv=JIs2csKb c=1 sm=1 tr=0 ts=69606400 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=Q9DP89o4N5N1XlnrPa8A:9 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-GUID: ozWtBLi7wdwoye3OUxpgp0_teN6j32Ak X-Proofpoint-ORIG-GUID: ozWtBLi7wdwoye3OUxpgp0_teN6j32Ak X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-09_01,2026-01-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 bulkscore=0 adultscore=0 spamscore=0 clxscore=1015 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601090012 Content-Type: text/plain; charset="utf-8" Add "select" node for each step to determine if another step is taken, trigger(s) are generated, counters/timers incremented/decremented, etc. Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 7 +++ drivers/hwtracing/qcom/tgu.c | 57 ++++++++++++++++++- drivers/hwtracing/qcom/tgu.h | 27 +++++++++ 3 files changed, 89 insertions(+), 2 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documen= tation/ABI/testing/sysfs-bus-amba-devices-tgu index 4efa36a11d8e..fffe65d3c0db 100644 --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -21,3 +21,10 @@ KernelVersion 6.19 Contact: Jinlong Mao , Songwei Chai Description: (RW) Set/Get the decode mode with specific step for TGU. + +What: /sys/bus/amba/devices//step[0:7]_condition_select/reg[0:3] +Date: January 2026 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the next action with specific step for TGU. diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c index 39301d35ee9d..e1a1f0f423ba 100644 --- a/drivers/hwtracing/qcom/tgu.c +++ b/drivers/hwtracing/qcom/tgu.c @@ -33,6 +33,10 @@ static int calculate_array_location(struct tgu_drvdata *= drvdata, ret =3D step_index * (drvdata->max_condition_decode) + reg_index; break; + case TGU_CONDITION_SELECT: + ret =3D step_index * (drvdata->max_condition_select) + + reg_index; + break; default: break; } @@ -74,6 +78,9 @@ static ssize_t tgu_dataset_show(struct device *dev, case TGU_CONDITION_DECODE: return sysfs_emit(buf, "0x%x\n", drvdata->value_table->condition_decode[index]); + case TGU_CONDITION_SELECT: + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->condition_select[index]); default: break; } @@ -115,6 +122,10 @@ static ssize_t tgu_dataset_store(struct device *dev, tgu_drvdata->value_table->condition_decode[index] =3D val; ret =3D size; break; + case TGU_CONDITION_SELECT: + tgu_drvdata->value_table->condition_select[index] =3D val; + ret =3D size; + break; default: ret =3D -EINVAL; break; @@ -148,6 +159,15 @@ static umode_t tgu_node_visible(struct kobject *kobjec= t, drvdata->max_condition_decode) ? attr->mode : 0; break; + case TGU_CONDITION_SELECT: + /* 'default' register is at the end of 'select' region */ + if (tgu_attr->reg_num =3D=3D + drvdata->max_condition_select - 1) + attr->name =3D "default"; + ret =3D (tgu_attr->reg_num < + drvdata->max_condition_select) ? + attr->mode : 0; + break; default: break; } @@ -186,6 +206,19 @@ static ssize_t tgu_write_all_hw_regs(struct tgu_drvdat= a *drvdata) drvdata->base + CONDITION_DECODE_STEP(i, j)); } } + + for (i =3D 0; i < drvdata->max_step; i++) { + for (j =3D 0; j < drvdata->max_condition_select; j++) { + index =3D check_array_location(drvdata, i, + TGU_CONDITION_SELECT, j); + + if (index =3D=3D -EINVAL) + goto exit; + + writel(drvdata->value_table->condition_select[index], + drvdata->base + CONDITION_SELECT_STEP(i, j)); + } + } /* Enable TGU to program the triggers */ writel(1, drvdata->base + TGU_CONTROL); exit: @@ -225,6 +258,8 @@ static void tgu_set_conditions(struct tgu_drvdata *drvd= ata) =20 devid =3D readl(drvdata->base + TGU_DEVID); drvdata->max_condition_decode =3D TGU_DEVID_CONDITIONS(devid); + /* select region has an additional 'default' register */ + drvdata->max_condition_select =3D TGU_DEVID_CONDITIONS(devid) + 1; } =20 static int tgu_enable(struct device *dev) @@ -356,6 +391,14 @@ static const struct attribute_group *tgu_attr_groups[]= =3D { CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(5), CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(6), CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(7), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(0), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(1), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(2), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(3), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(4), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(5), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(6), + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(7), NULL, }; =20 @@ -363,8 +406,8 @@ static int tgu_probe(struct amba_device *adev, const st= ruct amba_id *id) { struct device *dev =3D &adev->dev; struct tgu_drvdata *drvdata; - size_t priority_size, condition_size; - unsigned int *priority, *condition; + size_t priority_size, condition_size, select_size; + unsigned int *priority, *condition, *select; int ret; =20 drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); @@ -417,6 +460,16 @@ static int tgu_probe(struct amba_device *adev, const s= truct amba_id *id) =20 drvdata->value_table->condition_decode =3D condition; =20 + select_size =3D drvdata->max_condition_select * drvdata->max_step * + sizeof(*(drvdata->value_table->condition_select)); + + select =3D devm_kzalloc(dev, select_size, GFP_KERNEL); + + if (!select) + return -ENOMEM; + + drvdata->value_table->condition_select =3D select; + drvdata->enable =3D false; =20 pm_runtime_put(&adev->dev); diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h index 0d058663aca5..8c92e88d7e2c 100644 --- a/drivers/hwtracing/qcom/tgu.h +++ b/drivers/hwtracing/qcom/tgu.h @@ -50,6 +50,7 @@ #define STEP_OFFSET 0x1D8 #define PRIORITY_START_OFFSET 0x0074 #define CONDITION_DECODE_OFFSET 0x0050 +#define CONDITION_SELECT_OFFSET 0x0060 #define PRIORITY_OFFSET 0x60 #define REG_OFFSET 0x4 =20 @@ -61,6 +62,9 @@ #define CONDITION_DECODE_STEP(step, decode) \ (CONDITION_DECODE_OFFSET + REG_OFFSET * decode + STEP_OFFSET * step) =20 +#define CONDITION_SELECT_STEP(step, select) \ + (CONDITION_SELECT_OFFSET + REG_OFFSET * select + STEP_OFFSET * step) + #define tgu_dataset_rw(name, step_index, type, reg_num) \ (&((struct tgu_attribute[]){ { \ __ATTR(name, 0644, tgu_dataset_show, tgu_dataset_store), \ @@ -76,6 +80,9 @@ #define STEP_DECODE(step_index, reg_num) \ tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_DECODE, reg_num) =20 +#define STEP_SELECT(step_index, reg_num) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_SELECT, reg_num) + #define STEP_PRIORITY_LIST(step_index, priority) \ {STEP_PRIORITY(step_index, 0, priority), \ STEP_PRIORITY(step_index, 1, priority), \ @@ -106,6 +113,15 @@ NULL \ } =20 +#define STEP_SELECT_LIST(n) \ + {STEP_SELECT(n, 0), \ + STEP_SELECT(n, 1), \ + STEP_SELECT(n, 2), \ + STEP_SELECT(n, 3), \ + STEP_SELECT(n, 4), \ + NULL \ + } + #define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\ (&(const struct attribute_group){\ .attrs =3D (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\ @@ -120,12 +136,20 @@ .name =3D "step" #step "_condition_decode" \ }) =20 +#define CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(step)\ + (&(const struct attribute_group){\ + .attrs =3D (struct attribute*[])STEP_SELECT_LIST(step),\ + .is_visible =3D tgu_node_visible,\ + .name =3D "step" #step "_condition_select" \ + }) + enum operation_index { TGU_PRIORITY0, TGU_PRIORITY1, TGU_PRIORITY2, TGU_PRIORITY3, TGU_CONDITION_DECODE, + TGU_CONDITION_SELECT, }; =20 /* Maximum priority that TGU supports */ @@ -141,6 +165,7 @@ struct tgu_attribute { struct value_table { unsigned int *priority; unsigned int *condition_decode; + unsigned int *condition_select; }; =20 static inline void TGU_LOCK(void __iomem *addr) @@ -171,6 +196,7 @@ static inline void TGU_UNLOCK(void __iomem *addr) * @max_reg: Maximum number of registers * @max_step: Maximum step size * @max_condition_decode: Maximum number of condition_decode + * @max_condition_select: Maximum number of condition_select * * This structure defines the data associated with a TGU device, * including its base address, device pointers, clock, spinlock for @@ -186,6 +212,7 @@ struct tgu_drvdata { int max_reg; int max_step; int max_condition_decode; + int max_condition_select; }; =20 #endif --=20 2.34.1 From nobody Sun Feb 8 19:56:19 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DECCC27602C for ; Fri, 9 Jan 2026 02:12:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767924751; cv=none; b=G9CP2YTw3E9Z1B170VnieJPPNPU1HD1W3+FqgyTmtKXfkqcS4XJiA7jUADgrqrMPagUm0QRfzJ/8nXc6x75fKY41JUPFFjuYDgmyw4zEwQQcAnL7wFIv76hohpZSpxuWyQojDcXTQcLKPVnH4KLB/Ao9mFYwiwyJx9wdU9FA+Ao= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767924751; c=relaxed/simple; bh=TKHdvTT6nAXOE2RMFo8H2PDlDMvR4rtBIQcHpFhtmto=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jzIY/iwG/Z7HmIhRH+V8YuqlBuAGXHXQAaQ31cXdNjc7m+sYd9DLbpNnrzf9Q78h6XnQJwMGeDIIBWaE9l0nWAc97hnnbjHNPV82sc0FTN1mVZ4bEm76U1eE1EV2wPL9LsUpqZVU0LWwDxRrz8s5msZav8k4m2vWPutqI0393Ic= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=I7IzEYfn; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=RxTiS9v4; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="I7IzEYfn"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="RxTiS9v4" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 608HkJlA2154169 for ; Fri, 9 Jan 2026 02:12:19 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=VN+NLUr6REu iKzvXSuFSTv5hWAaHT1JfLZCPjKK8pmo=; b=I7IzEYfn4/qwNGCbxIXVx9xmsht 4nBSEAqubgFJ7pxNaFU7ilbhrjXvhXOPL/5x9EVHewyM1PB02Tx25fjaSFvBcJix yipXDunXo0b5FVwyZYBReWhnmozJGobsooGUFXOE5HATTfVjeMTGBYvi0Yu6U6gI ycgPwSUSVcGR1H03255Lcl7rAR8tdQrbdM+XzdWNT4Nw6HNAecwo+hMUn5nv2zEE rtjJIyXT1mTIu2pruT0ojH8e4XgvQLwvRzOeA7PXtQrDGktkmt5YZ1olhDjmOuKX +ADYYgKCdIWQAsaMmX1+emYF+uFwMDtZTpOwmV4DVzRQdi0HJncvIEYDYLQ== Received: from mail-dy1-f197.google.com (mail-dy1-f197.google.com [74.125.82.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bj3d6c0mj-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 09 Jan 2026 02:12:19 +0000 (GMT) Received: by mail-dy1-f197.google.com with SMTP id 5a478bee46e88-2b0751d8de7so4743435eec.1 for ; Thu, 08 Jan 2026 18:12:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1767924739; x=1768529539; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VN+NLUr6REuiKzvXSuFSTv5hWAaHT1JfLZCPjKK8pmo=; b=RxTiS9v4M2vlPyoFtJLY1xhUQew+LSTC10Ugcph1f/D58Gtx/ndwqB3A9zh5Dt1Qed zOeyNIyy9Rw1Tkkv/lpuhkCbApfzq9BROxnyp/QEBu1gO1S1h/AgssRlZvzhz1+ZIzm9 uyIcnwIEr7RTM/FW/lR7ZdSUq6cpIl6LCH4d5cxMu8wI1ZlWpqiyBMVNs7vMDYNIiqYp wUdgx4jImVsbrh8UFuBf3MNLnq3elqpji+Mgd6UL/4rMIgM0WeouW7tZh4gyaLMW/R+1 zGNFetFw4ZK32eEb6u5hf7UawY44PCINwvohLq4yxujTQ0vA9TPNu5AzOHsY1tvf02+t lFWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767924739; x=1768529539; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=VN+NLUr6REuiKzvXSuFSTv5hWAaHT1JfLZCPjKK8pmo=; b=mhCPaAHFxB+JOglgGunM14FYuCgGoxd2Ruo5xKHzYbOJrv+SURIqKi5jceeomTOTW3 7gpRuHANv8eri57Sz0vVykJadRn2lGh38I9brQguEahPqK1xLQGCBl0BjHSGYyZ+Eoev zzq9KyvQ1pTtl5NbdrQd/tBWXlpX6NXkvyPmnKKA8gIvJskYChsN8tPQOTxLpVw5FIPe eE6a2Dnve1yLuIpVR1iBESvMIPb9bLmLuLwFHwH+/ILJ1j+kuDx5VAMwYR+7CvqqPzvE xJ4n/P/TTSbLhwbo/qwi73+56fyn9SRpNdfPHrPLa6//cYdlKgIjPIozGDrvZjcoQfvi gjgQ== X-Forwarded-Encrypted: i=1; AJvYcCVe7p++e/yjiqDVyqameD89ICeCEPLSV3D2+vFm9OZWx4pRRZyl8lkZQ+smlffJS9A6GAVjy5PyBh+dBEI=@vger.kernel.org X-Gm-Message-State: AOJu0YwDzxPiHXCsUxmHII/MFNA1ROY/dWOv8D9nnuU9Ojbu3QcFjwre q/ErUie9JOoq4Ss12iXSLVONQmxxH/TK4xiA+83gLRAUMilR3gAAU0tS8Dwe6pBCvRoxK7PJFTU Fxiz0CRmVNYHzJ2yuiQIsJqITRd5EWX9HDAW6WPsuDm5OUeW99ZXe5pKecGfgwiIbs/4= X-Gm-Gg: AY/fxX4eMtAhydqiRrgp+c6LSfPr9DXxSd47tvRXTSNR07CuJptiypQtjDpGMskoTzV GLuyothQjoqYi9w1x6qn29nobT8F8qQjdwps5lzUZgO8R5qhkMDsiURffSH9Cu0kp8cN2KpJyLm O+bHpjIMbiGSDa46wA3W5zS+DncPm2L304bX+Dc7D91GBMC0jDDsAp3+2Tso538y1CdUpAn07E1 4AL5qCuz1+YR7y0Yl8mZd91fsX8QHiVPFRgGaRt90q+Byv5xf7W9s1KZbZy5z8ad9+MVLckio// Aj+6nuY4sVHO6hHPIPYy/9OC16zGJov0OnCv4TVFLQunrjM+qFPcM/tx5xx9Y74yBGAQa6fJZJR jg9siLEN9ZuV2reLqsnkJDptePEQ4tQ0V+W5QQo2m5sNZj/+4h0fRdhN56qBEWfYF X-Received: by 2002:a05:7300:c7cb:b0:2a7:1232:f3a2 with SMTP id 5a478bee46e88-2b17d069324mr4710518eec.0.1767924738396; Thu, 08 Jan 2026 18:12:18 -0800 (PST) X-Google-Smtp-Source: AGHT+IHNQKSPU9AaSxqFHao7LN5YXfpKAC0MLeIPxREDaQEYuh0jQ7nhOShJHhPVFAwqyO7aLAVLLg== X-Received: by 2002:a05:7300:c7cb:b0:2a7:1232:f3a2 with SMTP id 5a478bee46e88-2b17d069324mr4710489eec.0.1767924737731; Thu, 08 Jan 2026 18:12:17 -0800 (PST) Received: from hu-songchai-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b1707d76aasm9459111eec.33.2026.01.08.18.12.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 18:12:17 -0800 (PST) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, mike.leach@linaro.org, suzuki.poulose@arm.com, james.clark@arm.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org Subject: [PATCH v10 6/7] qcom-tgu: Add timer/counter functionality for TGU Date: Thu, 8 Jan 2026 18:11:40 -0800 Message-Id: <20260109021141.3778421-7-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260109021141.3778421-1-songwei.chai@oss.qualcomm.com> References: <20260109021141.3778421-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: dQBZr0jE5svdStPUtnymxcPcuMMSbthb X-Authority-Analysis: v=2.4 cv=APfYzRIR c=1 sm=1 tr=0 ts=69606403 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=eGDQztGCVwpQsGOtWZEA:9 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA5MDAxMiBTYWx0ZWRfXwRec0oZq+iEE OLc4MVVb6Zgfoe4CL14lbYLZF3kbx6b5BJvcm91GP9P1aRLSw0rQSfUElQSSkM4C1b10/MK9bVF O4Lt7PmHZB6GWn7wvsMJ6fWyFGD9g8OtfB0CpQ7tf63/n+srk4Tr4Nd45dOvFcLagfP/zZce2Kq XZsOGPN0pJJ9riherV9Lpq2ADYkkPXXBbC06zuDGeL66rzQy/rf2APOq3weTeU6d4TgxUSNBaI9 554q5HuW4h0e2n7GFahAqOEq3s+J7ouTvo96Ek8rkMdKV2mv6ipUoRgkYiVbL6HeAI6pie+YHSb 9nbAvEiDgCIf8KFT+YHpEBH1gP/cxSwdSl3SsC0i1m/g9oclExBOj+ydvrPI5gEM+QhBGyVx0CP ishGMLqttFEtPsBVP3ofiwaS5jY1FW8N9r6IrzhSXEr08YBEhM4zhSVDYsRJtoJ0M8Z3CrKD54N 7JRYtbmq63KXrT/I1XA== X-Proofpoint-ORIG-GUID: dQBZr0jE5svdStPUtnymxcPcuMMSbthb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-09_01,2026-01-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 clxscore=1015 adultscore=0 phishscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601090012 Content-Type: text/plain; charset="utf-8" Add counter and timer node for each step which could be programed if they are to be utilized in trigger event/sequence. Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 14 ++ drivers/hwtracing/qcom/tgu.c | 126 +++++++++++++++++- drivers/hwtracing/qcom/tgu.h | 54 ++++++++ 3 files changed, 192 insertions(+), 2 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documen= tation/ABI/testing/sysfs-bus-amba-devices-tgu index fffe65d3c0db..61b5a08bdee1 100644 --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -28,3 +28,17 @@ KernelVersion 6.19 Contact: Jinlong Mao , Songwei Chai Description: (RW) Set/Get the next action with specific step for TGU. + +What: /sys/bus/amba/devices//step[0:7]_timer/reg[0:1] +Date: January 2026 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the timer value with specific step for TGU. + +What: /sys/bus/amba/devices//step[0:7]_counter/reg[0:1] +Date: January 2026 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the counter value with specific step for TGU. diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c index e1a1f0f423ba..a3d9c3c4e28a 100644 --- a/drivers/hwtracing/qcom/tgu.c +++ b/drivers/hwtracing/qcom/tgu.c @@ -37,6 +37,12 @@ static int calculate_array_location(struct tgu_drvdata *= drvdata, ret =3D step_index * (drvdata->max_condition_select) + reg_index; break; + case TGU_COUNTER: + ret =3D step_index * (drvdata->max_counter) + reg_index; + break; + case TGU_TIMER: + ret =3D step_index * (drvdata->max_timer) + reg_index; + break; default: break; } @@ -81,6 +87,12 @@ static ssize_t tgu_dataset_show(struct device *dev, case TGU_CONDITION_SELECT: return sysfs_emit(buf, "0x%x\n", drvdata->value_table->condition_select[index]); + case TGU_TIMER: + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->timer[index]); + case TGU_COUNTER: + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->counter[index]); default: break; } @@ -126,6 +138,14 @@ static ssize_t tgu_dataset_store(struct device *dev, tgu_drvdata->value_table->condition_select[index] =3D val; ret =3D size; break; + case TGU_TIMER: + tgu_drvdata->value_table->timer[index] =3D val; + ret =3D size; + break; + case TGU_COUNTER: + tgu_drvdata->value_table->counter[index] =3D val; + ret =3D size; + break; default: ret =3D -EINVAL; break; @@ -168,6 +188,22 @@ static umode_t tgu_node_visible(struct kobject *kobjec= t, drvdata->max_condition_select) ? attr->mode : 0; break; + case TGU_COUNTER: + if (drvdata->max_counter =3D=3D 0) + ret =3D SYSFS_GROUP_INVISIBLE; + else + ret =3D (tgu_attr->reg_num < + drvdata->max_counter) ? + attr->mode : 0; + break; + case TGU_TIMER: + if (drvdata->max_timer =3D=3D 0) + ret =3D SYSFS_GROUP_INVISIBLE; + else + ret =3D (tgu_attr->reg_num < + drvdata->max_timer) ? + attr->mode : 0; + break; default: break; } @@ -219,6 +255,30 @@ static ssize_t tgu_write_all_hw_regs(struct tgu_drvdat= a *drvdata) drvdata->base + CONDITION_SELECT_STEP(i, j)); } } + + for (i =3D 0; i < drvdata->max_step; i++) { + for (j =3D 0; j < drvdata->max_timer; j++) { + index =3D check_array_location(drvdata, i, TGU_TIMER, j); + + if (index =3D=3D -EINVAL) + goto exit; + + writel(drvdata->value_table->timer[index], + drvdata->base + TIMER_COMPARE_STEP(i, j)); + } + } + + for (i =3D 0; i < drvdata->max_step; i++) { + for (j =3D 0; j < drvdata->max_counter; j++) { + index =3D check_array_location(drvdata, i, TGU_COUNTER, j); + + if (index =3D=3D -EINVAL) + goto exit; + + writel(drvdata->value_table->counter[index], + drvdata->base + COUNTER_COMPARE_STEP(i, j)); + } + } /* Enable TGU to program the triggers */ writel(1, drvdata->base + TGU_CONTROL); exit: @@ -262,6 +322,31 @@ static void tgu_set_conditions(struct tgu_drvdata *drv= data) drvdata->max_condition_select =3D TGU_DEVID_CONDITIONS(devid) + 1; } =20 +static void tgu_set_timer_counter(struct tgu_drvdata *drvdata) +{ + int num_timers, num_counters; + u32 devid2; + + devid2 =3D readl(drvdata->base + CORESIGHT_DEVID2); + + if (TGU_DEVID2_TIMER0(devid2) && TGU_DEVID2_TIMER1(devid2)) + num_timers =3D 2; + else if (TGU_DEVID2_TIMER0(devid2) || TGU_DEVID2_TIMER1(devid2)) + num_timers =3D 1; + else + num_timers =3D 0; + + if (TGU_DEVID2_COUNTER0(devid2) && TGU_DEVID2_COUNTER1(devid2)) + num_counters =3D 2; + else if (TGU_DEVID2_COUNTER0(devid2) || TGU_DEVID2_COUNTER1(devid2)) + num_counters =3D 1; + else + num_counters =3D 0; + + drvdata->max_timer =3D num_timers; + drvdata->max_counter =3D num_counters; +} + static int tgu_enable(struct device *dev) { struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); @@ -399,6 +484,22 @@ static const struct attribute_group *tgu_attr_groups[]= =3D { CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(5), CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(6), CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(7), + TIMER_ATTRIBUTE_GROUP_INIT(0), + TIMER_ATTRIBUTE_GROUP_INIT(1), + TIMER_ATTRIBUTE_GROUP_INIT(2), + TIMER_ATTRIBUTE_GROUP_INIT(3), + TIMER_ATTRIBUTE_GROUP_INIT(4), + TIMER_ATTRIBUTE_GROUP_INIT(5), + TIMER_ATTRIBUTE_GROUP_INIT(6), + TIMER_ATTRIBUTE_GROUP_INIT(7), + COUNTER_ATTRIBUTE_GROUP_INIT(0), + COUNTER_ATTRIBUTE_GROUP_INIT(1), + COUNTER_ATTRIBUTE_GROUP_INIT(2), + COUNTER_ATTRIBUTE_GROUP_INIT(3), + COUNTER_ATTRIBUTE_GROUP_INIT(4), + COUNTER_ATTRIBUTE_GROUP_INIT(5), + COUNTER_ATTRIBUTE_GROUP_INIT(6), + COUNTER_ATTRIBUTE_GROUP_INIT(7), NULL, }; =20 @@ -406,8 +507,8 @@ static int tgu_probe(struct amba_device *adev, const st= ruct amba_id *id) { struct device *dev =3D &adev->dev; struct tgu_drvdata *drvdata; - size_t priority_size, condition_size, select_size; - unsigned int *priority, *condition, *select; + size_t priority_size, condition_size, select_size, timer_size, counter_si= ze; + unsigned int *priority, *condition, *select, *timer, *counter; int ret; =20 drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); @@ -426,6 +527,7 @@ static int tgu_probe(struct amba_device *adev, const st= ruct amba_id *id) tgu_set_reg_number(drvdata); tgu_set_steps(drvdata); tgu_set_conditions(drvdata); + tgu_set_timer_counter(drvdata); =20 ret =3D sysfs_create_groups(&dev->kobj, tgu_attr_groups); if (ret) { @@ -470,6 +572,26 @@ static int tgu_probe(struct amba_device *adev, const s= truct amba_id *id) =20 drvdata->value_table->condition_select =3D select; =20 + timer_size =3D drvdata->max_step * drvdata->max_timer * + sizeof(*(drvdata->value_table->timer)); + + timer =3D devm_kzalloc(dev, timer_size, GFP_KERNEL); + + if (!timer) + return -ENOMEM; + + drvdata->value_table->timer =3D timer; + + counter_size =3D drvdata->max_step * drvdata->max_counter * + sizeof(*(drvdata->value_table->counter)); + + counter =3D devm_kzalloc(dev, counter_size, GFP_KERNEL); + + if (!counter) + return -ENOMEM; + + drvdata->value_table->counter =3D counter; + drvdata->enable =3D false; =20 pm_runtime_put(&adev->dev); diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h index 8c92e88d7e2c..94708750b02d 100644 --- a/drivers/hwtracing/qcom/tgu.h +++ b/drivers/hwtracing/qcom/tgu.h @@ -11,11 +11,17 @@ #define TGU_LAR 0xfb0 #define TGU_UNLOCK_OFFSET 0xc5acce55 #define TGU_DEVID 0xfc8 +#define CORESIGHT_DEVID2 0xfc0 =20 #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) #define TGU_DEVID_SENSE_INPUT(devid_val) ((int) BMVAL(devid_val, 10, 17)) #define TGU_DEVID_STEPS(devid_val) ((int)BMVAL(devid_val, 3, 6)) #define TGU_DEVID_CONDITIONS(devid_val) ((int)BMVAL(devid_val, 0, 2)) +#define TGU_DEVID2_TIMER0(devid_val) ((int)BMVAL(devid_val, 18, 23)) +#define TGU_DEVID2_TIMER1(devid_val) ((int)BMVAL(devid_val, 13, 17)) +#define TGU_DEVID2_COUNTER0(devid_val) ((int)BMVAL(devid_val, 6, 11)) +#define TGU_DEVID2_COUNTER1(devid_val) ((int)BMVAL(devid_val, 0, 5)) + #define NUMBER_BITS_EACH_SIGNAL 4 #define LENGTH_REGISTER 32 =20 @@ -51,6 +57,8 @@ #define PRIORITY_START_OFFSET 0x0074 #define CONDITION_DECODE_OFFSET 0x0050 #define CONDITION_SELECT_OFFSET 0x0060 +#define TIMER_START_OFFSET 0x0040 +#define COUNTER_START_OFFSET 0x0048 #define PRIORITY_OFFSET 0x60 #define REG_OFFSET 0x4 =20 @@ -62,6 +70,12 @@ #define CONDITION_DECODE_STEP(step, decode) \ (CONDITION_DECODE_OFFSET + REG_OFFSET * decode + STEP_OFFSET * step) =20 +#define TIMER_COMPARE_STEP(step, timer) \ + (TIMER_START_OFFSET + REG_OFFSET * timer + STEP_OFFSET * step) + +#define COUNTER_COMPARE_STEP(step, counter) \ + (COUNTER_START_OFFSET + REG_OFFSET * counter + STEP_OFFSET * step) + #define CONDITION_SELECT_STEP(step, select) \ (CONDITION_SELECT_OFFSET + REG_OFFSET * select + STEP_OFFSET * step) =20 @@ -83,6 +97,12 @@ #define STEP_SELECT(step_index, reg_num) \ tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_SELECT, reg_num) =20 +#define STEP_TIMER(step_index, reg_num) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_TIMER, reg_num) + +#define STEP_COUNTER(step_index, reg_num) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_COUNTER, reg_num) + #define STEP_PRIORITY_LIST(step_index, priority) \ {STEP_PRIORITY(step_index, 0, priority), \ STEP_PRIORITY(step_index, 1, priority), \ @@ -122,6 +142,18 @@ NULL \ } =20 +#define STEP_TIMER_LIST(n) \ + {STEP_TIMER(n, 0), \ + STEP_TIMER(n, 1), \ + NULL \ + } + +#define STEP_COUNTER_LIST(n) \ + {STEP_COUNTER(n, 0), \ + STEP_COUNTER(n, 1), \ + NULL \ + } + #define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\ (&(const struct attribute_group){\ .attrs =3D (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\ @@ -143,6 +175,20 @@ .name =3D "step" #step "_condition_select" \ }) =20 +#define TIMER_ATTRIBUTE_GROUP_INIT(step)\ + (&(const struct attribute_group){\ + .attrs =3D (struct attribute*[])STEP_TIMER_LIST(step),\ + .is_visible =3D tgu_node_visible,\ + .name =3D "step" #step "_timer" \ + }) + +#define COUNTER_ATTRIBUTE_GROUP_INIT(step)\ + (&(const struct attribute_group){\ + .attrs =3D (struct attribute*[])STEP_COUNTER_LIST(step),\ + .is_visible =3D tgu_node_visible,\ + .name =3D "step" #step "_counter" \ + }) + enum operation_index { TGU_PRIORITY0, TGU_PRIORITY1, @@ -150,6 +196,8 @@ enum operation_index { TGU_PRIORITY3, TGU_CONDITION_DECODE, TGU_CONDITION_SELECT, + TGU_TIMER, + TGU_COUNTER }; =20 /* Maximum priority that TGU supports */ @@ -166,6 +214,8 @@ struct value_table { unsigned int *priority; unsigned int *condition_decode; unsigned int *condition_select; + unsigned int *timer; + unsigned int *counter; }; =20 static inline void TGU_LOCK(void __iomem *addr) @@ -197,6 +247,8 @@ static inline void TGU_UNLOCK(void __iomem *addr) * @max_step: Maximum step size * @max_condition_decode: Maximum number of condition_decode * @max_condition_select: Maximum number of condition_select + * @max_timer: Maximum number of timers + * @max_counter: Maximum number of counters * * This structure defines the data associated with a TGU device, * including its base address, device pointers, clock, spinlock for @@ -213,6 +265,8 @@ struct tgu_drvdata { int max_step; int max_condition_decode; int max_condition_select; + int max_timer; + int max_counter; }; =20 #endif --=20 2.34.1 From nobody Sun Feb 8 19:56:19 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76EE827F75F for ; Fri, 9 Jan 2026 02:12:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767924751; cv=none; b=P+Np9PAsXlykjXeKO3c3u7+AWJ3zyYjfHDpak7v1xsaOquZdj77dAfs1g5HEalk8ov9Sdoi1W3g3uGHefgybxHFfbVXFKqICAAjlJafTpoTPMqLtK0CmBte2YN5W6bfpGxDyKrnX5DHnyUTgbgyANNmGBtN+Khw14+bVvFJWBKc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767924751; c=relaxed/simple; bh=BgfnQBt4eis79ePg7a9KA9sFWLA0Wf6CSKp55vnkyls=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=E84BiitMx8NX8ioz/aoGOm5jotE0P8EYv+zFtYcTGnZcS7BTcNh/ZoxQyebprpQOrCt2Vm0HddUQGvvnqdHwkAD/NUhRYFTLEJ0un9cXEiQ8MyIYO3LRUzh2P20KEIlq46wVBHfVYS4WkbkktDhwaT1WVavFlippqgpCKXoP1VE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=XRopE8hu; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Sja5EaqA; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="XRopE8hu"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Sja5EaqA" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 608Hk4Pw408435 for ; Fri, 9 Jan 2026 02:12:22 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=UNj9IldgTww Hcf0TlwaBwN96Jq68NG1f1miPWfIzHS0=; b=XRopE8huQ2mmSOHitPHwYKEPGIx uz7XH0kJd7/L7BH95n0PlXPjHq8ARD16uLC58gAfdXrvm5nseWKm+9HwSPSRwi53 DBwQeEs7UgL2UwngiurCUvXdXeSAtrMttDl0wmR8v/u3zA6HAnoHnRQnC/RNa4Y1 vEM8h8ggVHS4lrzWtilo8baMZ1amESQb1AM/RdrNrzoMvTTF+mCOsWCqFJMiLyDp evltOXvpSwy92JX/mE1yFCPQU15wTnJ6twIQEkuAeZfW/PCq4JuWzP8J9Wqhl20m dS0NKMn1p+4pHHHJLPpPaZnAh5pLlxEJakS0qDuBE+4RAEoN5CwGvJx9jWg== Received: from mail-dy1-f197.google.com (mail-dy1-f197.google.com [74.125.82.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bjb39tht6-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 09 Jan 2026 02:12:22 +0000 (GMT) Received: by mail-dy1-f197.google.com with SMTP id 5a478bee46e88-2ae6ef97ac5so10626572eec.1 for ; Thu, 08 Jan 2026 18:12:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1767924742; x=1768529542; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UNj9IldgTwwHcf0TlwaBwN96Jq68NG1f1miPWfIzHS0=; b=Sja5EaqAtfkb9wloTP7aBK39Rqy73AqKzaht9IGhf6m1KkB/ONIqKZEU62MFYPZ+wm snd67ivc+Ei+ZZj5FgRSXha+jNEu4/HfffPc1XT3c0qlU9P6GMnVgtSPY9YMjygXtGxJ rU7ALV1LKEkDrlShkPu8EaOCLhh6LKcpic0ZMKlULL/7pmhDpJpydqgTyKVwxKNFlWBx pRN+hhLPPb/iOasDo1Rkrdx4er59SWOEtt/6gjrmbD2Ai52a8iDZqkABktt+aZUOQq6O V8Kn3CEewKvjYaDncNknuIjwEPMU7H8RvMCL0B9HzPtdqmkDG8NsnXiTx791Pf1Akx70 3wCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767924742; x=1768529542; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=UNj9IldgTwwHcf0TlwaBwN96Jq68NG1f1miPWfIzHS0=; b=NAQo7Ynw5XIC8W2rYR4eL8sNLlk/grLmX4P6ToX7ihgiE1E2w7+/YjHDyMg6huPMQF 4V3GM2JDGX1LPFWlP/ECVyK75hvhSAWH/XQ6kDbAmRqeUa11oJykuJoNZGTH9rFKXaq7 tk5abEDa+gKb3b5HCXKeX3Dbe4VkE6BBM0LsiglKzpFnHugJiRDflqG1Vmstr19/stey NJeTYmgP8X/xUl53IMaxje6xMUn9p/xh2/GYMBBZxsVhAK5g944W0af9M1WvtoHXAS+R zZIfjEXOMGyiiaJhMZ1MStCdf28i6ixD/DYNgtPqtc0Y5BuwzFjVPCYwTEsl37eahuWR 8Czg== X-Forwarded-Encrypted: i=1; AJvYcCWM7Z/LgNaDnmZuuZklAUAN2LjRX4ScEOolsqU0h10l2i5DJPbmHKSxG96ai7X0AOWikEY5UoUgnWt/nyA=@vger.kernel.org X-Gm-Message-State: AOJu0Yx9i1maAffQPjwW4xclchFLTYF8iP7myVZFhNJcxvic5tA8R/8k tJdVA0QUBGqebG+/pDb0rH2Gj9TRMXO+Zv66m2p9hts0W9Lc8IFaoqkONWphAKhQzh3ksL37xqw 9hZO1fswMxq7+2RkU2+UafBk90mbTd9UBfuIrQV6HOWYNosKgm0LYgqhlwvdLgC1NPrs= X-Gm-Gg: AY/fxX6P5Nf3THidkCWEfdSXMxwJqE+6Hh9AetrGx+v9mIVpo8plM1vED5nKZTEQJIu qQFtgYCI6M0GceVaX2CPLj4wsSG7OwrvWFcFA/jQ+iuD1FeC9AjYQClPM146nQQ0hFOzsg68vZ7 6IGKIQk8KEthU25qIQbt3qWEusYw//x8eJ25qwbAe4Dnb1EE8eSvyDef5qKk0ICoEhf6pC6Ll6q FBn6qAw6p59fgiKDznyIAXqEw45hFRdCFQIcZ7afKnRbXoYn556MNbTYG64HAdrkl1q3qav1Ne0 QMG4sZv6SEuxmr8zGsxlT/kVYvoar7YrZ10LUZcqtdXiFXSSepIoYCKzWJ7kN5XQAVoyQYLZl+M DfWUjwUkrlwq/AcUWXElfqwAIjhgJY268mP+evT4E39IbXFBcCPS2kpNlHOopK+a9 X-Received: by 2002:a05:7301:5387:b0:2b0:5c02:7516 with SMTP id 5a478bee46e88-2b17d24d19amr5467606eec.15.1767924741880; Thu, 08 Jan 2026 18:12:21 -0800 (PST) X-Google-Smtp-Source: AGHT+IHQfTti3+ws20Sqrv0AXLPG8dqfyhqRGOTHJYP7pS9+6hYpKG5AapDxym6UcH2zDfuYgG6C+Q== X-Received: by 2002:a05:7301:5387:b0:2b0:5c02:7516 with SMTP id 5a478bee46e88-2b17d24d19amr5467591eec.15.1767924741341; Thu, 08 Jan 2026 18:12:21 -0800 (PST) Received: from hu-songchai-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b1707d76aasm9459111eec.33.2026.01.08.18.12.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 18:12:20 -0800 (PST) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, mike.leach@linaro.org, suzuki.poulose@arm.com, james.clark@arm.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org, gregkh@linuxfoundation.org Subject: [PATCH v10 7/7] qcom-tgu: Add reset node to initialize Date: Thu, 8 Jan 2026 18:11:41 -0800 Message-Id: <20260109021141.3778421-8-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260109021141.3778421-1-songwei.chai@oss.qualcomm.com> References: <20260109021141.3778421-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: MzUS0XOc4aaiEf66C8xlS3kYBwOD5oYC X-Authority-Analysis: v=2.4 cv=X7Jf6WTe c=1 sm=1 tr=0 ts=69606406 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=IgPCHI2mAnvcCQI4J_AA:9 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA5MDAxMiBTYWx0ZWRfX5q5hF+jGMjbD NWSDkEJds02DggQlP9qArbTNjihOOPZpK1qKMPXcZlMCfwzJTW9D3KxgdxzCODMU9xkUc5YdBlg hqZv2uDO0f77P962/gkGCJQd1IqzEUMzsS/Js6aXLXIsGELNsHvWyIYjFqZFXdOBEM2oBALE4jK 6rS49YF0W4LAKUXhjtsTkg05ZT8ZAieNPKvcZNRoSzWhoGJ12zq/StBt5B3XWw7fLr0B4XH2yGK Rsv3NXPZ/3XrMLCknQSANcfl5FNR26lEDOZEHvWY3P/quyqWEzUbJ46z2vZAty8e7SHSGH/pKDy WhXUbe7dqEqT9/1YwV+Fg49LFlVEYNdYm8SidAJZOd6wQIsBgg+8XM0nN7J2bNQML8kBhH9CvAO 6frpkEC4uij5tn51kH5jgK8/IHqH6wMygf6LpJDvC5wxRqMIPkSk3ZzH5JyUG7TRd1bxhzslIbb B4R1eOl6A0FLiNo4wYA== X-Proofpoint-ORIG-GUID: MzUS0XOc4aaiEf66C8xlS3kYBwOD5oYC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-09_01,2026-01-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 bulkscore=0 suspectscore=0 phishscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601090012 Content-Type: text/plain; charset="utf-8" Add reset node to initialize the value of priority/condition_decode/condition_select/timer/counter nodes. Signed-off-by: Songwei Chai --- .../ABI/testing/sysfs-bus-amba-devices-tgu | 7 ++ drivers/hwtracing/qcom/tgu.c | 74 +++++++++++++++++++ 2 files changed, 81 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documen= tation/ABI/testing/sysfs-bus-amba-devices-tgu index 61b5a08bdee1..fa2618b31ab9 100644 --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu @@ -42,3 +42,10 @@ KernelVersion 6.19 Contact: Jinlong Mao , Songwei Chai Description: (RW) Set/Get the counter value with specific step for TGU. + +What: /sys/bus/amba/devices//reset_tgu +Date: January 2026 +KernelVersion 6.19 +Contact: Jinlong Mao , Songwei Chai +Description: + (Write) Write 1 to reset the dataset for TGU. diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c index a3d9c3c4e28a..0a45ff78858b 100644 --- a/drivers/hwtracing/qcom/tgu.c +++ b/drivers/hwtracing/qcom/tgu.c @@ -424,8 +424,82 @@ static ssize_t enable_tgu_store(struct device *dev, } static DEVICE_ATTR_RW(enable_tgu); =20 +/* reset_tgu_store - Reset Trace and Gating Unit (TGU) configuration. */ +static ssize_t reset_tgu_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t size) +{ + struct tgu_drvdata *drvdata =3D dev_get_drvdata(dev); + unsigned long value; + int i, j, ret; + + if (kstrtoul(buf, 0, &value) || value =3D=3D 0) + return -EINVAL; + + if (!drvdata->enable) { + ret =3D pm_runtime_get_sync(drvdata->dev); + if (ret < 0) { + pm_runtime_put(drvdata->dev); + return ret; + } + } + + guard(spinlock)(&drvdata->lock); + TGU_UNLOCK(drvdata->base); + + writel(0, drvdata->base + TGU_CONTROL); + + TGU_LOCK(drvdata->base); + + if (drvdata->value_table->priority) + memset(drvdata->value_table->priority, 0, + MAX_PRIORITY * drvdata->max_step * + drvdata->max_reg * sizeof(unsigned int)); + + if (drvdata->value_table->condition_decode) + memset(drvdata->value_table->condition_decode, 0, + drvdata->max_condition_decode * drvdata->max_step * + sizeof(unsigned int)); + + /* Initialize all condition registers to NOT(value=3D0x1000000) */ + for (i =3D 0; i < drvdata->max_step; i++) { + for (j =3D 0; j < drvdata->max_condition_decode; j++) { + drvdata->value_table + ->condition_decode[calculate_array_location( + drvdata, i, TGU_CONDITION_DECODE, j)] =3D + 0x1000000; + } + } + + if (drvdata->value_table->condition_select) + memset(drvdata->value_table->condition_select, 0, + drvdata->max_condition_select * drvdata->max_step * + sizeof(unsigned int)); + + if (drvdata->value_table->timer) + memset(drvdata->value_table->timer, 0, + (drvdata->max_step) * + (drvdata->max_timer) * + sizeof(unsigned int)); + + if (drvdata->value_table->counter) + memset(drvdata->value_table->counter, 0, + (drvdata->max_step) * + (drvdata->max_counter) * + sizeof(unsigned int)); + + dev_dbg(dev, "Qualcomm-TGU reset complete\n"); + + drvdata->enable =3D false; + pm_runtime_put(drvdata->dev); + + return size; +} +static DEVICE_ATTR_WO(reset_tgu); + static struct attribute *tgu_common_attrs[] =3D { &dev_attr_enable_tgu.attr, + &dev_attr_reset_tgu.attr, NULL, }; =20 --=20 2.34.1