From nobody Tue Feb 10 01:34:51 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE34B366DAE for ; Fri, 9 Jan 2026 17:18:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979123; cv=none; b=bX0gc4x+VCDWSNehH3nCHe9D0kIJgZcAVE1ZQkMbznCmuG1JXY6lSe02SLnsARIUMibUbum1XQrOLc9I8SjPtUFb4hRarK0JGKwaelDlm+uYpU2fonhbG0yMZ8dprDsRJf1/c4hfnT6sJnJNa8x1TPaodRlYAYoN5riJVsUBuGw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979123; c=relaxed/simple; bh=C9hwsEV3wdatwD062DI30KDF+447ewMTinjMJ6/pCpk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pigziUxtorgnGG1gvCfS9ifBzO5Tbpvvl6cOlcZJ5D1rtLIlEA7nZSgCuLWXRt61/XVssT7v9mpycba5Bx76a5Wb1omC1i0uLH3xTT6Zx9Pb8DbCZPTXA5jJo4ANzzvubMIcqdGPu2dlASXoLyDcfWD+ETzlM9vLC0LTOjykIVw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=UdsMaNco; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="UdsMaNco" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id E1D741A2755; Fri, 9 Jan 2026 17:18:34 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id B1DD6606C6; Fri, 9 Jan 2026 17:18:34 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 2A784103C89B6; Fri, 9 Jan 2026 18:18:33 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767979114; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=ByaYUaNaJV4Ff78T5l6xTtVf1Fq+ywBCL3Mu7MTdSkQ=; b=UdsMaNcoXXLblizSSEA94E3C9P1gYOwOG3Vz5eSmiqJHjG5wg6BwLbw8AesjWv6FfCZVdy MJWXpNP5Y2g1QFUXsAOKSy81FE+msf1OCh1zcmjrOBTC6p5EuO8i9z5T7SwzQ8Qotnre56 DkwcD5Uql3fcEqo9TV9KN9IC+68+4whP6QJw+XRHDijyQxyLKFjSO8BdnHf34tn1ZEadJi Loj5px3PcU+6lDYLHlzIEqqdZz423KFusUKE7TeNS/SseFaydMgk2PttoEXKB73M8X/E7r nBWITkh/C0maqJiWF9GauvknVG5/lFc7iJBRbASjgrn5fCCSEb7hBLwVAMnyDA== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:11 +0100 Subject: [PATCH v2 13/27] mtd: spinand: winbond: Convert W35N specific operation to SPINAND_OP() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-13-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Winbond W35N* chips require a vendor specific operation to write their VCR register (a configuration register, typically used for tuning the number of dummy cycles and switching to a different bus interface). Instead of defining this op only in the function that needs it, hiding it from the core, make it a proper define like all other spi-mem operations, and implement the necessary spinand_fill_*_op() helper to make the SPINAND_OP() macro work. This way we can use it from any function without any extra handling outside of this helper when we will convert the core to support octal DDR busses. Reviewed-by: Tudor Ambarus Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/winbond.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index dde59f8f63f5..3003ad7e83ee 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -87,6 +87,18 @@ static SPINAND_OP_VARIANTS(update_cache_variants, SPINAND_PROG_LOAD_1S_1S_4S_OP(false, 0, NULL, 0), SPINAND_PROG_LOAD_1S_1S_1S_OP(false, 0, NULL, 0)); =20 +#define SPINAND_WINBOND_WRITE_VCR_1S_1S_1S(reg, buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x81, 1), \ + SPI_MEM_OP_ADDR(3, reg, 1), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(1, buf, 1)) + +static struct spi_mem_op +spinand_fill_winbond_write_vcr_op(struct spinand_device *spinand, u8 reg, = void *valptr) +{ + return (struct spi_mem_op)SPINAND_WINBOND_WRITE_VCR_1S_1S_1S(reg, valptr); +} + #define SPINAND_WINBOND_SELECT_TARGET_1S_0_1S(buf) \ SPI_MEM_OP(SPI_MEM_OP_CMD(0xc2, 1), \ SPI_MEM_OP_NO_ADDR, \ @@ -329,11 +341,8 @@ static int w25n0xjw_hs_cfg(struct spinand_device *spin= and) =20 static int w35n0xjw_write_vcr(struct spinand_device *spinand, u8 reg, u8 v= al) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(0x81, 1), - SPI_MEM_OP_ADDR(3, reg, 1), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, spinand->scratchbuf, 1)); + struct spi_mem_op op =3D SPINAND_OP(spinand, winbond_write_vcr, + reg, spinand->scratchbuf); int ret; =20 *spinand->scratchbuf =3D val; --=20 2.51.1