From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE620365A11; Fri, 9 Jan 2026 17:18:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979105; cv=none; b=DnE116wBsT5hEdU/gI34IV7LDxfFZEfluGLFQCKRhmeFu8IwdSifqAs3KsU6TK1k1r/oC0e3Is4jWPX2C/WZzX6G2A9wjOA5NoD7XDvRXNbFh6tpMDw+KCMCajZdahidO0i1/zApJHXINa2pUfDnV7wyWMEX8oMPUFpTWSC6cyg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979105; c=relaxed/simple; bh=0sln/3oAuwBPrchoQttcANFqFqWVGEF9tBH4dh5X15o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eUWKe80EfvF7vRSJDTL+c2cvewVXQ08xpTW7p0abnwGOWebEWI5rSAR48FfV6huhOk2m+1TH0WBmOy7oThEvvisvfcDdjX7vLTu1zC5yzYjvseNo1x2B4FNRrx5E+W3IQNDiYo/rgzuQLKz1ApujfIbgWKBZsdiUkfIxvtlwzhE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=kZLAZdgI; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="kZLAZdgI" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 84F241A2752; Fri, 9 Jan 2026 17:18:20 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 5C00C606C6; Fri, 9 Jan 2026 17:18:20 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 8D19C103C89AB; Fri, 9 Jan 2026 18:18:18 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767979099; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=9G/aUTnLmrJx/EKe3AC5h2XyiwOQM2CjA2RNxNPKj0U=; b=kZLAZdgIAwwqf4/dpch+VvSRsdxmzJOwoZw/n74dUBbuRHzqQq73AtLYqXxZE9RWElkG7z cuEmfLJs6HB1OxVZEY8Tgt0+XOgyEXW5KYVpWL4f4jlkZhX3NGcjiKzAeb/EUU6s9qK/LZ WKF+QYKqvk8puaW2J9zUrTfEQVjLGqL+XVtKlQWaaowwTeb2+RJELxICAvojzDrIrwvYpc 1TC1MyITJv0iQyQ2i67SJGKf4YJ+mW8L04IckabagghPW3cIkJ0TzY3ynAhkbPc5Q2rk5B CPzye2lc21wnp3qd8G1GwwpiJyeiXsyTiFB3p4dnndZ3QA4LepsrzCSwKvQdWQ== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:17:59 +0100 Subject: [PATCH v2 01/27] spi: spi-mem: Make the DTR command operation macro more suitable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-1-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 In order to introduce DTR support in SPI NAND, a number of macros had to be created in the spi-mem layer. One of them remained unused at this point, SPI_MEM_DTR_OP_CMD. Being in the process of introducing octal DTR support now, experience shows that as-is the macro is not useful. In order to be really useful in octal DTR mode, the command opcode (one byte) must always be transmitted on the 8 data lines on both the rising and falling edge of the clock. Align the macro with the real needs by duplicating the opcode in the buffer and doubling its size. Reviewed-by: Tudor Ambarus Signed-off-by: Miquel Raynal --- include/linux/spi/spi-mem.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index 82390712794c..81c9c7e793b6 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -20,10 +20,10 @@ .opcode =3D __opcode, \ } =20 -#define SPI_MEM_DTR_OP_CMD(__opcode, __buswidth) \ +#define SPI_MEM_DTR_OP_RPT_CMD(__opcode, __buswidth) \ { \ - .nbytes =3D 1, \ - .opcode =3D __opcode, \ + .nbytes =3D 2, \ + .opcode =3D __opcode | __opcode << 8, \ .buswidth =3D __buswidth, \ .dtr =3D true, \ } --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F720366565 for ; Fri, 9 Jan 2026 17:18:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979105; cv=none; b=bLiqKoXLQRp02/6y5tj1BVSjWPRKsZCXsI9+A8Q9PRXahLLtkCcqGDJ4ApRCv6oDHUInJUdcsU7FI+e5YbgALVP76pOrsagawXF3M7nInG1uRAEw/aH3Vwrkfah4wgXiFsN6YGjEkwjWgnefaKDb03VFhbafbUvqeY7rbQH5cmI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979105; c=relaxed/simple; bh=L+WFaZEg4oo76+avTtmBhbTWOBzmGBPkcF+3yacI8mI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WFkvE6GxlspZr+7CUbc172Wy9iXotyLsLTncYI4KU9yz4VPqz/iKOztR8H3mvN79MF8rLTuRYXBjzwgIzv+3KtimVqHwjsOKBj/bHY/Bs/KhuJWiJDppPtTm4p4O+Cuj/lM6oHtIpFltVNDelLSD1lygh1FEBSTvwbBa2E0zo/I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=fZkuhbyn; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="fZkuhbyn" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 4FB80C1F6E6; Fri, 9 Jan 2026 17:17:55 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 988A9606C6; Fri, 9 Jan 2026 17:18:21 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 06108103C89AD; Fri, 9 Jan 2026 18:18:19 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767979100; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=TdRhJU2g1aCtWJB6jVyDXMoLZUtYtJ3QCG7nSo0yd9g=; b=fZkuhbynJrZvzxDpARwKOTLI3aT3fjUyhlxHsZ06G115O4FLa1GKpHCfaXHScGSyaI9wck aLA61q9c2slPTNSddPoe8ODdLC4Oen3wdse/fMEAArrNSDuJxV5YUdpRCoZ5C2n6h7oVzQ KEEJCox7EXLcRnorC/jUkUeFyFZ9lAOO/NFTSdfEvg0Zb3YncDOEjtAU4mqd8OL5lC+pvT NuaIM87WIJwreaivgtDkddUZK9ACL4LaUo5JF5j6d7sqX2SZKNHoOCJN2oIrmcRzpU+DRB 5wW/hjSx3j4YNEo4JLAUmfWHwPOHF6lAAfB7k0UzYkzbGXUe9BWHBS2AyjKveg== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:00 +0100 Subject: [PATCH v2 02/27] spi: spi-mem: Create a repeated address operation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-2-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 In octal DTR mode addresses may either be long enough to cover at least two bytes (in which case the existing macro works), or otherwise for single byte addresses, the byte must also be duplicated and sent twice: on each front of the clock. Create a macro for this common case. Signed-off-by: Miquel Raynal --- include/linux/spi/spi-mem.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index 81c9c7e793b6..e4db0924898c 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -43,6 +43,14 @@ .dtr =3D true, \ } =20 +#define SPI_MEM_DTR_OP_RPT_ADDR(__val, __buswidth) \ + { \ + .nbytes =3D 2, \ + .val =3D __val | __val << 8, \ + .buswidth =3D __buswidth, \ + .dtr =3D true, \ + } + #define SPI_MEM_OP_NO_ADDR { } =20 #define SPI_MEM_OP_DUMMY(__nbytes, __buswidth) \ --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A824363C7D for ; Fri, 9 Jan 2026 17:18:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979106; cv=none; b=uoosTQKwFBvDJOM7Oxlxr4w07po08VQ/4ShQ8fThmFzzVJf3Q6rUSw8KjAY81KBrWfeeeKrwsVsTx6/CJUD6bPbiztP0M1wJA6mdBYfEFNXBahMjWprsiVyB1ilQt2Zk4dHBZZXnwqt/xLHz4HanB837Kvh+TcraI1Einl6DgeM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979106; c=relaxed/simple; bh=Vcy/12KBDerD4lsZZ0OCPmONKW4YxSkzB+GIyt5FonY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sLuZlzqSwX2oLvcO8MIL49AWrqgvueHOCb3jBs46Wy3ueWG7vRj+BKRzf8Zf1NtSmRGnDEL4GOHuJP/4XiP0cojrUpzrSdolhzqY3iEb7Cq2L6wcSydQU9zzes57AZsXD6gMLmdGUhVZ8QMfRuB0Kkj2r6oaWMvFfjnKW+qw7aQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=rt6j6ZvB; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="rt6j6ZvB" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 95136C1F6E7; Fri, 9 Jan 2026 17:17:56 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id DEDC8606C6; Fri, 9 Jan 2026 17:18:22 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 31395103C89AF; Fri, 9 Jan 2026 18:18:21 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767979102; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=hpWiGp2IJhYFgxmfj56BPtbUVs0Zl/pSRbFJbsG8PAQ=; b=rt6j6ZvB+gVvtkjvT5b/qqqXMMtTMJ4no6KRPrg1z7A7g8TY9U3T9os07NoQaiH2IhQm5i lPKkvlAjD7ltT/lsLFyAUy3d1F9faa21ajqVuB0rNUr2AfvZjzfRGKu+CUoZqhqSyvcFUi ghhPFrH3emnkB39qO6dC2BqStYVXb2GYomhEu1UPQVkzxyAXyCV9KgLlNOhecjsCtoqqNJ gFAgodyruiT+Hiyy6lNvj04pXH/hP4SykA2w0Dk6U51N8gj1yawctATkcPIL3kMJQYVdD5 mtC8yG7L9zEUIIFKPSZ0wmY25+gvFIcolbtpLtsJ4siA7tRGyUSR1ivTjc8JaA== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:01 +0100 Subject: [PATCH v2 03/27] spi: spi-mem: Limit octal DTR constraints to octal DTR situations Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-3-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 In this helper, any operation with a single DTR cycle (like 1S-1S-8D) is considered requiring a duplicated command opcode. This is wrong as this constraint only applies to octal DTR operations (8D-8D-8D). Narrow the application of this constraint to the concerned bus interface. Note: none of the possible XD-XD-XD pattern, with X being one of {1, 2, 4} would benefit from this check either as there is only in octal DTR mode that a single clock edge would be enough to transmit the full opcode. Make sure the constraint of expecting two bytes for the command is applied to the relevant bus interface. Reviewed-by: Tudor Ambarus Signed-off-by: Miquel Raynal --- drivers/spi/spi-mem.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index c8b2add2640e..6c7921469b90 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -178,8 +178,19 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, if (op->data.swap16 && !spi_mem_controller_is_capable(ctlr, swap16)) return false; =20 - if (op->cmd.nbytes !=3D 2) - return false; + /* Extra 8D-8D-8D limitations */ + if (op->cmd.dtr && op->cmd.buswidth =3D=3D 8) { + if (op->cmd.nbytes !=3D 2) + return false; + + if ((op->addr.nbytes % 2) || + (op->dummy.nbytes % 2) || + (op->data.nbytes % 2)) { + dev_err(&ctlr->dev, + "Even byte numbers not allowed in octal DTR operations\n"); + return false; + } + } } else { if (op->cmd.nbytes !=3D 1) return false; --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A720C36657B; Fri, 9 Jan 2026 17:18:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979107; cv=none; b=C7ZjrRZWUSqFWC6UnwP28EsnpYRVCOAUzxiximAMtIWtjh3kyPWDxFpywEvySrS+LJ+jFgawt/AcDVCr3y9d5DaSUBGkJThqdAqJhT0TVQ6e9WuzUU97SpkWlql5F+G2FKKpRCrwYDZwFfN9y25vre467uzf46zak6OOZTjGAiw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979107; c=relaxed/simple; bh=eEC1htR5mO8DAeWFHvr4zf41GPHnAH75KSWAsNDMHoU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kiUAf7HEXkj7OaGTwwkst5ubESNi41Ck5tzeNVqUx+wbaLcqBuZcTRjJVToSw5PdLDjnWck4gojTMT6aWX/e0AIFqiZBSdPN4nDBcgO665FmJ3mVQH0ne+wZxl/aL/vPDEbawNwYW6I6rFMoCtIxnMaKCdncXkcpyqXmIvYCnos= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=nHAa5EOE; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="nHAa5EOE" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 5CA094E42027; Fri, 9 Jan 2026 17:18:24 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 2D26F606C6; Fri, 9 Jan 2026 17:18:24 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 82F87103C89AB; Fri, 9 Jan 2026 18:18:22 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767979103; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=XlR+uDRIZQQiUnMwB6JtAAy6JempSPfArezroNR9cWY=; b=nHAa5EOEVMqlzmMHeNj4UzlNVt1C+N8UH6t0j0exFoQZHiSVrYFoPEtvBhpw8zR03kDnRT 0XM8C+gSY2zr3jUzjXh6b4VrrUzvg47sZe6MBTDQ/Dfx6wlDCNo9GUGzBb2thYOM+5o6Df 3WVtXwy/NR0pK+3vVja72N8NLE90CBk3g+mVoYNpZBRWxuPAGWOvc24wvP9TaMj0RVBltX 0aekYJ0/e3wBeMFNZvE9oF/YZKkTYuakwri/uYZzIGVqDARnsB9MKnSzSJZzp43GSA+TQ7 rDp/lsHO1U8hXBI0WLKKM0iOlCREZlV0BlC5GSLVdCLcfOAxDvdmBc7Vd2wRUA== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:02 +0100 Subject: [PATCH v2 04/27] mtd: spinand: Fix kernel doc Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-4-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The @data buffer is 5 bytes, not 4, it has been extended for the need of devices with an extra ID bytes. Fixes: 34a956739d29 ("mtd: spinand: Add support for 5-byte IDs") Reviewed-by: Tudor Ambarus Signed-off-by: Miquel Raynal --- include/linux/mtd/spinand.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index ce76f5c632e1..049d55c38d52 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -287,7 +287,7 @@ struct spinand_device; =20 /** * struct spinand_id - SPI NAND id structure - * @data: buffer containing the id bytes. Currently 4 bytes large, but can + * @data: buffer containing the id bytes. Currently 5 bytes large, but can * be extended if required * @len: ID length */ --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB729366DD3 for ; Fri, 9 Jan 2026 17:18:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979108; cv=none; b=XT03PwgXAoJV03Vse5u2JKgpeiOlTrolwV7zCg7+VqOVrSqALrIeNKzrsJlVTvWsckItYA+DkCDIAJGbtRxl00MA8prCGfbIngSuSRTytQ+Mk8TV1Tlgu/xX2jWLsWBngH2q6TiOXZ/speCrBCTw2F+jpmskbGv/4g+22/uwIVQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979108; c=relaxed/simple; bh=IJQIQ1qPwnyGsodqhdDYlPN0s9/YWzU7C+O/2+1S0xM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aY2OyVhDN0ray/HFj6u2owvf24ov1YbAzI+l085umNb/19Lc01dEXe8RAI4gSNev69ceUNWn2fAzdokhjvp+gC6s5y9qHh/WlOhH05hsMfjAyR9WiLjQmSerHe1FGfQdNo7RyIH9egBW0T9NVicATEAJe8Wc6gmdMbibdRlxkMU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=wVJ+MX0p; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="wVJ+MX0p" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 1D020C1F6E9; Fri, 9 Jan 2026 17:17:59 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 64C0A606C6; Fri, 9 Jan 2026 17:18:25 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id B60D9103C89AD; Fri, 9 Jan 2026 18:18:23 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767979104; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=v22HJHx8//qB5/a5Mqzhu2mFFylXUtBtPnkP97yMpsw=; b=wVJ+MX0pEoXe/7NLlNWUtxxBoI/lzU9mojd2jzQG93nDEXa3RsmSGhB2bptt7G/SnTRLBZ 4fVO/5/czzugN6vkX+kUET3HUqmF7ItOAUTQCFXdFN23Fvu+caG/fpIpu9+D7N1tKjLayU aygZjlNhJmmDNDdS0lfgK/tGMdWbBrUBmZJr2ecHtKLAOGYkY6BcZZFvbiRrLsfFBFHn46 Nk1ZS8cYeFI8tW4tkX6/4m7X0O4FV3mdBenwQeSlCBOKAjNkbzAZA1KuWVAOhaCuh2E3TC v+4o/eg0J7/n3tVsTOWbLFUwp4Ec+6vRljUCyKTi43fewgVX+rLrkF8QsmWjKQ== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:03 +0100 Subject: [PATCH v2 05/27] mtd: spinand: Add missing check Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-5-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The update cache variant is mandatory, both read and write versions are being checked, but not this one. All chip drivers seem to implement this variant, so there should be no breakage. Reviewed-by: Tudor Ambarus Signed-off-by: Miquel Raynal --- The core has been like that since the begining, I do not think this patch should be backported, hence no Fixes tag. This barely qualifies as a fix anyway. --- drivers/mtd/nand/spi/core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 62447801abb1..8acea0372f21 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1432,6 +1432,9 @@ int spinand_match_and_init(struct spinand_device *spi= nand, =20 op =3D spinand_select_op_variant(spinand, info->op_variants.update_cache); + if (!op) + return -ENOTSUPP; + spinand->op_templates.update_cache =3D op; =20 return 0; --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B49D330149F; Fri, 9 Jan 2026 17:18:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979114; cv=none; b=FoAkV+SS5iH+TgtnZqSol72sVMoEfNQFeCE5uD1TcundnacNukkgTqHgi4G39wklzCOmryuPLYuA1PKRzmD+vEtjQwH4QIZEhfcuLssI8NFx/pnlx+Q/YQLGfqE4yg71kDoqUJh1/6hNLvQuRja1x94tlplkS7ps0yfAWnDcXjQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979114; c=relaxed/simple; bh=t2/eAaKJ9Xy8Li8YXfUEutFre1NJlcHvaAFMV0Kgiuo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fB0Dh0ROF46fxTlrSY7hVuhLjMC7Q6I8y1pnxeF0Fg0bM5lfQdPGWMlTKyN4D2NQ8XxT6PlV8Nh4vUebA1JlLrTH76y8GLaK1DDxPPFCnQMeHq1l0j8azdcyfQOaSppWF15/csX4XahQqVEY9QDcgbkNftJs6ITK+djaKG88HEE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=l4DhprWE; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="l4DhprWE" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 21635C1F6E4; Fri, 9 Jan 2026 17:18:00 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 6A94F606C6; Fri, 9 Jan 2026 17:18:26 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id E2028103C8956; Fri, 9 Jan 2026 18:18:24 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767979105; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=Ba70zlYcbz8QlJI8mSBGaiXcm4X/itTgn1V4VCKgo+E=; b=l4DhprWEs5zbKkrQZO+XkLm+NE+5V/RcLPIos0dLXX01VbFKN3IP/Ou8JbsNWVZ6tb/Tzo VwUeIRl6DaaNK6kH+bR6imsyI2XRXfADra4GhO29uRY4Lc7hfA1CnmvuB/uRz8AEN+JjUw ErTL8HMqvUTi2fAs0c6G2jjIPFfU+yLDoqh8nSRbdIcHGnffpScPTVduslqBfVMdV3bJoo s+PkqQyLIowQ5fgqwL//6Ng6yfoWktMK0gmrI/HRYSZV9aFIddGtzXq2frc6yk1SrY1IXP pFfYpJE+/M9A6jAFeICx2qynl2KrXmZS01+Q81XpmMnrD9WJv0KxBheGxOkeTA== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:04 +0100 Subject: [PATCH v2 06/27] mtd: spinand: Remove stale definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-6-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 SPI NAND command values are directly included in the macros defining the ops. These are stale definitions, they are unused so drop them. Reviewed-by: Tudor Ambarus Signed-off-by: Miquel Raynal --- include/linux/mtd/spinand.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 049d55c38d52..ad2773f1f963 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -232,12 +232,6 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_OUT(len, buf, 8)) =20 -/** - * Standard SPI NAND flash commands - */ -#define SPINAND_CMD_PROG_LOAD_X4 0x32 -#define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4 0x34 - /* feature register */ #define REG_BLOCK_LOCK 0xa0 #define BL_ALL_UNLOCKED 0x00 --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2DEE1369225; Fri, 9 Jan 2026 17:18:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979115; cv=none; b=T7pkdlZCxLI8ED8QXa6eQmQ+EiY0cGGe5D91JuXNI6XtKDGQXFNsutcI5V1VeWzTVi3sCvK1wKLtjLbYhcr56XWDdNBtatl3vvzmo6FrMnhVvA0127gbsyCck/uP98l4Mg6ZfOU8qYBCi5d/JZOOEzWPCv6oCI+5bxmkCYNHicE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979115; c=relaxed/simple; bh=bLXQwY2X+HWDmSjIH+88jisc8V0Mv2LIfYmZ6hOFc4g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kzvD691sB/ngOgRphVK1Af7SYh700x9bK3EtOKo+kOutfNnk8U6SpTu9R/YVPTtHPJ2wK4qo0sJln9uhAyg4PGWtDPgl14qZELZzQEnIfwY96Fr//b+PANBuJX0oMAUfFZc0dy+DTyxK4hNBob933Ql4F9eH9cLJKbASI3m4YTg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=AtRg/7QQ; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="AtRg/7QQ" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id BE0A81A2751; Fri, 9 Jan 2026 17:18:27 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 90AD6606C6; Fri, 9 Jan 2026 17:18:27 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 057F3103C89AF; Fri, 9 Jan 2026 18:18:25 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767979106; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=3fZHdLVT5PZs+GglC5vvX4FQ5Jnb/RN7FPEdbUSBxJw=; b=AtRg/7QQnelwa/V+wRQj9SopmraxNZaszEiPYvTqD0ygrJbZIRiwAKsy0r1oAlVclVD/Zd JR/rvSvqZqs1z0V6bRAmcaRmtxK5HTTkVerx0k2RPzZiJS2CcGgKfvs0qVgjZTWXPdZIRx 3yNs5R9mxhK0yPr8iN4Tz7bq35nlGDA4mJUavhfaA3DukYRK87SU2m1wHa2cvMyVPMNzzU EMF9N2u9r3kgO+oShf1AVdrxa+jb8t9ChmCaAJwVybEg65DoOnpVARVjNcxRfVLXLV83R8 xUH95GqE3dkTDkcHDy2opfdu6BB+jxeIJzyAvVY/D0IiA1tvEfDGEttU3ohOJw== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:05 +0100 Subject: [PATCH v2 07/27] mtd: spinand: Use standard return values Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-7-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Replace -ENOTSUPP with -EOPNOTSUPP which is as relevant in this case but is standard. Reviewed-by: Tudor Ambarus Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/core.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 8acea0372f21..3abc56e4d23f 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1419,28 +1419,28 @@ int spinand_match_and_init(struct spinand_device *s= pinand, op =3D spinand_select_op_variant(spinand, info->op_variants.read_cache); if (!op) - return -ENOTSUPP; + return -EOPNOTSUPP; =20 spinand->op_templates.read_cache =3D op; =20 op =3D spinand_select_op_variant(spinand, info->op_variants.write_cache); if (!op) - return -ENOTSUPP; + return -EOPNOTSUPP; =20 spinand->op_templates.write_cache =3D op; =20 op =3D spinand_select_op_variant(spinand, info->op_variants.update_cache); if (!op) - return -ENOTSUPP; + return -EOPNOTSUPP; =20 spinand->op_templates.update_cache =3D op; =20 return 0; } =20 - return -ENOTSUPP; + return -EOPNOTSUPP; } =20 static int spinand_detect(struct spinand_device *spinand) --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D3D2366572 for ; Fri, 9 Jan 2026 17:18:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979115; cv=none; b=kQZX8Pyd/vWcjrMwbfyRoGTeuUrX6KTPW0pQMfbBXCkd/aeZqjj3FV47ed4pjIvSPosSRZ0AsabMoVmJqnuxHxy/YPuCFcNdoB+K8L8quGyvEpfklEl0e42T9cmvIrcpqP/T7Hv35tW/WhxyGZvVGkuxrUZT5QdrrIMahbcJdJk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979115; c=relaxed/simple; bh=3cnZl6iBYq20G1oigmirIZU3zYFeD3CzrUt2kAf0RZE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=q4UFlC5tkOFHvnlcksADuklfY/Xmxo+nCqq9l3+YMYcQMLk2qN/83nBVnA72YCHGTdY7QgaJh2Qmf3spyOfVphF3U68Y1/5E5NDCHA2nZJnA44acfyjs1lD3Yfs1qRov7cXxaTIcPQO88Bj7jlctxSZWFpuD/2TA7miPtuLQVhI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=anUYVoSF; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="anUYVoSF" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id E332B1A2752; Fri, 9 Jan 2026 17:18:28 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id B8A2D606C6; Fri, 9 Jan 2026 17:18:28 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 23A93103C89B0; Fri, 9 Jan 2026 18:18:27 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767979108; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=+jxMeS1xeb2E/hPVCFWCVOrKjIjBVGxQ/ROrL992r1Q=; b=anUYVoSF/XEgcDp6AyMCYYU4XpfSBdPg8hGKre023w+RWt7yJh0T0Nd3i3Kr5jrdQta2v4 WT+2Dk3YY0Wboj3L4MyE5Cm2Jb/9YwErd6zxfLmhN9VtXuEd9awgxsAZ3gwieFmbRWih5t Es1nOOTSXTrZl7ySmeGZjK7/EjVyn2PpFyUgudVh76nTzgKeDBYWy/1ZNEkhHaCDlHCHcE XdxgTiVJQlt0ONb3wwDPi43vIShbeXHyxRIEmJTMDv2A/Npvx36Gem/YWTZ13ESZdwW34c RXvo2YVvlIelwY8Rc8M9YP6Yi2CDBouoenRzxJrPhlpU4kgBqzksa/i1q+iAog== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:06 +0100 Subject: [PATCH v2 08/27] mtd: spinand: Decouple write enable and write disable operations Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-8-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 In order to introduce templates for all operations and not only for page helpers (in order to introduce octal DDR support), decouple the WR_EN and WR_DIS operations into two separate macros. Adapt the callers accordingly. There is no functional change. Reviewed-by: Tudor Ambarus Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/core.c | 2 +- drivers/mtd/nand/spi/esmt.c | 2 +- drivers/mtd/nand/spi/micron.c | 2 +- include/linux/mtd/spinand.h | 10 ++++++++-- 4 files changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 3abc56e4d23f..b6613f2651bd 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -362,7 +362,7 @@ static void spinand_ondie_ecc_save_status(struct nand_d= evice *nand, u8 status) =20 int spinand_write_enable_op(struct spinand_device *spinand) { - struct spi_mem_op op =3D SPINAND_WR_EN_DIS_1S_0_0_OP(true); + struct spi_mem_op op =3D SPINAND_WR_EN_1S_0_0_OP; =20 return spi_mem_exec_op(spinand->spimem, &op); } diff --git a/drivers/mtd/nand/spi/esmt.c b/drivers/mtd/nand/spi/esmt.c index e60e4ac1fd6f..adadc01e8f2f 100644 --- a/drivers/mtd/nand/spi/esmt.c +++ b/drivers/mtd/nand/spi/esmt.c @@ -138,7 +138,7 @@ static int f50l1g41lb_user_otp_info(struct spinand_devi= ce *spinand, size_t len, static int f50l1g41lb_otp_lock(struct spinand_device *spinand, loff_t from, size_t len) { - struct spi_mem_op write_op =3D SPINAND_WR_EN_DIS_1S_0_0_OP(true); + struct spi_mem_op write_op =3D SPINAND_WR_EN_1S_0_0_OP; struct spi_mem_op exec_op =3D SPINAND_PROG_EXEC_1S_1S_0_OP(0); u8 status; int ret; diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c index a49d7cb6a96d..b8130e04e8e7 100644 --- a/drivers/mtd/nand/spi/micron.c +++ b/drivers/mtd/nand/spi/micron.c @@ -251,7 +251,7 @@ static int mt29f2g01abagd_user_otp_info(struct spinand_= device *spinand, static int mt29f2g01abagd_otp_lock(struct spinand_device *spinand, loff_t = from, size_t len) { - struct spi_mem_op write_op =3D SPINAND_WR_EN_DIS_1S_0_0_OP(true); + struct spi_mem_op write_op =3D SPINAND_WR_EN_1S_0_0_OP; struct spi_mem_op exec_op =3D SPINAND_PROG_EXEC_1S_1S_0_OP(0); u8 status; int ret; diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index ad2773f1f963..f7621b47b28f 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -26,8 +26,14 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_NO_DATA) =20 -#define SPINAND_WR_EN_DIS_1S_0_0_OP(enable) \ - SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1), \ +#define SPINAND_WR_EN_1S_0_0_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x06, 1), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPINAND_WR_DIS_1S_0_0_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x04, 1), \ SPI_MEM_OP_NO_ADDR, \ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_NO_DATA) --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D3223659F9 for ; Fri, 9 Jan 2026 17:18:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979115; cv=none; b=SQVvf5fbDys6IEWG/FTDsnLGFl11YsSUp4nawmK+vVAtE95yFv4t/WHtZglu+IVnVK9g+btTShN03pc4tDWrqBc4mbtcQOrUYoyT0J9jL9xBjga2aSpIYhpLGsT1FIyBKdFDd5KW1P03uS9BPTbb9eAwm7X70QF/uWDUPjVS+3U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979115; c=relaxed/simple; bh=O2Vja9Q74ZaAIKZ9783grLO1CK0oEQBSP+m0MsajdQc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EWPneVp54Kp6FDXchmUsLAY6zgFfuKoscQjKmJyqLZzYXiDuoEO40PcvwZNqWwUxkbGA3XLI1Xpg2X7R4vweOyOCFCQNEsfFUmyhc/Gg1WObJHNlHTSpya2nYe18zaRN5UtIEXpnmMACj00Rf9gErG/Tl+otBg03qELqJ/3y22Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=geYncy1I; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="geYncy1I" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id AA439C1F6E6; Fri, 9 Jan 2026 17:18:03 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id F2696606C6; Fri, 9 Jan 2026 17:18:29 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 5C7F8103C89B1; Fri, 9 Jan 2026 18:18:28 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767979109; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=C+NW7ufPtXAo90lRbqvpylIj3Nw7aLGrnWQNApnc12c=; b=geYncy1IUnZfeLV1g2M2kua6pOdWbNq9sZC7EbCL0Sm6YcBXJ9akT191QBKtkKEeVmkFKA 2NaVsSc+SB8nwUD8wDC9rjRGy8bFASsa689lVMEqmTED5I6WOdTP7TBiTszX++6JN2LN+L QBlCxnpusTuZ9ekhDpzGyad3c65cYE4HfEq0sb8n9UAmiHaw5w0OtC4uE+FPb6sI19ZFdV b6DSceNRb1PmOlDfvGBfh4OV4obW0/aE0t42Gs34TtcS18ymaSA64dzygD8ORdrW2HuehS GkreL4Hhmq2d00V/d8Y6gB/wOHt3x2ROTpjdaDcLK//djjXNQsjb/1QSBtX/Vg== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:07 +0100 Subject: [PATCH v2 09/27] mtd: spinand: Create an array of operation templates Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-9-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Currently, the SPI NAND core implementation directly calls macros to get the various operations in shape. These macros are specific to the bus interface, currently only supporting the single SDR interface (any command following the 1S-XX-XX pattern). Introducing support for other bus interfaces (such as octal DTR) would mean that every user of these macros should become aware of the current bus interface and act accordingly, picking up and adapting to the current configuration. This would add quite a bit of boilerplate, be repetitive as well as error prone in case we miss one occurrence. Instead, let's create a table with all SPI NAND memory operations that are currently supported. We initialize them with the same single SDR _OP macros as before. This opens the possibility for users of the individual macros to make use of these templates instead. This way, when we will add another bus interface, we can just switch to another set of templates and all users will magically fill in their spi_mem_op structures with the correct ops. The existing read, write and update cache variants are also moved in this template array, which is barely noticeable by callers as we also add a structure member pointing to it. Reviewed-by: Tudor Ambarus Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/core.c | 38 +++++++++++++++++++++++++++---------- drivers/mtd/nand/spi/winbond.c | 4 ++-- include/linux/mtd/spinand.h | 43 +++++++++++++++++++++++++++++++++-----= ---- 3 files changed, 64 insertions(+), 21 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index b6613f2651bd..3e1b6c6c6a22 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -184,9 +184,9 @@ static int spinand_init_quad_enable(struct spinand_devi= ce *spinand) if (!(spinand->flags & SPINAND_HAS_QE_BIT)) return 0; =20 - if (spinand->op_templates.read_cache->data.buswidth =3D=3D 4 || - spinand->op_templates.write_cache->data.buswidth =3D=3D 4 || - spinand->op_templates.update_cache->data.buswidth =3D=3D 4) + if (spinand->op_templates->read_cache->data.buswidth =3D=3D 4 || + spinand->op_templates->write_cache->data.buswidth =3D=3D 4 || + spinand->op_templates->update_cache->data.buswidth =3D=3D 4) enable =3D true; =20 return spinand_upd_cfg(spinand, CFG_QUAD_ENABLE, @@ -1154,7 +1154,7 @@ static int spinand_create_dirmap(struct spinand_devic= e *spinand, info.offset =3D plane << fls(nand->memorg.pagesize); =20 info.length =3D nanddev_page_size(nand) + nanddev_per_page_oobsize(nand); - info.op_tmpl =3D *spinand->op_templates.update_cache; + info.op_tmpl =3D *spinand->op_templates->update_cache; desc =3D devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev, spinand->spimem, &info); if (IS_ERR(desc)) @@ -1162,7 +1162,7 @@ static int spinand_create_dirmap(struct spinand_devic= e *spinand, =20 spinand->dirmaps[plane].wdesc =3D desc; =20 - info.op_tmpl =3D *spinand->op_templates.read_cache; + info.op_tmpl =3D *spinand->op_templates->read_cache; desc =3D spinand_create_rdesc(spinand, &info); if (IS_ERR(desc)) return PTR_ERR(desc); @@ -1177,7 +1177,7 @@ static int spinand_create_dirmap(struct spinand_devic= e *spinand, } =20 info.length =3D nanddev_page_size(nand) + nanddev_per_page_oobsize(nand); - info.op_tmpl =3D *spinand->op_templates.update_cache; + info.op_tmpl =3D *spinand->op_templates->update_cache; info.op_tmpl.data.ecc =3D true; desc =3D devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev, spinand->spimem, &info); @@ -1186,7 +1186,7 @@ static int spinand_create_dirmap(struct spinand_devic= e *spinand, =20 spinand->dirmaps[plane].wdesc_ecc =3D desc; =20 - info.op_tmpl =3D *spinand->op_templates.read_cache; + info.op_tmpl =3D *spinand->op_templates->read_cache; info.op_tmpl.data.ecc =3D true; desc =3D spinand_create_rdesc(spinand, &info); if (IS_ERR(desc)) @@ -1323,6 +1323,22 @@ static void spinand_manufacturer_cleanup(struct spin= and_device *spinand) return spinand->manufacturer->ops->cleanup(spinand); } =20 +static void spinand_init_ssdr_templates(struct spinand_device *spinand) +{ + struct spinand_mem_ops *tmpl =3D &spinand->ssdr_op_templates; + + tmpl->reset =3D (struct spi_mem_op)SPINAND_RESET_1S_0_0_OP; + tmpl->readid =3D (struct spi_mem_op)SPINAND_READID_1S_1S_1S_OP(0, 0, NULL= , 0); + tmpl->wr_en =3D (struct spi_mem_op)SPINAND_WR_EN_1S_0_0_OP; + tmpl->wr_dis =3D (struct spi_mem_op)SPINAND_WR_DIS_1S_0_0_OP; + tmpl->set_feature =3D (struct spi_mem_op)SPINAND_SET_FEATURE_1S_1S_1S_OP(= 0, NULL); + tmpl->get_feature =3D (struct spi_mem_op)SPINAND_GET_FEATURE_1S_1S_1S_OP(= 0, NULL); + tmpl->blk_erase =3D (struct spi_mem_op)SPINAND_BLK_ERASE_1S_1S_0_OP(0); + tmpl->page_read =3D (struct spi_mem_op)SPINAND_PAGE_READ_1S_1S_0_OP(0); + tmpl->prog_exec =3D (struct spi_mem_op)SPINAND_PROG_EXEC_1S_1S_0_OP(0); + spinand->op_templates =3D &spinand->ssdr_op_templates; +} + static const struct spi_mem_op * spinand_select_op_variant(struct spinand_device *spinand, const struct spinand_op_variants *variants) @@ -1421,21 +1437,21 @@ int spinand_match_and_init(struct spinand_device *s= pinand, if (!op) return -EOPNOTSUPP; =20 - spinand->op_templates.read_cache =3D op; + spinand->ssdr_op_templates.read_cache =3D op; =20 op =3D spinand_select_op_variant(spinand, info->op_variants.write_cache); if (!op) return -EOPNOTSUPP; =20 - spinand->op_templates.write_cache =3D op; + spinand->ssdr_op_templates.write_cache =3D op; =20 op =3D spinand_select_op_variant(spinand, info->op_variants.update_cache); if (!op) return -EOPNOTSUPP; =20 - spinand->op_templates.update_cache =3D op; + spinand->ssdr_op_templates.update_cache =3D op; =20 return 0; } @@ -1550,6 +1566,8 @@ static int spinand_init(struct spinand_device *spinan= d) if (!spinand->scratchbuf) return -ENOMEM; =20 + spinand_init_ssdr_templates(spinand); + ret =3D spinand_detect(spinand); if (ret) goto err_free_bufs; diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 4870b2d5edb2..d5799c2df065 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -291,7 +291,7 @@ static int w25n0xjw_hs_cfg(struct spinand_device *spina= nd) u8 sr4; int ret; =20 - op =3D spinand->op_templates.read_cache; + op =3D spinand->op_templates->read_cache; if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) hs =3D false; else if (op->cmd.buswidth =3D=3D 1 && op->addr.buswidth =3D=3D 1 && @@ -355,7 +355,7 @@ static int w35n0xjw_vcr_cfg(struct spinand_device *spin= and) u8 io_mode; int ret; =20 - op =3D spinand->op_templates.read_cache; + op =3D spinand->op_templates->read_cache; =20 single =3D (op->cmd.buswidth =3D=3D 1 && op->addr.buswidth =3D=3D 1 && op= ->data.buswidth =3D=3D 1); dtr =3D (op->cmd.dtr || op->addr.dtr || op->data.dtr); diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index f7621b47b28f..2691b5818f77 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -599,6 +599,36 @@ struct spinand_dirmap { struct spi_mem_dirmap_desc *rdesc_ecc; }; =20 +/** + * struct spinand_mem_ops - SPI NAND memory operations + * @reset: reset op template + * @readid: read ID op template + * @wr_en: write enable op template + * @wr_dis: write disable op template + * @set_feature: set feature op template + * @get_feature: get feature op template + * @blk_erase: blk erase op template + * @page_read: page read op template + * @prog_exec: prog exec op template + * @read_cache: read cache op template + * @write_cache: write cache op template + * @update_cache: update cache op template + */ +struct spinand_mem_ops { + struct spi_mem_op reset; + struct spi_mem_op readid; + struct spi_mem_op wr_en; + struct spi_mem_op wr_dis; + struct spi_mem_op set_feature; + struct spi_mem_op get_feature; + struct spi_mem_op blk_erase; + struct spi_mem_op page_read; + struct spi_mem_op prog_exec; + const struct spi_mem_op *read_cache; + const struct spi_mem_op *write_cache; + const struct spi_mem_op *update_cache; +}; + /** * struct spinand_device - SPI NAND device instance * @base: NAND device instance @@ -606,10 +636,8 @@ struct spinand_dirmap { * @lock: lock used to serialize accesses to the NAND * @id: NAND ID as returned by READ_ID * @flags: NAND flags - * @op_templates: various SPI mem op templates - * @op_templates.read_cache: read cache op template - * @op_templates.write_cache: write cache op template - * @op_templates.update_cache: update cache op template + * @ssdr_op_templates: Templates for all single SDR SPI mem operations + * @op_templates: Templates for all SPI mem operations * @select_target: select a specific target/die. Usually called before sen= ding * a command addressing a page or an eraseblock embedded in * this die. Only required if your chip exposes several dies @@ -643,11 +671,8 @@ struct spinand_device { struct spinand_id id; u32 flags; =20 - struct { - const struct spi_mem_op *read_cache; - const struct spi_mem_op *write_cache; - const struct spi_mem_op *update_cache; - } op_templates; + struct spinand_mem_ops ssdr_op_templates; + struct spinand_mem_ops *op_templates; =20 struct spinand_dirmap *dirmaps; =20 --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A1DC364E9F for ; Fri, 9 Jan 2026 17:18:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979118; cv=none; b=cM2X4uoib4ept+vuRz7VbKMQXN4SOEltv5HptgPc/Y30UQxXQXw26zyiJJY46EBNRoJoDQfpTZM4g/2aYwcCjvc4kMFtW4FzYSYF1l42Fc9p6AgfQcrVxE7amYsj5zGwqbYmwyewetHBnqZzhIahfIYVLVXHRnPA6n3Fewtel1o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979118; c=relaxed/simple; bh=8Td95AA6h9Rh8RI4v6vVN+K/8NNZLwlUA5PsGP4azBQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=X6gR6BhVUXcMOxf+aTwm885IN+z3b2JFw1CSQaW7epsPJ9cJ1EaN3vntTMrMi9GRJJ9b31i32jRKCJbOR6GR+KeccMH3BTCSAesyLCF/D+LI0FmMQevS5sXFcffj4QPzjnygRTV8uOK06ckvS6Un1zIUqX/AmBuWRoaNd+hxsRA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=vUVL8aAC; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="vUVL8aAC" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id EC0E5C1F6E7; Fri, 9 Jan 2026 17:18:04 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 3FBF5606C6; Fri, 9 Jan 2026 17:18:31 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 990CB103C89B2; Fri, 9 Jan 2026 18:18:29 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767979110; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=47BFkvp1DEd5/5BI/hfjcGhX9bpoRnXfqFY5VY7IdiU=; b=vUVL8aAC94fy4qJjrT/nxxn5sEgLApkL10IK2BfakUtcEHgPZGwrMYKs9KjyZG4exKeX9n vANJyIrcpl+5TXKiGI2u2SX82e0hKgdMtjR02RdPNEJKmCLuo99D53M7YLaqfj1NDi3ITq MtzaOkGPoDCnNwwICkLHIG2DR9EsqrsNPCZJqnYeZhH99f2Ld6MEiOOjTn3JcEkn1oNsMG wVPiNsgZM3WQJ4iiRkcUNBI84F0Qru9hvI/OYXQey2iIVc9CJJ5Eq9Ki1bdldr8xC266Az RNDTOrsX0/NZdyoNs3NK7N2eemAs7FJy7dMeN9/ufAAOd6eLfU84v39+AbUu7Q== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:08 +0100 Subject: [PATCH v2 10/27] mtd: spinand: Make use of the operation templates through SPINAND_OP() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-10-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Create a SPINAND_OP() macro to which we give the name of the operation we want. This macro retrieves the correct operation template based on the current bus interface (currently only single SDR, will soon be extended to octal DTR) and fills it with the usual parameters. This macro makes the transition from calling directly the low-level macros into using the (bus interface dependent) templates very smooth. Use it in all places that can be trivially converted. At this stage there is no functional change expected, until octal DTR support gets added. Reviewed-by: Tudor Ambarus Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/core.c | 110 +++++++++++++++++++++++++++++++++-= ---- drivers/mtd/nand/spi/esmt.c | 4 +- drivers/mtd/nand/spi/gigadevice.c | 8 +-- drivers/mtd/nand/spi/macronix.c | 4 +- drivers/mtd/nand/spi/micron.c | 8 +-- drivers/mtd/nand/spi/toshiba.c | 3 +- drivers/mtd/nand/spi/winbond.c | 3 +- include/linux/mtd/spinand.h | 8 +++ 8 files changed, 121 insertions(+), 27 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 3e1b6c6c6a22..609a955788fa 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -20,10 +20,94 @@ #include #include =20 +static struct spi_mem_op +spinand_fill_reset_op(struct spinand_device *spinand) +{ + return spinand->op_templates->reset; +} + +static struct spi_mem_op +spinand_fill_readid_op(struct spinand_device *spinand, + u8 naddr, u8 ndummy, void *buf, unsigned int len) +{ + struct spi_mem_op op =3D spinand->op_templates->readid; + + op.addr.nbytes =3D naddr; + op.dummy.nbytes =3D ndummy; + op.data.buf.in =3D buf; + op.data.nbytes =3D len; + + return op; +} + +struct spi_mem_op +spinand_fill_wr_en_op(struct spinand_device *spinand) +{ + return spinand->op_templates->wr_en; +} + +static __maybe_unused struct spi_mem_op +spinand_fill_wr_dis_op(struct spinand_device *spinand) +{ + return spinand->op_templates->wr_dis; +} + +struct spi_mem_op +spinand_fill_set_feature_op(struct spinand_device *spinand, u64 reg, const= void *valptr) +{ + struct spi_mem_op op =3D spinand->op_templates->set_feature; + + op.addr.val =3D reg; + op.data.buf.out =3D valptr; + + return op; +} + +struct spi_mem_op +spinand_fill_get_feature_op(struct spinand_device *spinand, u64 reg, void = *valptr) +{ + struct spi_mem_op op =3D spinand->op_templates->get_feature; + + op.addr.val =3D reg; + op.data.buf.in =3D valptr; + + return op; +} + +static struct spi_mem_op +spinand_fill_blk_erase_op(struct spinand_device *spinand, u64 addr) +{ + struct spi_mem_op op =3D spinand->op_templates->blk_erase; + + op.addr.val =3D addr; + + return op; +} + +static struct spi_mem_op +spinand_fill_page_read_op(struct spinand_device *spinand, u64 addr) +{ + struct spi_mem_op op =3D spinand->op_templates->page_read; + + op.addr.val =3D addr; + + return op; +} + +struct spi_mem_op +spinand_fill_prog_exec_op(struct spinand_device *spinand, u64 addr) +{ + struct spi_mem_op op =3D spinand->op_templates->prog_exec; + + op.addr.val =3D addr; + + return op; +} + int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) { - struct spi_mem_op op =3D SPINAND_GET_FEATURE_1S_1S_1S_OP(reg, - spinand->scratchbuf); + struct spi_mem_op op =3D SPINAND_OP(spinand, get_feature, + reg, spinand->scratchbuf); int ret; =20 ret =3D spi_mem_exec_op(spinand->spimem, &op); @@ -36,8 +120,8 @@ int spinand_read_reg_op(struct spinand_device *spinand, = u8 reg, u8 *val) =20 int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val) { - struct spi_mem_op op =3D SPINAND_SET_FEATURE_1S_1S_1S_OP(reg, - spinand->scratchbuf); + struct spi_mem_op op =3D SPINAND_OP(spinand, set_feature, + reg, spinand->scratchbuf); =20 *spinand->scratchbuf =3D val; return spi_mem_exec_op(spinand->spimem, &op); @@ -362,7 +446,7 @@ static void spinand_ondie_ecc_save_status(struct nand_d= evice *nand, u8 status) =20 int spinand_write_enable_op(struct spinand_device *spinand) { - struct spi_mem_op op =3D SPINAND_WR_EN_1S_0_0_OP; + struct spi_mem_op op =3D SPINAND_OP(spinand, wr_en); =20 return spi_mem_exec_op(spinand->spimem, &op); } @@ -372,7 +456,7 @@ static int spinand_load_page_op(struct spinand_device *= spinand, { struct nand_device *nand =3D spinand_to_nand(spinand); unsigned int row =3D nanddev_pos_to_row(nand, &req->pos); - struct spi_mem_op op =3D SPINAND_PAGE_READ_1S_1S_0_OP(row); + struct spi_mem_op op =3D SPINAND_OP(spinand, page_read, row); =20 return spi_mem_exec_op(spinand->spimem, &op); } @@ -527,7 +611,7 @@ static int spinand_program_op(struct spinand_device *sp= inand, { struct nand_device *nand =3D spinand_to_nand(spinand); unsigned int row =3D nanddev_pos_to_row(nand, &req->pos); - struct spi_mem_op op =3D SPINAND_PROG_EXEC_1S_1S_0_OP(row); + struct spi_mem_op op =3D SPINAND_OP(spinand, prog_exec, row); =20 return spi_mem_exec_op(spinand->spimem, &op); } @@ -537,7 +621,7 @@ static int spinand_erase_op(struct spinand_device *spin= and, { struct nand_device *nand =3D spinand_to_nand(spinand); unsigned int row =3D nanddev_pos_to_row(nand, pos); - struct spi_mem_op op =3D SPINAND_BLK_ERASE_1S_1S_0_OP(row); + struct spi_mem_op op =3D SPINAND_OP(spinand, blk_erase, row); =20 return spi_mem_exec_op(spinand->spimem, &op); } @@ -557,8 +641,8 @@ static int spinand_erase_op(struct spinand_device *spin= and, int spinand_wait(struct spinand_device *spinand, unsigned long initial_del= ay_us, unsigned long poll_delay_us, u8 *s) { - struct spi_mem_op op =3D SPINAND_GET_FEATURE_1S_1S_1S_OP(REG_STATUS, - spinand->scratchbuf); + struct spi_mem_op op =3D SPINAND_OP(spinand, get_feature, + REG_STATUS, spinand->scratchbuf); u8 status; int ret; =20 @@ -591,8 +675,8 @@ int spinand_wait(struct spinand_device *spinand, unsign= ed long initial_delay_us, static int spinand_read_id_op(struct spinand_device *spinand, u8 naddr, u8 ndummy, u8 *buf) { - struct spi_mem_op op =3D SPINAND_READID_1S_1S_1S_OP( - naddr, ndummy, spinand->scratchbuf, SPINAND_MAX_ID_LEN); + struct spi_mem_op op =3D SPINAND_OP(spinand, readid, + naddr, ndummy, spinand->scratchbuf, SPINAND_MAX_ID_LEN); int ret; =20 ret =3D spi_mem_exec_op(spinand->spimem, &op); @@ -604,7 +688,7 @@ static int spinand_read_id_op(struct spinand_device *sp= inand, u8 naddr, =20 static int spinand_reset_op(struct spinand_device *spinand) { - struct spi_mem_op op =3D SPINAND_RESET_1S_0_0_OP; + struct spi_mem_op op =3D SPINAND_OP(spinand, reset); int ret; =20 ret =3D spi_mem_exec_op(spinand->spimem, &op); diff --git a/drivers/mtd/nand/spi/esmt.c b/drivers/mtd/nand/spi/esmt.c index adadc01e8f2f..3020aa89a495 100644 --- a/drivers/mtd/nand/spi/esmt.c +++ b/drivers/mtd/nand/spi/esmt.c @@ -138,8 +138,8 @@ static int f50l1g41lb_user_otp_info(struct spinand_devi= ce *spinand, size_t len, static int f50l1g41lb_otp_lock(struct spinand_device *spinand, loff_t from, size_t len) { - struct spi_mem_op write_op =3D SPINAND_WR_EN_1S_0_0_OP; - struct spi_mem_op exec_op =3D SPINAND_PROG_EXEC_1S_1S_0_OP(0); + struct spi_mem_op write_op =3D SPINAND_OP(spinand, wr_en); + struct spi_mem_op exec_op =3D SPINAND_OP(spinand, prog_exec, 0); u8 status; int ret; =20 diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigad= evice.c index 72ad36c9a126..e4380208edd0 100644 --- a/drivers/mtd/nand/spi/gigadevice.c +++ b/drivers/mtd/nand/spi/gigadevice.c @@ -266,8 +266,8 @@ static int gd5fxgq4uexxg_ecc_get_status(struct spinand_= device *spinand, u8 status) { u8 status2; - struct spi_mem_op op =3D SPINAND_GET_FEATURE_1S_1S_1S_OP(GD5FXGQXXEXXG_RE= G_STATUS2, - spinand->scratchbuf); + struct spi_mem_op op =3D SPINAND_OP(spinand, get_feature, + GD5FXGQXXEXXG_REG_STATUS2, spinand->scratchbuf); int ret; =20 switch (status & STATUS_ECC_MASK) { @@ -309,8 +309,8 @@ static int gd5fxgq5xexxg_ecc_get_status(struct spinand_= device *spinand, u8 status) { u8 status2; - struct spi_mem_op op =3D SPINAND_GET_FEATURE_1S_1S_1S_OP(GD5FXGQXXEXXG_RE= G_STATUS2, - spinand->scratchbuf); + struct spi_mem_op op =3D SPINAND_OP(spinand, get_feature, + GD5FXGQXXEXXG_REG_STATUS2, spinand->scratchbuf); int ret; =20 switch (status & STATUS_ECC_MASK) { diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macroni= x.c index edf63b9996cf..143cc120bdec 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -148,8 +148,8 @@ static int macronix_set_cont_read(struct spinand_device= *spinand, bool enable) static int macronix_set_read_retry(struct spinand_device *spinand, unsigned int retry_mode) { - struct spi_mem_op op =3D SPINAND_SET_FEATURE_1S_1S_1S_OP(MACRONIX_FEATURE= _ADDR_READ_RETRY, - spinand->scratchbuf); + struct spi_mem_op op =3D SPINAND_OP(spinand, set_feature, + MACRONIX_FEATURE_ADDR_READ_RETRY, spinand->scratchbuf); =20 *spinand->scratchbuf =3D retry_mode; return spi_mem_exec_op(spinand->spimem, &op); diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c index b8130e04e8e7..36f6cbbd7462 100644 --- a/drivers/mtd/nand/spi/micron.c +++ b/drivers/mtd/nand/spi/micron.c @@ -137,8 +137,8 @@ static const struct mtd_ooblayout_ops micron_4_ooblayou= t =3D { static int micron_select_target(struct spinand_device *spinand, unsigned int target) { - struct spi_mem_op op =3D SPINAND_SET_FEATURE_1S_1S_1S_OP(MICRON_DIE_SELEC= T_REG, - spinand->scratchbuf); + struct spi_mem_op op =3D SPINAND_OP(spinand, set_feature, + MICRON_DIE_SELECT_REG, spinand->scratchbuf); =20 if (target > 1) return -EINVAL; @@ -251,8 +251,8 @@ static int mt29f2g01abagd_user_otp_info(struct spinand_= device *spinand, static int mt29f2g01abagd_otp_lock(struct spinand_device *spinand, loff_t = from, size_t len) { - struct spi_mem_op write_op =3D SPINAND_WR_EN_1S_0_0_OP; - struct spi_mem_op exec_op =3D SPINAND_PROG_EXEC_1S_1S_0_OP(0); + struct spi_mem_op write_op =3D SPINAND_OP(spinand, wr_en); + struct spi_mem_op exec_op =3D SPINAND_OP(spinand, prog_exec, 0); u8 status; int ret; =20 diff --git a/drivers/mtd/nand/spi/toshiba.c b/drivers/mtd/nand/spi/toshiba.c index 6530257ac0be..ef649162ee68 100644 --- a/drivers/mtd/nand/spi/toshiba.c +++ b/drivers/mtd/nand/spi/toshiba.c @@ -73,7 +73,8 @@ static int tx58cxgxsxraix_ecc_get_status(struct spinand_d= evice *spinand, { struct nand_device *nand =3D spinand_to_nand(spinand); u8 mbf =3D 0; - struct spi_mem_op op =3D SPINAND_GET_FEATURE_1S_1S_1S_OP(0x30, spinand->s= cratchbuf); + struct spi_mem_op op =3D SPINAND_OP(spinand, get_feature, + 0x30, spinand->scratchbuf); =20 switch (status & STATUS_ECC_MASK) { case STATUS_ECC_NO_BITFLIPS: diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index d5799c2df065..bfec5d037f25 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -251,7 +251,8 @@ static int w25n02kv_ecc_get_status(struct spinand_devic= e *spinand, { struct nand_device *nand =3D spinand_to_nand(spinand); u8 mbf =3D 0; - struct spi_mem_op op =3D SPINAND_GET_FEATURE_1S_1S_1S_OP(0x30, spinand->s= cratchbuf); + struct spi_mem_op op =3D SPINAND_OP(spinand, get_feature, + 0x30, spinand->scratchbuf); =20 switch (status & STATUS_ECC_MASK) { case STATUS_ECC_NO_BITFLIPS: diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 2691b5818f77..f579245c90a6 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -702,6 +702,14 @@ struct spinand_device { unsigned int retry_mode); }; =20 +struct spi_mem_op spinand_fill_wr_en_op(struct spinand_device *spinand); +struct spi_mem_op spinand_fill_set_feature_op(struct spinand_device *spina= nd, u64 reg, const void *valptr); +struct spi_mem_op spinand_fill_get_feature_op(struct spinand_device *spina= nd, u64 reg, void *valptr); +struct spi_mem_op spinand_fill_prog_exec_op(struct spinand_device *spinand= , u64 addr); + +#define SPINAND_OP(spinand, op_name, ...) \ + spinand_fill_ ## op_name ## _op(spinand, ##__VA_ARGS__) + /** * mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance * @mtd: MTD instance --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23202363C7D; Fri, 9 Jan 2026 17:18:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; 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dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="B/LGMcFR" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id A00594E42029; Fri, 9 Jan 2026 17:18:32 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 7557A606C6; Fri, 9 Jan 2026 17:18:32 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id CC50D103C89B4; Fri, 9 Jan 2026 18:18:30 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767979111; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=4zjmlLEWJ7QiWDqCO5iOkGGWDWg9nbW2A4ll6YCRUWA=; b=B/LGMcFRBzv6EB4j2c0orh3cOwxmyU5vLKT8cWE6pXSo3dOam9Qlmkxis31MCOFDMjOEWJ 9Woy8QXW8qyBncApfqGJfJu5967gIV0WvoTChgzqGdrnk+QXJvjWh6PKIGobvtqWElc7zW kObxAOHcp+x4HYAT48VfE6sK1iVPr5SogSEAzu5fwdCnl+cLQ1dYjgBPVcy6JBZmGqOu7a alPc8/JLSj7WdeE5Hu9JDXjbMkh9OlrRJ46zQEWHek8zdmWQrHlwq8j5tgo8DuB7oqGbVv kMIfuZDYeTVLFE/LaYh98KDk6XeixcHTniEaTgI7Pl2wnyyI3FzQiFilf8llpg== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:09 +0100 Subject: [PATCH v2 11/27] mtd: spinand: macronix: Convert vendor specific operation to SPINAND_OP() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-11-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Macronix chips require a vendor specific operation to read the ECC status register. Instead of defining this op only in the function that needs it, hiding it from the core, make it a proper define like all other spi-mem operations, and implement the necessary spinand_fill_*_op() helper to make the SPINAND_OP() macro work. This way we can use it from any function without any extra handling outside of this helper when we will convert the core to support octal DDR busses. Reviewed-by: Tudor Ambarus Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/macronix.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macroni= x.c index 143cc120bdec..a847ea8f49a8 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -41,6 +41,18 @@ static SPINAND_OP_VARIANTS(update_cache_variants, SPINAND_PROG_LOAD_1S_1S_4S_OP(false, 0, NULL, 0), SPINAND_PROG_LOAD_1S_1S_1S_OP(false, 0, NULL, 0)); =20 +#define SPINAND_MACRONIX_READ_ECCSR_1S_0_1S(buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x7c, 1), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_DUMMY(1, 1), \ + SPI_MEM_OP_DATA_IN(1, buf, 1)) + +static struct spi_mem_op +spinand_fill_macronix_read_eccsr_op(struct spinand_device *spinand, void *= valptr) +{ + return (struct spi_mem_op)SPINAND_MACRONIX_READ_ECCSR_1S_0_1S(valptr); +} + static int mx35lfxge4ab_ooblayout_ecc(struct mtd_info *mtd, int section, struct mtd_oob_region *region) { @@ -67,12 +79,10 @@ static const struct mtd_ooblayout_ops mx35lfxge4ab_oobl= ayout =3D { static int macronix_get_eccsr(struct spinand_device *spinand, u8 *eccsr) { struct macronix_priv *priv =3D spinand->priv; - struct spi_mem_op op =3D SPI_MEM_OP(SPI_MEM_OP_CMD(0x7c, 1), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_DUMMY(1, 1), - SPI_MEM_OP_DATA_IN(1, eccsr, 1)); + struct spi_mem_op op =3D SPINAND_OP(spinand, macronix_read_eccsr, eccsr); + int ret; =20 - int ret =3D spi_mem_exec_op(spinand->spimem, &op); + ret =3D spi_mem_exec_op(spinand->spimem, &op); if (ret) return ret; =20 --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D872836A008; Fri, 9 Jan 2026 17:18:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979122; cv=none; b=uoAvDd+4zPRsCVwH1b+1rfPIPVcraQiDnO21ju/z5/MfTVXlcQGY2Cvp1uQXvUSXnQyBk+GM/LtjnapfE3i5nlM24zz0ZwSkdKvJ0GWKO6KIlPtl3iTJ0FUPwGwmDP4y0T3IQoY0hCkGrVVG+10c0pogccRM5uzX0Pn6UHGAWgs= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-12-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Winbond W25N* chips require a vendor specific operation to select the target. Instead of defining this op only in the function that needs it, hiding it from the core, make it a proper define like all other spi-mem operations, and implement the necessary spinand_fill_*_op() helper to make the SPINAND_OP() macro work. This way we can use it from any function without any extra handling outside of this helper when we will convert the core to support octal DDR busses. Reviewed-by: Tudor Ambarus Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/winbond.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index bfec5d037f25..dde59f8f63f5 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -87,6 +87,18 @@ static SPINAND_OP_VARIANTS(update_cache_variants, SPINAND_PROG_LOAD_1S_1S_4S_OP(false, 0, NULL, 0), SPINAND_PROG_LOAD_1S_1S_1S_OP(false, 0, NULL, 0)); =20 +#define SPINAND_WINBOND_SELECT_TARGET_1S_0_1S(buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0xc2, 1), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(1, buf, 1)) + +static struct spi_mem_op +spinand_fill_winbond_select_target_op(struct spinand_device *spinand, void= *valptr) +{ + return (struct spi_mem_op)SPINAND_WINBOND_SELECT_TARGET_1S_0_1S(valptr); +} + static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section, struct mtd_oob_region *region) { @@ -119,12 +131,8 @@ static const struct mtd_ooblayout_ops w25m02gv_ooblayo= ut =3D { static int w25m02gv_select_target(struct spinand_device *spinand, unsigned int target) { - struct spi_mem_op op =3D SPI_MEM_OP(SPI_MEM_OP_CMD(0xc2, 1), - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, - spinand->scratchbuf, - 1)); + struct spi_mem_op op =3D SPINAND_OP(spinand, winbond_select_target, + spinand->scratchbuf); =20 *spinand->scratchbuf =3D target; return spi_mem_exec_op(spinand->spimem, &op); --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE34B366DAE for ; Fri, 9 Jan 2026 17:18:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979123; cv=none; b=bX0gc4x+VCDWSNehH3nCHe9D0kIJgZcAVE1ZQkMbznCmuG1JXY6lSe02SLnsARIUMibUbum1XQrOLc9I8SjPtUFb4hRarK0JGKwaelDlm+uYpU2fonhbG0yMZ8dprDsRJf1/c4hfnT6sJnJNa8x1TPaodRlYAYoN5riJVsUBuGw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979123; c=relaxed/simple; bh=C9hwsEV3wdatwD062DI30KDF+447ewMTinjMJ6/pCpk=; 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Fri, 9 Jan 2026 17:18:34 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id B1DD6606C6; Fri, 9 Jan 2026 17:18:34 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 2A784103C89B6; Fri, 9 Jan 2026 18:18:33 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767979114; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=ByaYUaNaJV4Ff78T5l6xTtVf1Fq+ywBCL3Mu7MTdSkQ=; b=UdsMaNcoXXLblizSSEA94E3C9P1gYOwOG3Vz5eSmiqJHjG5wg6BwLbw8AesjWv6FfCZVdy MJWXpNP5Y2g1QFUXsAOKSy81FE+msf1OCh1zcmjrOBTC6p5EuO8i9z5T7SwzQ8Qotnre56 DkwcD5Uql3fcEqo9TV9KN9IC+68+4whP6QJw+XRHDijyQxyLKFjSO8BdnHf34tn1ZEadJi Loj5px3PcU+6lDYLHlzIEqqdZz423KFusUKE7TeNS/SseFaydMgk2PttoEXKB73M8X/E7r nBWITkh/C0maqJiWF9GauvknVG5/lFc7iJBRbASjgrn5fCCSEb7hBLwVAMnyDA== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:11 +0100 Subject: [PATCH v2 13/27] mtd: spinand: winbond: Convert W35N specific operation to SPINAND_OP() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-13-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Winbond W35N* chips require a vendor specific operation to write their VCR register (a configuration register, typically used for tuning the number of dummy cycles and switching to a different bus interface). Instead of defining this op only in the function that needs it, hiding it from the core, make it a proper define like all other spi-mem operations, and implement the necessary spinand_fill_*_op() helper to make the SPINAND_OP() macro work. This way we can use it from any function without any extra handling outside of this helper when we will convert the core to support octal DDR busses. Reviewed-by: Tudor Ambarus Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/winbond.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index dde59f8f63f5..3003ad7e83ee 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -87,6 +87,18 @@ static SPINAND_OP_VARIANTS(update_cache_variants, SPINAND_PROG_LOAD_1S_1S_4S_OP(false, 0, NULL, 0), SPINAND_PROG_LOAD_1S_1S_1S_OP(false, 0, NULL, 0)); =20 +#define SPINAND_WINBOND_WRITE_VCR_1S_1S_1S(reg, buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x81, 1), \ + SPI_MEM_OP_ADDR(3, reg, 1), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(1, buf, 1)) + +static struct spi_mem_op +spinand_fill_winbond_write_vcr_op(struct spinand_device *spinand, u8 reg, = void *valptr) +{ + return (struct spi_mem_op)SPINAND_WINBOND_WRITE_VCR_1S_1S_1S(reg, valptr); +} + #define SPINAND_WINBOND_SELECT_TARGET_1S_0_1S(buf) \ SPI_MEM_OP(SPI_MEM_OP_CMD(0xc2, 1), \ SPI_MEM_OP_NO_ADDR, \ @@ -329,11 +341,8 @@ static int w25n0xjw_hs_cfg(struct spinand_device *spin= and) =20 static int w35n0xjw_write_vcr(struct spinand_device *spinand, u8 reg, u8 v= al) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(0x81, 1), - SPI_MEM_OP_ADDR(3, reg, 1), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, spinand->scratchbuf, 1)); + struct spi_mem_op op =3D SPINAND_OP(spinand, winbond_write_vcr, + reg, spinand->scratchbuf); int ret; =20 *spinand->scratchbuf =3D val; --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74DE9366DAC for ; Fri, 9 Jan 2026 17:18:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979120; cv=none; b=UN9/Ka9W8TJnVsi4hqbj9jUPAtEDNjikk5aePmZADRE334MRm2F0vgf68IgRxGkyKsv4BfSVURlSfviEsXtLiINRr7F4LaggGAybqJTDVygr6TBwdfqQ4u9+HLoL558hty1/n1prSnISIL3HcA272X2YHwrb73oHdgmF+/9SR98= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979120; c=relaxed/simple; bh=KXCxJyeTz+tBBHYeqYf6wM/IdY/jM+iWLdTSbL0nLxc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Fri, 9 Jan 2026 17:18:35 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 5CF4B103C89B5; Fri, 9 Jan 2026 18:18:34 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767979115; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=dYZrs+RXfmLTkElRF8rJDqyvuBNMZBhyjBaevLKTgG0=; b=tkutj35lH9dAIxT7QJEFbQNZeOQ85inTVOh42yZIfEDabffbpwSyKIfVStzc6SnZr2Znvc HU+QbtGs7vemC7u+pabN1oqENrTQhVWICqEB3Y4R1qHABxsNHHdjujM9/gRCBTFq+RqmXy bDUhGtV6ynBYa7A//2+Ub3nenE4Qsvifi7/tQJIVio4LOkQT5Bcpaw0ITrftveVyxkzdKe yPFIHeLxJFm3fM1b3DtzdUORy8Kz+XY/moT6mJ1q5ixYb59QovVT2zhqka1CbYUhW77veS CzABnRNaDIjfKDegEsjINYCPpxIm+1mLwnf++SSIY96eBvEWzEWVKo4Wi+Njog== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:12 +0100 Subject: [PATCH v2 14/27] mtd: spinand: List vendor specific operations and make sure they are supported Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-14-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 It is probably safe to expect that all SPI controller drivers will ever support all the most basic SPI NAND operations, such as write enable, register reads, page program, block erases, etc. However, what about vendor specific operations? So far nobody complained about it, but as we are about to introduce octal DTR support, and as none of the SPI NAND instruction set is defined in any standard, we must remain careful about these extra operations. One way to make sure we do not blindly get ourselves in strange situations with vendor commands failing silently is to make the check once for all, while probing the chip. However at this stage we have no such list, so let's add the necessary infrastructure to allow: - registering vendor operations, - checking they are actually supported when appropriate. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/core.c | 26 ++++++++++++++++++++++++++ include/linux/mtd/spinand.h | 5 +++++ 2 files changed, 31 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 609a955788fa..88d87a96ddb0 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1423,6 +1423,27 @@ static void spinand_init_ssdr_templates(struct spina= nd_device *spinand) spinand->op_templates =3D &spinand->ssdr_op_templates; } =20 +static int spinand_support_vendor_ops(struct spinand_device *spinand, + const struct spinand_info *info) +{ + int i; + + /* + * The vendor ops array is only used in order to verify this chip and all= its memory + * operations are supported. If we see patterns emerging, we could ideall= y name these + * operations and define them at the SPI NAND core level instead. + * For now, this only serves as a sanity check. + */ + for (i =3D 0; i < info->vendor_ops->nops; i++) { + const struct spi_mem_op *op =3D &info->vendor_ops->ops[i]; + + if (!spi_mem_supports_op(spinand->spimem, op)) + return -EOPNOTSUPP; + } + + return 0; +} + static const struct spi_mem_op * spinand_select_op_variant(struct spinand_device *spinand, const struct spinand_op_variants *variants) @@ -1492,6 +1513,7 @@ int spinand_match_and_init(struct spinand_device *spi= nand, u8 *id =3D spinand->id.data; struct nand_device *nand =3D spinand_to_nand(spinand); unsigned int i; + int ret; =20 for (i =3D 0; i < table_size; i++) { const struct spinand_info *info =3D &table[i]; @@ -1537,6 +1559,10 @@ int spinand_match_and_init(struct spinand_device *sp= inand, =20 spinand->ssdr_op_templates.update_cache =3D op; =20 + ret =3D spinand_support_vendor_ops(spinand, info); + if (ret) + return ret; + return 0; } =20 diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index f579245c90a6..88871287c739 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -493,6 +493,7 @@ struct spinand_user_otp { * @op_variants.read_cache: variants of the read-cache operation * @op_variants.write_cache: variants of the write-cache operation * @op_variants.update_cache: variants of the update-cache operation + * @vendor_ops: vendor specific operations * @select_target: function used to select a target/die. Required only for * multi-die chips * @configure_chip: Align the chip configuration with the core settings @@ -517,6 +518,7 @@ struct spinand_info { const struct spinand_op_variants *write_cache; const struct spinand_op_variants *update_cache; } op_variants; + const struct spinand_op_variants *vendor_ops; int (*select_target)(struct spinand_device *spinand, unsigned int target); int (*configure_chip)(struct spinand_device *spinand); @@ -543,6 +545,9 @@ struct spinand_info { .update_cache =3D __update, \ } =20 +#define SPINAND_INFO_VENDOR_OPS(__ops) \ + .vendor_ops =3D __ops + #define SPINAND_ECCINFO(__ooblayout, __get_status) \ .eccinfo =3D { \ .ooblayout =3D __ooblayout, \ --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71D4E36A026 for ; Fri, 9 Jan 2026 17:18:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979120; cv=none; b=lRBkV1ajI5L4RcqDFiQ2iW1jCm8RY2szE1S49hJTZjZO9caW5YEoGBawWf60v4Bo3l+1HqQ6E579/lc443n30kCvRz/2yJz5OfG+4ZB6+7ldEHyO6dhsAG3PFteWHNfuUI6+W6zheKz3ht6h6f1DEGeOjBPqnAim81XD52AvCcg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979120; c=relaxed/simple; bh=T5mrn5eLWK+kknNvL9a96ce7ZXaGz/rSrwm7+sg8ok8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cxeoi4TBA1bE5aLMy/tHtfAEFWampfm1KrQcBON73r3+FhAviG6bz4AZVxKZz7F2sqHIX3OKmTjUy3n415NQ04qyyRJOq9mDVl69xWut4TyOfuPz+qsAwEBgxvSYwgMF7VHCcGGZk94RqUZKJ52QCsGWMXk7Yk/w7hgpPDbWShs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=YUrGheo4; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="YUrGheo4" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 252814E4202A; Fri, 9 Jan 2026 17:18:37 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id E8E14606C6; Fri, 9 Jan 2026 17:18:36 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7AE04103C89B7; Fri, 9 Jan 2026 18:18:35 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767979116; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=H4b/jihKaaRHLMkQa+3eYNM0Q4yLDy5j6pgAhk5XWgM=; b=YUrGheo4NfMN+KwLPa9bufow95Bh6nbD05IRmxzugQI757sJkTwatnZbQgPrm9npkUFx08 v5skf33y2p6bMeTPsAcJ5yNhHnv6H9SJOJYq+nAEg106k1T0jiq0qH0bIKNWRPpD25EWVw eQKeSss0SRyHfnHInRV/dlds3xuB0WY7ktwNWSuGTStrxcEQxd3Pel6YxuzfblOreU5kV9 Ae21h5TaNClqk3vgECGA8YPnEAY4Dkgi282kEhNMxqmKcLzjv/HcImRZfE1ffP+7EovBe9 LmixS/h0zKsi4IKFL0JYOAk4PJ9CQ7kXVP2vC1YlCDdkicpygNcGMm/M9kVsMg== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:13 +0100 Subject: [PATCH v2 15/27] mtd: spinand: macronix: Register vendor specific operation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-15-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Provide the Macronix specific "read ECC status register" operation so that the core can verify if it is supported by the controller before using it. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/macronix.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macroni= x.c index a847ea8f49a8..6b7cbcc6e287 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -47,6 +47,9 @@ static SPINAND_OP_VARIANTS(update_cache_variants, SPI_MEM_OP_DUMMY(1, 1), \ SPI_MEM_OP_DATA_IN(1, buf, 1)) =20 +static SPINAND_OP_VARIANTS(macronix_ops, + SPINAND_MACRONIX_READ_ECCSR_1S_0_1S(NULL)); + static struct spi_mem_op spinand_fill_macronix_read_eccsr_op(struct spinand_device *spinand, void *= valptr) { @@ -174,6 +177,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status)), SPINAND_INFO("MX35LF2GE4AB", @@ -195,6 +199,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_CONT_READ(macronix_set_cont_read), @@ -208,6 +213,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_CONT_READ(macronix_set_cont_read), @@ -278,6 +284,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status)), SPINAND_INFO("MX31UF1GE4BC", @@ -288,6 +295,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status)), =20 @@ -301,6 +309,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_HAS_QE_BIT | SPINAND_HAS_PROG_PLANE_SELECT_BIT | SPINAND_HAS_READ_PLANE_SELECT_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status)), SPINAND_INFO("MX35UF4G24AD", @@ -312,6 +321,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &update_cache_variants), SPINAND_HAS_QE_BIT | SPINAND_HAS_PROG_PLANE_SELECT_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, @@ -324,6 +334,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, @@ -336,6 +347,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_CONT_READ(macronix_set_cont_read), @@ -351,6 +363,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_HAS_QE_BIT | SPINAND_HAS_PROG_PLANE_SELECT_BIT | SPINAND_HAS_READ_PLANE_SELECT_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status)), SPINAND_INFO("MX35UF2G24AD", @@ -362,6 +375,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &update_cache_variants), SPINAND_HAS_QE_BIT | SPINAND_HAS_PROG_PLANE_SELECT_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, @@ -374,6 +388,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, @@ -386,6 +401,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_CONT_READ(macronix_set_cont_read), @@ -399,6 +415,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_CONT_READ(macronix_set_cont_read)), @@ -410,6 +427,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status)), SPINAND_INFO("MX35UF1G24AD", @@ -420,6 +438,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, @@ -432,6 +451,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_CONT_READ(macronix_set_cont_read), @@ -445,6 +465,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_CONT_READ(macronix_set_cont_read)), @@ -456,6 +477,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status)), SPINAND_INFO("MX3UF2GE4BC", @@ -466,6 +488,7 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, + SPINAND_INFO_VENDOR_OPS(¯onix_ops), SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status)), }; --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS 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s=dkim; t=1767979117; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=lnokEMFB4NwttnDPKwrpdjjcxdmg3b5O6SJBXL7NJ0s=; b=uiD8NIYzaeFDctQYhOWJnQb5qr6Y7NUQoL60Npic3ffuF6iUrJ3fJAWmWTJxoIYp72dheG gr+7OgafM9T50STuFGgMKNcnYcMG7NW5QX7OUhkTH+zdXBRgf+0hf/EdJ5Yu8KXweaeKkW fNqcq0oJYRQscOgAUbsijhM+p/CtDT213TxCkA1KMr+IStc+VTQb0a9Rq7cskzIBNqS0T2 zyxh9F6v4CwxRH5qCJGY9ZlsebSk77ZW83+MdBWghv1YVo9LBtqrVq3usPa+IoJtHUl3ma qsX6f105OSUxJgjP9lsjnGzfuUhMtD6A5xOEizlVL/xYFT14aEzbeQwbfC0XRA== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:14 +0100 Subject: [PATCH v2 16/27] mtd: spinand: winbond: Register W25N vendor specific operation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-16-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Provide the Winbond W25N specific "select target" operation to let the core verify it is supported by the controller before using it. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/winbond.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 3003ad7e83ee..36053f35ee5e 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -105,6 +105,9 @@ spinand_fill_winbond_write_vcr_op(struct spinand_device= *spinand, u8 reg, void * SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_OUT(1, buf, 1)) =20 +static SPINAND_OP_VARIANTS(winbond_w25_ops, + SPINAND_WINBOND_SELECT_TARGET_1S_0_1S(NULL)); + static struct spi_mem_op spinand_fill_winbond_select_target_op(struct spinand_device *spinand, void= *valptr) { @@ -497,6 +500,7 @@ static const struct spinand_info winbond_spinand_table[= ] =3D { &write_cache_variants, &update_cache_variants), 0, + SPINAND_INFO_VENDOR_OPS(&winbond_w25_ops), SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL), SPINAND_SELECT_TARGET(w25m02gv_select_target)), SPINAND_INFO("W25N02JW", /* high-speed 1.8V */ --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0310036AB53 for ; Fri, 9 Jan 2026 17:18:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979123; cv=none; b=s19IJEZAWB4bZEg+SWJ+4Se8OKwkVGVUc6PljWrKlkbp/hI8d75L6HGRAdSfK2ypSf144aBdQAJ+8AXg9icjuoMDPI8Ru3aSnQLViZh4JDszM22xGO3ScsUTi6cpBn0oCS4cZtEpK/RtQtpjR4NZ0SQobgybWjm46ACCfQGwAj4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979123; c=relaxed/simple; bh=Ox0L1v3HiExI92/LUH/7t9BvWEIu09FtfkVzm2QMYtE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Yrn4CTEGqiwRGldgh4WzDBY0Q33yVqPVWhPdZ+1J6a9rJ7IABOJ6CgecNQj1IL6+SNM+Bpe2jtRJbU13d7rE4/+tfeq6fNgEiQaK3ydOZ8icfZhdbr1+JvNJ5kELyZSVidyeyFbg3tmE2F3sI3vRidGnxf6cxRP8NYG9hAD614Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=tbS1LKI/; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="tbS1LKI/" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 5DACCC1F6E4; Fri, 9 Jan 2026 17:18:13 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id A63B7606C6; Fri, 9 Jan 2026 17:18:39 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id BE8B1103C89B9; Fri, 9 Jan 2026 18:18:37 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767979118; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=ms4xzKXIpxyRYeFBoWeTIh6rA/J+YRqZaN/VfApNv70=; b=tbS1LKI/eb73Y9y03PSO8xpC3djkLri3PDl7xXIvP1Zx3T/6F966i52Zcsn2Dp759d+kcq rZySUp63Lg6ISx9Hc6Bba4pcTKmZtMRMNbB4QbD1UkiAXxMrTU0/Ba6aJxC7EohTN53XZo mrHBXUOKVKH0SkgYLjmbKePb+Tl6XQ4w1okHaaa2bExxLdxgptZj1gWen+wxFzIOaBkNVD xC7eZlEd/rcFdO0aDxyHdNINZd5b4nfrhkDPCt/DZWazHhLPVXStilcnMXjubY7CHQXMCI LQ1ckWE/F0UqRqpYNhP11KVV6U/OOcw29Tozmq5wEAUm1bWXVYNXWDZIcXa+7w== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:15 +0100 Subject: [PATCH v2 17/27] mtd: spinand: winbond: Register W35N vendor specific operation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-17-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Provide the Winbond W35N specific "write VCR register" operation to let the core verify it is supported by the controller before using it. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/winbond.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 36053f35ee5e..1c13dba08369 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -93,6 +93,9 @@ static SPINAND_OP_VARIANTS(update_cache_variants, SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_OUT(1, buf, 1)) =20 +static SPINAND_OP_VARIANTS(winbond_w35_ops, + SPINAND_WINBOND_WRITE_VCR_1S_1S_1S(0, NULL)); + static struct spi_mem_op spinand_fill_winbond_write_vcr_op(struct spinand_device *spinand, u8 reg, = void *valptr) { @@ -469,6 +472,7 @@ static const struct spinand_info winbond_spinand_table[= ] =3D { &write_cache_octal_variants, &update_cache_octal_variants), 0, + SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops), SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL), SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg)), SPINAND_INFO("W35N02JW", /* 1.8V */ @@ -479,6 +483,7 @@ static const struct spinand_info winbond_spinand_table[= ] =3D { &write_cache_octal_variants, &update_cache_octal_variants), 0, + SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops), SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL), SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg)), SPINAND_INFO("W35N04JW", /* 1.8V */ @@ -489,6 +494,7 @@ static const struct spinand_info winbond_spinand_table[= ] =3D { &write_cache_octal_variants, &update_cache_octal_variants), 0, + SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops), SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL), SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg)), /* 2G-bit densities */ --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7BDB36AB6A for ; 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bh=W6+rvBQGeoJcUuTU/Yf2GkJyCdo7KGLjvhpSVmkvjVc=; b=zMOUPjUAOqspSfsNt505s/8CA2O3cgcgg8yJCBsN+gMIijYLK6nlXFTeUmqT3tq1D9Wh6A BhfsXxv6b8HY5BBvdrUTKIIZ+auAQ0KLBLns82N4viG+TPr3cfVgIlS66v6U6b/SQoETgv E91jKZnLJZSxx06pWa+IspmvDc6U8GzKa6PJIdG21vI6K4LtR0hf1X3DcLqnQxxV6ogv6Y NfNj91UfwCAayJnH+iASo0wasO8/XiI+DG6BRHmLuRm35hvdea5CpuKxdF+a6wGA0YTE9I A2MaLXI2gbxl17zh+xOMJdJMQqYWypR+alewZYZhV6sbdv4V/5+svwg9Tm4GSA== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:16 +0100 Subject: [PATCH v2 18/27] mtd: spinand: winbond: Fix style Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-18-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add a missing new line in the middle of the driver. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/winbond.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 1c13dba08369..7eade2251f7b 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -408,6 +408,7 @@ static int w35n0xjw_vcr_cfg(struct spinand_device *spin= and) default: return -EINVAL; } + ret =3D w35n0xjw_write_vcr(spinand, W35N01JW_VCR_DUMMY_CLOCK_REG, dummy_c= ycles); if (ret) return ret; --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E69736AB79 for ; Fri, 9 Jan 2026 17:18:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979125; cv=none; b=qK830hcTbNKO7lQdZSs9/M3A5s+Yu8nxeYAvzheLpmbscwqrQcGK0n6pLG1nYDsBv93avxjJZz2TjQ5AdYKBma9s86cZ/It9yxmgJUS3+g9fSo01krKd6SmS7yf6eUi9T3HMSwAqhqHXe2bBno8Pjjs2i2kf3qShBbY7xC6O7iI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979125; c=relaxed/simple; bh=BV8D7nBZkFVhYpQyKB0DGYiE68OVjWx/XnDOI3/F8wY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=D+9qdQWzcLk2oLO7crgfjr3wbm4bvWcKR7K1RfFuD/NJrsjQv2gE2VVvuNGwcvmzNggSL0TM4GAakNDiufRHHK+CCxRKaxgdNuWgHNQ9bUG1bqMutQnqS1tiylfP3a8elXRCeyUV5P6/OA4Bjmwklw+1efHV4TQ7Xt5bFwgj4NE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=V8rJzHi9; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="V8rJzHi9" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 2EEF11A2752; Fri, 9 Jan 2026 17:18:42 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 0426D606C6; Fri, 9 Jan 2026 17:18:42 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 542E4103C89BB; Fri, 9 Jan 2026 18:18:40 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767979121; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=6HYIcnqwyFWxHq3DkqAqIbtZT7IZvCykXnPBw3eNAvA=; b=V8rJzHi926cmEs6Gy53noktAnngb4K3uRi6ofuWB8Sort6rU+WndQ4GbUql4ZuEhdOvnIZ y8u5z9GJePmW3A+ZiCM8ABQcD+dJsZkUP8BLZM2agaakpgN+xl7sMisaV9fJTd2cXImy9b Mdt0G8FFASpZuEKnBn9+InEVZvpAv4l2mQaeZhacHXfnKmR7nrqnvEMjzznV10QNWWJ89+ nkEvX7DZuK3NgWDSkPNfVv6+vaxdjCOPP0sMlxA1nWo0h2xjWrKq6QuDJfbUqT1josmX8u lYP2M8i3FCFE55oqTSj/ADsqA/UqZjTJYJfBkcb23UAdhDVj/QGgWsq1EfMZIg== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:17 +0100 Subject: [PATCH v2 19/27] mtd: spinand: winbond: Rename IO_MODE register macro Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-19-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Suffix the macro name with *_REG to align with the rest of the driver. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/winbond.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 7eade2251f7b..b16963637683 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -22,7 +22,7 @@ #define W25N0XJW_SR4 0xD0 #define W25N0XJW_SR4_HS BIT(2) =20 -#define W35N01JW_VCR_IO_MODE 0x00 +#define W35N01JW_VCR_IO_MODE_REG 0x00 #define W35N01JW_VCR_IO_MODE_SINGLE_SDR 0xFF #define W35N01JW_VCR_IO_MODE_OCTAL_SDR 0xDF #define W35N01JW_VCR_IO_MODE_OCTAL_DDR_DS 0xE7 @@ -392,7 +392,7 @@ static int w35n0xjw_vcr_cfg(struct spinand_device *spin= and) else return -EINVAL; =20 - ret =3D w35n0xjw_write_vcr(spinand, W35N01JW_VCR_IO_MODE, io_mode); + ret =3D w35n0xjw_write_vcr(spinand, W35N01JW_VCR_IO_MODE_REG, io_mode); if (ret) return ret; =20 --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD70036B060 for ; Fri, 9 Jan 2026 17:18:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979126; cv=none; b=pahsRaV/60InxeZ1kAZRE+iNx2gqz/dlc2CiDt5rYRVm86yJ2QsCJpsfR4ejqAUU+HRg18PsaLnW/qJ2tuIuSOYXtiJ6cK0nuTB0Nz133YnVZvoXj8QQCesxg1s64dZvLX6kRPKn7yjrNozy7mlrPA8q9BEd9g49v87T/akh1Yg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979126; c=relaxed/simple; bh=s5DqMiIYKdUfxWUAhN4RGGYA4fqft2YfnmGn93p+UVQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ITN9VOyUUbGQurb83AWbCJH5RVq4nVsGQfuqxnxGdgjCUIqIXI3p5ElgP5MYb/J/vMJw7CDv3nBzafho5f94tDLbNxY2hqEARUb6+j6XrPelC+baN8EV+hKJ3e+C8Bc5+5LJ9MzfNo2IwkQKZppwW1Necb9DdPno+H4eX/wSVzg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=VsVf09XI; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="VsVf09XI" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id E3BABC1F6E5; Fri, 9 Jan 2026 17:18:16 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 38D1E606C6; Fri, 9 Jan 2026 17:18:43 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 99992103C89BE; Fri, 9 Jan 2026 18:18:41 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767979122; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=MJtnWz64Xe2CigN2SsqL9dz4pY2jKcHax/iVWEjwuVE=; b=VsVf09XIYY2kdVeC7p8aVeJhhXqg3JjokyNXGBN/qHn+C8TZq/tt9kVF8GKjfzrTja2L49 ObuMZwLg6icAY8fW1jwM8TCNfKPkvcWs4PqikhCyUD+7fqYCE/mjiTLzwBfYEQGICfoQb7 LHVUj0tVRQ0O9Y3pZypA10d2LigK45IrsM87PfSQj9Lr2H/chB6Ct017Vm/mDMM/tHHAzI OmF7aL5DFTrSBB1621r+FS+UtY4TCk869vywmaiZB/zZc629UUxlIn1LxHE21ThmJa4SYC M0XEXdCHeuIgfp7NjC8xu/6zHpYF2N9bWBYd0E8O8oe/MY+vEVJGz2kvP619Dw== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:18 +0100 Subject: [PATCH v2 20/27] mtd: spinand: winbond: Configure the IO mode after the dummy cycles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-20-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 When we will change the bus interface, the action that actually performs the transition is the IO mode register write. This means after the IO mode register write, we should use the new bus interface. But the ->configure_chip() hook itself is not responsible of making this change official, it is the caller that must act according to the return value. Reorganize this helper to first configure the dummy cycles before possibly switching to another bus interface. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/winbond.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index b16963637683..1d79a8ae7920 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -381,21 +381,6 @@ static int w35n0xjw_vcr_cfg(struct spinand_device *spi= nand) =20 op =3D spinand->op_templates->read_cache; =20 - single =3D (op->cmd.buswidth =3D=3D 1 && op->addr.buswidth =3D=3D 1 && op= ->data.buswidth =3D=3D 1); - dtr =3D (op->cmd.dtr || op->addr.dtr || op->data.dtr); - if (single && !dtr) - io_mode =3D W35N01JW_VCR_IO_MODE_SINGLE_SDR; - else if (!single && !dtr) - io_mode =3D W35N01JW_VCR_IO_MODE_OCTAL_SDR; - else if (!single && dtr) - io_mode =3D W35N01JW_VCR_IO_MODE_OCTAL_DDR; - else - return -EINVAL; - - ret =3D w35n0xjw_write_vcr(spinand, W35N01JW_VCR_IO_MODE_REG, io_mode); - if (ret) - return ret; - dummy_cycles =3D ((op->dummy.nbytes * 8) / op->dummy.buswidth) / (op->dum= my.dtr ? 2 : 1); switch (dummy_cycles) { case 8: @@ -413,6 +398,21 @@ static int w35n0xjw_vcr_cfg(struct spinand_device *spi= nand) if (ret) return ret; =20 + single =3D (op->cmd.buswidth =3D=3D 1 && op->addr.buswidth =3D=3D 1 && op= ->data.buswidth =3D=3D 1); + dtr =3D (op->cmd.dtr && op->addr.dtr && op->data.dtr); + if (single && !dtr) + io_mode =3D W35N01JW_VCR_IO_MODE_SINGLE_SDR; + else if (!single && !dtr) + io_mode =3D W35N01JW_VCR_IO_MODE_OCTAL_SDR; + else if (!single && dtr) + io_mode =3D W35N01JW_VCR_IO_MODE_OCTAL_DDR; + else + return -EINVAL; + + ret =3D w35n0xjw_write_vcr(spinand, W35N01JW_VCR_IO_MODE_REG, io_mode); + if (ret) + return ret; + return 0; } =20 --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19B85366DAC; Fri, 9 Jan 2026 17:18:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979127; cv=none; b=ovpmqVgXqaeOj/k5P+waahdHXOrvz5BH+dGEEpamPLRtD/Es7nmdBQp/Z481w7vFg/WRZo6/S++hyI3V9zpLonsEOwBZQbEI19damXCGuLo5fmLD7avBH0GXNt/n6Twhn1gzv/PhYyE/+ofi/bwNZqxQBXzoZQ1KZqBdP1GBVAs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979127; c=relaxed/simple; bh=ZBa9WI9sNZf/R3HFBY0G831aCKS+wM03PWRWgU0Aikk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pfBYQVLJR1Ik0vhWevdvDitGjEtRW/xVbgIHq3BoMFEau1wI9EpUzZfjSS0FLSE8BQEBfoitJX6BopIqsy8fKUWOI2Q5fzFB3AwPx54d30BZ45T68TrcpVt2SdC+JwONmUTy+DzpLFFHimAbMQJ+gZymENZbqiWmrnuDVgJqHZY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=2GWdC6RF; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="2GWdC6RF" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id B0FE84E4202B; Fri, 9 Jan 2026 17:18:44 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 89E25606C6; Fri, 9 Jan 2026 17:18:44 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id D1BBA103C89BD; Fri, 9 Jan 2026 18:18:42 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767979123; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=71VfqlwpnO88b/BySfbu5HhBv3rjVPZdc4UiUGls3+g=; b=2GWdC6RFF/oN61uiGb0U2Bfk6QtlTupk4CCJ0UftEV2hk0MCSwA5glgEp3PMl2sI6bZVai cFI8myiIMfCBF7H4m8iJKjTEz4zmN7Se4ua7TEr4wsGgN/pUIFmQxrONiS4U7WVk8Wbfjw nI3WgT2zIjTkpGfQ/id93LVlU8/4ywafoyphM20J7wYcARplx+fMsOOCM5vF/EwySwAwqK x4Nj4vIdOCf/QVJ8POdb5FGYGXKC1GjR7qxlXFI5U94zmx1nfYRgywARbIXYEvXHX3E84w QPBWJPGZrbNmvv+5vCXb6C+77YSToZOC2XCCwSGt3QUUc7HvSUo0wBG7kpkW4Q== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:19 +0100 Subject: [PATCH v2 21/27] mtd: spinand: Gather all the bus interface steps in one single function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-21-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Writing the quad enable bit in one helper and doing the chip configuration in another does not make much sense from a bus interface setup point of view. Instead, let's create a broader helper which is going to be in charge of all the bus configuration steps at once. This will specifically allow to transition to octal DDR mode, and even fallback to quad (if suppoorted) or single mode otherwise. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/core.c | 62 +++++++++++++++++++++++++++--------------= ---- 1 file changed, 37 insertions(+), 25 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 88d87a96ddb0..54a32cea3755 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -261,18 +261,9 @@ static int spinand_init_cfg_cache(struct spinand_devic= e *spinand) return 0; } =20 -static int spinand_init_quad_enable(struct spinand_device *spinand) +static int spinand_init_quad_enable(struct spinand_device *spinand, + bool enable) { - bool enable =3D false; - - if (!(spinand->flags & SPINAND_HAS_QE_BIT)) - return 0; - - if (spinand->op_templates->read_cache->data.buswidth =3D=3D 4 || - spinand->op_templates->write_cache->data.buswidth =3D=3D 4 || - spinand->op_templates->update_cache->data.buswidth =3D=3D 4) - enable =3D true; - return spinand_upd_cfg(spinand, CFG_QUAD_ENABLE, enable ? CFG_QUAD_ENABLE : 0); } @@ -1391,12 +1382,6 @@ static int spinand_manufacturer_init(struct spinand_= device *spinand) return ret; } =20 - if (spinand->configure_chip) { - ret =3D spinand->configure_chip(spinand); - if (ret) - return ret; - } - return 0; } =20 @@ -1602,6 +1587,31 @@ static int spinand_detect(struct spinand_device *spi= nand) return 0; } =20 +static int spinand_configure_chip(struct spinand_device *spinand) +{ + bool quad_enable =3D false; + int ret; + + if (spinand->flags & SPINAND_HAS_QE_BIT) { + if (spinand->ssdr_op_templates.read_cache->data.buswidth =3D=3D 4 || + spinand->ssdr_op_templates.write_cache->data.buswidth =3D=3D 4 || + spinand->ssdr_op_templates.update_cache->data.buswidth =3D=3D 4) + quad_enable =3D true; + } + + ret =3D spinand_init_quad_enable(spinand, quad_enable); + if (ret) + return ret; + + if (spinand->configure_chip) { + ret =3D spinand->configure_chip(spinand); + if (ret) + return ret; + } + + return ret; +} + static int spinand_init_flash(struct spinand_device *spinand) { struct device *dev =3D &spinand->spimem->spi->dev; @@ -1612,10 +1622,6 @@ static int spinand_init_flash(struct spinand_device = *spinand) if (ret) return ret; =20 - ret =3D spinand_init_quad_enable(spinand); - if (ret) - return ret; - ret =3D spinand_upd_cfg(spinand, CFG_OTP_ENABLE, 0); if (ret) return ret; @@ -1628,19 +1634,25 @@ static int spinand_init_flash(struct spinand_device= *spinand) return ret; } =20 + ret =3D spinand_configure_chip(spinand); + if (ret) + goto manuf_cleanup; + /* After power up, all blocks are locked, so unlock them here. */ for (i =3D 0; i < nand->memorg.ntargets; i++) { ret =3D spinand_select_target(spinand, i); if (ret) - break; + goto manuf_cleanup; =20 ret =3D spinand_lock_block(spinand, BL_ALL_UNLOCKED); if (ret) - break; + goto manuf_cleanup; } =20 - if (ret) - spinand_manufacturer_cleanup(spinand); + return 0; + +manuf_cleanup: + spinand_manufacturer_cleanup(spinand); =20 return ret; } --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 396FD36C0C9; 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arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="qFAxyJAM" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 174071A2753; Fri, 9 Jan 2026 17:18:46 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id E1D25606C6; Fri, 9 Jan 2026 17:18:45 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 2E61B103C89AB; Fri, 9 Jan 2026 18:18:44 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767979125; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=B1lJ7HTagSCXQak24k+E5wMJF7OUHHqDYZn/cpX8YLs=; b=qFAxyJAMLb9dmFmKXyEEX6aOVWiaZsvLf/JgV8Nu5MS2v0FWtQj5sUmWamEm8tqYjjdeDG RKPO/cdOiIdLVV/tFca8S+hzonDigZUasYPfCMo1egKvLX0DkeaaInf2k8OgCrS9jWZfeg yAqqMnmkWfo5UJHHhgR1ov+2Tm8VWKjPCNWpDLwHDrxx/jHzM8Ija3m5epByh+dkY5pytf 2seIAYysMfVNLj0vPPSmzakb3OZ3EMfyGxm+AY8mZIjexLb3o2Sy/PZyyuiXqByl2O3lt9 Y+2Ma7V+ixBNl2rQefpZ2A5U1lBaB9gHGCCj0mjDZruhLQbo+WW2b02UGwS2eg== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:20 +0100 Subject: [PATCH v2 22/27] mtd: spinand: Add support for setting a bus interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-22-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Create a bus interface enumeration, currently only containing the one we support: SSDR, for single SDR, so any operation whose command is sent over a single data line in SDR mode, ie. any operation matching 1S-XX-XX. The main spinand_device structure gets a new parameter to store this enumeration, for now unused. Of course it is set to SSDR during the SSDR templates initialization to further clarify the state we are in at the moment. This member is subject to be used to know in which bus configuration we and be updated by the core when we switch to faster mode(s). Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/core.c | 1 + include/linux/mtd/spinand.h | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 54a32cea3755..a5166b49020c 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1406,6 +1406,7 @@ static void spinand_init_ssdr_templates(struct spinan= d_device *spinand) tmpl->page_read =3D (struct spi_mem_op)SPINAND_PAGE_READ_1S_1S_0_OP(0); tmpl->prog_exec =3D (struct spi_mem_op)SPINAND_PROG_EXEC_1S_1S_0_OP(0); spinand->op_templates =3D &spinand->ssdr_op_templates; + spinand->bus_iface =3D SSDR; } =20 static int spinand_support_vendor_ops(struct spinand_device *spinand, diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 88871287c739..027923841bba 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -481,6 +481,14 @@ struct spinand_user_otp { const struct spinand_user_otp_ops *ops; }; =20 +/** + * enum spinand_bus_interface - SPI NAND bus interface types + * @SSDR: Bus configuration supporting all 1S-XX-XX operations, including = dual and quad + */ +enum spinand_bus_interface { + SSDR, +}; + /** * struct spinand_info - Structure used to describe SPI NAND chips * @model: model name @@ -643,6 +651,7 @@ struct spinand_mem_ops { * @flags: NAND flags * @ssdr_op_templates: Templates for all single SDR SPI mem operations * @op_templates: Templates for all SPI mem operations + * @bus_iface: Current bus interface * @select_target: select a specific target/die. Usually called before sen= ding * a command addressing a page or an eraseblock embedded in * this die. Only required if your chip exposes several dies @@ -678,6 +687,7 @@ struct spinand_device { =20 struct spinand_mem_ops ssdr_op_templates; struct spinand_mem_ops *op_templates; + enum spinand_bus_interface bus_iface; =20 struct spinand_dirmap *dirmaps; =20 --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95C8E36AB79; Fri, 9 Jan 2026 17:18:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979132; cv=none; b=kLI35GFZucT2SB4sm9q6bvvcaPmfyiHCmGGw4V6pr/bj3znBog4s4IyP1vW4zqjs7NtYMxdh4/gOGjGwEaQFF/5bxKxJOeuaImn/in33WbBwGYpkDoOpQvUFjM4u0/RGniGzoAu/f6GB7I29S4sPPDPiSR1XzBNKiQ5DISds3oI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979132; c=relaxed/simple; bh=WrdVrZoKVo7gsw1pCH6PG6OXJObCz4MraKoZETSmsB8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eKLDEefXgaM9kBmc7/EAutb4DEd+VzefEMouMQeXdMavB5c1Zr+qmHMTsNzAKbnX5JorMk/jXtOscHdLbW5S/wlStVBN3sGkrVERLXLD5/f7kekF1OzTJDVIEi8pU3JUNV+B3UkTXuG/94J3OLdfKg47I7pWAb/oir1huvDAsQ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=BBiadMXg; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="BBiadMXg" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id E7E77C1F6E5; Fri, 9 Jan 2026 17:18:22 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 3BC3C606C6; Fri, 9 Jan 2026 17:18:49 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 6BEDC103C89B1; Fri, 9 Jan 2026 18:18:45 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767979126; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=TvT8KJbAI4+CbX9ktmIBaXAw+sBQzrpvbOewgKo4BbY=; b=BBiadMXgp6XHU8+FJoxBFnflrpev8GygXL88DIWVtos0GJ1ahXR6wjXBRtB8KY81GcfEDD bQpszt8t7P06j2ql7IHAauo4wdTboUW8rQWyJKyGu5Kh9AGTpU5foLBlLlNydaJns3L6aP MXihlzvvN+v5LXlOhA9skPEikY5Mtd2oWXPPNzVfWUXw2jGTyz142C032OxWXshpoSZAhM D0uFefBJCi3j+CZW812mVmr+BCYSktX5nzG3fOh5g40BpVJG1JymH7uoHdB+2QxxO+j4ew 7RIWpo8W6iHgFpBVX/P43Ivn5lQgGkCq58p/LAZ/81KFzm/UlUeX6K3eASwxXQ== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:21 +0100 Subject: [PATCH v2 23/27] mtd: spinand: Propagate the bus interface across core helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-23-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 For now all drivers provide SSDR variants only. When we add support for ODTR modes, there will be a need to differentiate the type of variant we target as well as the need to check if we support one or the other type of operations. Pass this parameter to lower level helpers, which for now is unused, in order to simplify the patch introducing ODTR support. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/core.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index a5166b49020c..019594182c60 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1410,7 +1410,8 @@ static void spinand_init_ssdr_templates(struct spinan= d_device *spinand) } =20 static int spinand_support_vendor_ops(struct spinand_device *spinand, - const struct spinand_info *info) + const struct spinand_info *info, + enum spinand_bus_interface iface) { int i; =20 @@ -1431,7 +1432,7 @@ static int spinand_support_vendor_ops(struct spinand_= device *spinand, } =20 static const struct spi_mem_op * -spinand_select_op_variant(struct spinand_device *spinand, +spinand_select_op_variant(struct spinand_device *spinand, enum spinand_bus= _interface iface, const struct spinand_op_variants *variants) { struct nand_device *nand =3D spinand_to_nand(spinand); @@ -1524,28 +1525,28 @@ int spinand_match_and_init(struct spinand_device *s= pinand, spinand->read_retries =3D table[i].read_retries; spinand->set_read_retry =3D table[i].set_read_retry; =20 - op =3D spinand_select_op_variant(spinand, + op =3D spinand_select_op_variant(spinand, SSDR, info->op_variants.read_cache); if (!op) return -EOPNOTSUPP; =20 spinand->ssdr_op_templates.read_cache =3D op; =20 - op =3D spinand_select_op_variant(spinand, + op =3D spinand_select_op_variant(spinand, SSDR, info->op_variants.write_cache); if (!op) return -EOPNOTSUPP; =20 spinand->ssdr_op_templates.write_cache =3D op; =20 - op =3D spinand_select_op_variant(spinand, + op =3D spinand_select_op_variant(spinand, SSDR, info->op_variants.update_cache); if (!op) return -EOPNOTSUPP; =20 spinand->ssdr_op_templates.update_cache =3D op; =20 - ret =3D spinand_support_vendor_ops(spinand, info); + ret =3D spinand_support_vendor_ops(spinand, info, SSDR); if (ret) return ret; =20 --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2893E36C0DB; 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bh=XWoEYvW6UTkurEFnLt3TZWYNsLRXIKXbu8O7GL39Atk=; b=m1OjgYCJbE2Pt2/lIyPBAsS4bjN0OHbj4JHexQn2QnPGFzjTwVJtplLDPTv7YhDgvoVlQY ACYBqHLhHZSEP5nwVZ5Qm+6jQMYr1otMoKeHa2Jm/gFsxfa7kLfl5i/NfWasWI8TPKp38v YM7FvLRH27QVf7MSbifvh8f9qCkh0fAbk3uPrVG0CKXtLzyPTZz4tw/KW4nV7xbbirB1SM 1CDstgICLGMiluRNIZ6bJBe9wJLyRyjMw4y4nuRMjCmzd4VXuz94fSm4hD+9FCqiuYQtbt 0XUT3ZPDpSObp/P80TkoRXJyaITrZH9JWHFTY0biXxT/4vQyljqda+Hdk3/XKg== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:22 +0100 Subject: [PATCH v2 24/27] mtd: spinand: Give the bus interface to the configuration helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-24-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The chip configuration hook is the one responsible to actually switch the switch between bus interfaces. It is natural to give it the bus interface we expect with a new parameter. For now the only value we can give is SSDR, but this is subject to change in the future, so add a bit of extra logic in the implementations of this callback to make sure both the core and the chip driver are aligned on the request. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/core.c | 2 +- drivers/mtd/nand/spi/winbond.c | 28 +++++++++++++++++++++------- include/linux/mtd/spinand.h | 6 ++++-- 3 files changed, 26 insertions(+), 10 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 019594182c60..1ac1d0181a91 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1606,7 +1606,7 @@ static int spinand_configure_chip(struct spinand_devi= ce *spinand) return ret; =20 if (spinand->configure_chip) { - ret =3D spinand->configure_chip(spinand); + ret =3D spinand->configure_chip(spinand, SSDR); if (ret) return ret; } diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 1d79a8ae7920..419f4303a0dc 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -311,13 +311,17 @@ static int w25n02kv_ecc_get_status(struct spinand_dev= ice *spinand, return -EINVAL; } =20 -static int w25n0xjw_hs_cfg(struct spinand_device *spinand) +static int w25n0xjw_hs_cfg(struct spinand_device *spinand, + enum spinand_bus_interface iface) { const struct spi_mem_op *op; bool hs; u8 sr4; int ret; =20 + if (iface !=3D SSDR) + return -EOPNOTSUPP; + op =3D spinand->op_templates->read_cache; if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) hs =3D false; @@ -371,17 +375,25 @@ static int w35n0xjw_write_vcr(struct spinand_device *= spinand, u8 reg, u8 val) return 0; } =20 -static int w35n0xjw_vcr_cfg(struct spinand_device *spinand) +static int w35n0xjw_vcr_cfg(struct spinand_device *spinand, + enum spinand_bus_interface iface) { - const struct spi_mem_op *op; + const struct spi_mem_op *ref_op; unsigned int dummy_cycles; bool dtr, single; u8 io_mode; int ret; =20 - op =3D spinand->op_templates->read_cache; + switch (iface) { + case SSDR: + ref_op =3D spinand->ssdr_op_templates.read_cache; + break; + default: + return -EOPNOTSUPP; + }; =20 - dummy_cycles =3D ((op->dummy.nbytes * 8) / op->dummy.buswidth) / (op->dum= my.dtr ? 2 : 1); + dummy_cycles =3D ((ref_op->dummy.nbytes * 8) / ref_op->dummy.buswidth) / + (ref_op->dummy.dtr ? 2 : 1); switch (dummy_cycles) { case 8: case 12: @@ -398,8 +410,10 @@ static int w35n0xjw_vcr_cfg(struct spinand_device *spi= nand) if (ret) return ret; =20 - single =3D (op->cmd.buswidth =3D=3D 1 && op->addr.buswidth =3D=3D 1 && op= ->data.buswidth =3D=3D 1); - dtr =3D (op->cmd.dtr && op->addr.dtr && op->data.dtr); + single =3D (ref_op->cmd.buswidth =3D=3D 1 && + ref_op->addr.buswidth =3D=3D 1 && + ref_op->data.buswidth =3D=3D 1); + dtr =3D (ref_op->cmd.dtr && ref_op->addr.dtr && ref_op->data.dtr); if (single && !dtr) io_mode =3D W35N01JW_VCR_IO_MODE_SINGLE_SDR; else if (!single && !dtr) diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 027923841bba..b7eb3eceb138 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -529,7 +529,8 @@ struct spinand_info { const struct spinand_op_variants *vendor_ops; int (*select_target)(struct spinand_device *spinand, unsigned int target); - int (*configure_chip)(struct spinand_device *spinand); + int (*configure_chip)(struct spinand_device *spinand, + enum spinand_bus_interface iface); int (*set_cont_read)(struct spinand_device *spinand, bool enable); struct spinand_fact_otp fact_otp; @@ -704,7 +705,8 @@ struct spinand_device { const struct spinand_manufacturer *manufacturer; void *priv; =20 - int (*configure_chip)(struct spinand_device *spinand); + int (*configure_chip)(struct spinand_device *spinand, + enum spinand_bus_interface iface); bool cont_read_possible; int (*set_cont_read)(struct spinand_device *spinand, bool enable); --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 637A036C0D1 for ; Fri, 9 Jan 2026 17:18:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979136; cv=none; b=R9o4sMEDK36TomQDTRmcJLwUVlS5w74f6lvXjqU/fcYOoQCLrZd+REUU+mBP/LHmtRS63vtfYW5kNpvs7nkwgvxsS+zSo+d06/D7RFTBpYW1nozLc4yNVQKlCtU3D87biaNeVCJcjLhH63tBuXT53sq/EyPq2JS+KYc7c/dwMWk= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-25-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Both Macronix and Winbond have chip specific operations which are SSDR only. Trying to use them in an ODTR setup will fail and doing this is a pure software bug. Warn explicitly in this case. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/macronix.c | 2 ++ drivers/mtd/nand/spi/winbond.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macroni= x.c index 6b7cbcc6e287..84be5e0402b5 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -53,6 +53,8 @@ static SPINAND_OP_VARIANTS(macronix_ops, static struct spi_mem_op spinand_fill_macronix_read_eccsr_op(struct spinand_device *spinand, void *= valptr) { + WARN_ON_ONCE(spinand->bus_iface !=3D SSDR); + return (struct spi_mem_op)SPINAND_MACRONIX_READ_ECCSR_1S_0_1S(valptr); } =20 diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 419f4303a0dc..90e4ece00cf5 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -114,6 +114,8 @@ static SPINAND_OP_VARIANTS(winbond_w25_ops, static struct spi_mem_op spinand_fill_winbond_select_target_op(struct spinand_device *spinand, void= *valptr) { + WARN_ON_ONCE(spinand->bus_iface !=3D SSDR); + return (struct spi_mem_op)SPINAND_WINBOND_SELECT_TARGET_1S_0_1S(valptr); } =20 --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CF9A368291 for ; Fri, 9 Jan 2026 17:18:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979137; cv=none; b=L3Gg7IvqEGEzzI5Ay5dZNFQ0wDzKfbblOwMPKtn1vyCRtlepEDYFw1XyvYHY6EC+sJEg4fsMF1NvWH8o3+tWy7I5cXGqPuGVJUvmdKL/PGkxGEImyajfyCOsSkHBz6uWV2KxNWlDiIOgcF9URimtS4Mzs3JQr+VFLKY/Mme4nFg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979137; c=relaxed/simple; bh=Ck66NbxnHoY/dJ5n6YWd09rdI8MKEX0Wdpsh7JS+qZg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bMX4UyFwRFnv6NhQa2nDs9ZsAUCrY3Uf66yGxkSzvKBiunASC792kXzc5pL2Pa8WCasbQOTHQ06ntT9qKAr+pk44IOUKcvaqXVXObOIzcYXQMDBCICdRuzVllcjb9RPIZSd9SMByv4J/eP2ORESly5etonI9UccejY0ZQXJkt34= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=h6Hxf9RF; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="h6Hxf9RF" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 21F7DC1F6E4; Fri, 9 Jan 2026 17:18:27 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 69A19606C6; Fri, 9 Jan 2026 17:18:53 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A7D36103C89AD; Fri, 9 Jan 2026 18:18:51 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767979132; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=neklhWF9Sg2eyfEOKn2xQ0FrpcEjSrtWyZMej8TTw7I=; b=h6Hxf9RFggVUKiGmkEU9Oa0WuchAe/mhHHO/U92LClWZAv+vHE4jxtxpRqJVvLPXVdKIvV esUvh1Je7PAYAHFthIMBD8xssvCH3twWgjIu4E7JkiVNilGRjXEu5E4XBRXpjQ2HPjKOWS TSPx24VaurL/qFJOUekxvv3kc15KMt1E/6YFvnPPF4JaZ8kbO/7mAuq7DGNhKtyvCOei58 vVnwANeix7HoQZfbEHUFLHqd7xcwWtLJTj+R81mgKiM3IG2aSErK/tx4yEfnV2uGpmIWEO Ndf2yUvluYpyLps0cd5XgKc5hCZdEMBuz3RfA5/2w2dYuelGOC7dYdoF/8lfMQ== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:24 +0100 Subject: [PATCH v2 26/27] mtd: spinand: Add octal DTR support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-26-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Create a new bus interface named ODTR for "octal DTR", which matches the following pattern: 8D-8D-8D. Add octal DTR support for all the existing core operations. Add a second set of templates for this bus interface. Give the possibility for drivers to register their read, write and update cache variants as well as their vendor specific operations. Check the SPI controller driver supports all the octal DTR commands that we might need before switching to the ODTR bus interface. Make the switch by calling ->configure_chip() with the ODTR parameter. Fallback in case this step fails. If someone ever attempts to suspend a chip in octal DTR mode, there are changes that it will loose its configuration at resume. Prevent any problem by explicitly switching back to SSDR while suspending. Note: there is a limitation in the current approach, page I/Os are not available as the dirmaps will be created for the ODTR bus interface if that option is supported and not switched back to SSDR during suspend. Switching them is possible but would be costly and would not bring anything as right after resuming we will switch again to ODTR. In case this capability is used for debug, developpers should mind to destroy and recreate suitable direct mappings. Finally, as a side effect, we increase the buffer for reading IDs to 6. No device at this point returns 6 bytes, but we support 5 bytes IDs, which means in octal DTR mode we have no other choice than reading an even number of bytes, hence 6. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/core.c | 140 ++++++++++++++++++++++++++++++++++++++++= +++- include/linux/mtd/spinand.h | 79 ++++++++++++++++++++++++- 2 files changed, 216 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 1ac1d0181a91..e1336859c600 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -57,6 +57,9 @@ spinand_fill_set_feature_op(struct spinand_device *spinan= d, u64 reg, const void { struct spi_mem_op op =3D spinand->op_templates->set_feature; =20 + if (op.cmd.dtr && op.cmd.buswidth =3D=3D 8) + reg |=3D reg << 8; + op.addr.val =3D reg; op.data.buf.out =3D valptr; =20 @@ -68,6 +71,9 @@ spinand_fill_get_feature_op(struct spinand_device *spinan= d, u64 reg, void *valpt { struct spi_mem_op op =3D spinand->op_templates->get_feature; =20 + if (op.cmd.dtr && op.cmd.buswidth =3D=3D 8) + reg |=3D reg << 8; + op.addr.val =3D reg; op.data.buf.in =3D valptr; =20 @@ -1392,6 +1398,11 @@ static void spinand_manufacturer_cleanup(struct spin= and_device *spinand) return spinand->manufacturer->ops->cleanup(spinand); } =20 +static bool spinand_op_is_odtr(const struct spi_mem_op *op) +{ + return op->cmd.dtr && op->cmd.buswidth =3D=3D 8; +} + static void spinand_init_ssdr_templates(struct spinand_device *spinand) { struct spinand_mem_ops *tmpl =3D &spinand->ssdr_op_templates; @@ -1424,6 +1435,10 @@ static int spinand_support_vendor_ops(struct spinand= _device *spinand, for (i =3D 0; i < info->vendor_ops->nops; i++) { const struct spi_mem_op *op =3D &info->vendor_ops->ops[i]; =20 + if ((iface =3D=3D SSDR && spinand_op_is_odtr(op)) || + (iface =3D=3D ODTR && !spinand_op_is_odtr(op))) + continue; + if (!spi_mem_supports_op(spinand->spimem, op)) return -EOPNOTSUPP; } @@ -1431,6 +1446,49 @@ static int spinand_support_vendor_ops(struct spinand= _device *spinand, return 0; } =20 +static int spinand_init_odtr_instruction_set(struct spinand_device *spinan= d) +{ + struct spinand_mem_ops *tmpl =3D &spinand->odtr_op_templates; + + tmpl->reset =3D (struct spi_mem_op)SPINAND_RESET_8D_0_0_OP; + if (!spi_mem_supports_op(spinand->spimem, &tmpl->reset)) + return -EOPNOTSUPP; + + tmpl->readid =3D (struct spi_mem_op)SPINAND_READID_8D_8D_8D_OP(0, 0, NULL= , 0); + if (!spi_mem_supports_op(spinand->spimem, &tmpl->readid)) + return -EOPNOTSUPP; + + tmpl->wr_en =3D (struct spi_mem_op)SPINAND_WR_EN_8D_0_0_OP; + if (!spi_mem_supports_op(spinand->spimem, &tmpl->wr_en)) + return -EOPNOTSUPP; + + tmpl->wr_dis =3D (struct spi_mem_op)SPINAND_WR_DIS_8D_0_0_OP; + if (!spi_mem_supports_op(spinand->spimem, &tmpl->wr_dis)) + return -EOPNOTSUPP; + + tmpl->set_feature =3D (struct spi_mem_op)SPINAND_SET_FEATURE_8D_8D_8D_OP(= 0, NULL); + if (!spi_mem_supports_op(spinand->spimem, &tmpl->set_feature)) + return -EOPNOTSUPP; + + tmpl->get_feature =3D (struct spi_mem_op)SPINAND_GET_FEATURE_8D_8D_8D_OP(= 0, NULL); + if (!spi_mem_supports_op(spinand->spimem, &tmpl->get_feature)) + return -EOPNOTSUPP; + + tmpl->blk_erase =3D (struct spi_mem_op)SPINAND_BLK_ERASE_8D_8D_0_OP(0); + if (!spi_mem_supports_op(spinand->spimem, &tmpl->blk_erase)) + return -EOPNOTSUPP; + + tmpl->page_read =3D (struct spi_mem_op)SPINAND_PAGE_READ_8D_8D_0_OP(0); + if (!spi_mem_supports_op(spinand->spimem, &tmpl->page_read)) + return -EOPNOTSUPP; + + tmpl->prog_exec =3D (struct spi_mem_op)SPINAND_PROG_EXEC_8D_8D_0_OP(0); + if (!spi_mem_supports_op(spinand->spimem, &tmpl->prog_exec)) + return -EOPNOTSUPP; + + return 0; +} + static const struct spi_mem_op * spinand_select_op_variant(struct spinand_device *spinand, enum spinand_bus= _interface iface, const struct spinand_op_variants *variants) @@ -1446,6 +1504,10 @@ spinand_select_op_variant(struct spinand_device *spi= nand, enum spinand_bus_inter unsigned int nbytes; int ret; =20 + if ((iface =3D=3D SSDR && spinand_op_is_odtr(&op)) || + (iface =3D=3D ODTR && !spinand_op_is_odtr(&op))) + continue; + nbytes =3D nanddev_per_page_oobsize(nand) + nanddev_page_size(nand); =20 @@ -1525,6 +1587,8 @@ int spinand_match_and_init(struct spinand_device *spi= nand, spinand->read_retries =3D table[i].read_retries; spinand->set_read_retry =3D table[i].set_read_retry; =20 + /* I/O variants selection with single-spi SDR commands */ + op =3D spinand_select_op_variant(spinand, SSDR, info->op_variants.read_cache); if (!op) @@ -1550,6 +1614,28 @@ int spinand_match_and_init(struct spinand_device *sp= inand, if (ret) return ret; =20 + /* I/O variants selection with octo-spi DDR commands (optional) */ + + ret =3D spinand_init_odtr_instruction_set(spinand); + if (ret) + return 0; + + ret =3D spinand_support_vendor_ops(spinand, info, ODTR); + if (ret) + return 0; + + op =3D spinand_select_op_variant(spinand, ODTR, + info->op_variants.read_cache); + spinand->odtr_op_templates.read_cache =3D op; + + op =3D spinand_select_op_variant(spinand, ODTR, + info->op_variants.write_cache); + spinand->odtr_op_templates.write_cache =3D op; + + op =3D spinand_select_op_variant(spinand, ODTR, + info->op_variants.update_cache); + spinand->odtr_op_templates.update_cache =3D op; + return 0; } =20 @@ -1591,9 +1677,34 @@ static int spinand_detect(struct spinand_device *spi= nand) =20 static int spinand_configure_chip(struct spinand_device *spinand) { - bool quad_enable =3D false; + bool odtr =3D false, quad_enable =3D false; int ret; =20 + if (spinand->odtr_op_templates.read_cache && + spinand->odtr_op_templates.write_cache && + spinand->odtr_op_templates.update_cache) + odtr =3D true; + + if (odtr) { + if (!spinand->configure_chip) + goto try_ssdr; + + /* ODTR bus interface configuration happens here */ + ret =3D spinand->configure_chip(spinand, ODTR); + if (ret) { + spinand->odtr_op_templates.read_cache =3D NULL; + spinand->odtr_op_templates.write_cache =3D NULL; + spinand->odtr_op_templates.update_cache =3D NULL; + goto try_ssdr; + } + + spinand->op_templates =3D &spinand->odtr_op_templates; + spinand->bus_iface =3D ODTR; + + return 0; + } + +try_ssdr: if (spinand->flags & SPINAND_HAS_QE_BIT) { if (spinand->ssdr_op_templates.read_cache->data.buswidth =3D=3D 4 || spinand->ssdr_op_templates.write_cache->data.buswidth =3D=3D 4 || @@ -1675,6 +1786,32 @@ static void spinand_mtd_resume(struct mtd_info *mtd) spinand_ecc_enable(spinand, false); } =20 +static int spinand_mtd_suspend(struct mtd_info *mtd) +{ + struct spinand_device *spinand =3D mtd_to_spinand(mtd); + int ret; + + /* + * Return to SSDR interface in the suspend path to make sure the + * reset operation is correctly processed upon resume. + * + * Note: Once back in SSDR mode, every operation but the page helpers + * (dirmap based I/O accessors) will work. Page accesses would require + * destroying and recreating the dirmaps twice to work, which would be + * impacting for no reason, as this is just a transitional state. + */ + if (spinand->bus_iface =3D=3D ODTR) { + ret =3D spinand->configure_chip(spinand, SSDR); + if (ret) + return ret; + + spinand->op_templates =3D &spinand->ssdr_op_templates; + spinand->bus_iface =3D SSDR; + } + + return 0; +} + static int spinand_init(struct spinand_device *spinand) { struct device *dev =3D &spinand->spimem->spi->dev; @@ -1744,6 +1881,7 @@ static int spinand_init(struct spinand_device *spinan= d) mtd->_block_isreserved =3D spinand_mtd_block_isreserved; mtd->_erase =3D spinand_mtd_erase; mtd->_max_bad_blocks =3D nanddev_mtd_max_bad_blocks; + mtd->_suspend =3D spinand_mtd_suspend; mtd->_resume =3D spinand_mtd_resume; =20 if (spinand_user_otp_size(spinand) || spinand_fact_otp_size(spinand)) { diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index b7eb3eceb138..fc5111fc778f 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -238,6 +238,77 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_OUT(len, buf, 8)) =20 +/** + * Octal DDR SPI NAND flash operations + */ + +#define SPINAND_RESET_8D_0_0_OP \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0xff, 8), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPINAND_READID_8D_8D_8D_OP(naddr, ndummy, buf, len) \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x9f, 8), \ + SPI_MEM_DTR_OP_ADDR(naddr, 0, 8), \ + SPI_MEM_DTR_OP_DUMMY(ndummy, 8), \ + SPI_MEM_DTR_OP_DATA_IN(len, buf, 8)) + +#define SPINAND_WR_EN_8D_0_0_OP \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x06, 8), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPINAND_WR_DIS_8D_0_0_OP \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x04, 8), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPINAND_SET_FEATURE_8D_8D_8D_OP(reg, valptr) \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x1f, 8), \ + SPI_MEM_DTR_OP_RPT_ADDR(reg, 8), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_DTR_OP_DATA_OUT(2, valptr, 8)) + +#define SPINAND_GET_FEATURE_8D_8D_8D_OP(reg, valptr) \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x0f, 8), \ + SPI_MEM_DTR_OP_RPT_ADDR(reg, 8), \ + SPI_MEM_DTR_OP_DUMMY(14, 8), \ + SPI_MEM_DTR_OP_DATA_IN(2, valptr, 8)) + +#define SPINAND_BLK_ERASE_8D_8D_0_OP(addr) \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0xd8, 8), \ + SPI_MEM_DTR_OP_ADDR(2, addr, 8), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPINAND_PAGE_READ_8D_8D_0_OP(addr) \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x13, 8), \ + SPI_MEM_DTR_OP_ADDR(2, addr, 8), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPINAND_PAGE_READ_FROM_CACHE_8D_8D_8D_OP(addr, ndummy, buf, len, f= req) \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x9d, 8), \ + SPI_MEM_DTR_OP_ADDR(2, addr, 8), \ + SPI_MEM_DTR_OP_DUMMY(ndummy, 8), \ + SPI_MEM_DTR_OP_DATA_IN(len, buf, 8), \ + SPI_MEM_OP_MAX_FREQ(freq)) + +#define SPINAND_PROG_EXEC_8D_8D_0_OP(addr) \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x10, 8), \ + SPI_MEM_DTR_OP_ADDR(2, addr, 8), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPINAND_PROG_LOAD_8D_8D_8D_OP(reset, addr, buf, len) \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD((reset ? 0xc2 : 0xc4), 8), \ + SPI_MEM_DTR_OP_ADDR(2, addr, 8), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_DTR_OP_DATA_OUT(len, buf, 8)) + /* feature register */ #define REG_BLOCK_LOCK 0xa0 #define BL_ALL_UNLOCKED 0x00 @@ -261,7 +332,7 @@ struct spinand_op; struct spinand_device; =20 -#define SPINAND_MAX_ID_LEN 5 +#define SPINAND_MAX_ID_LEN 6 /* * For erase, write and read operation, we got the following timings : * tBERS (erase) 1ms to 4ms @@ -287,7 +358,7 @@ struct spinand_device; =20 /** * struct spinand_id - SPI NAND id structure - * @data: buffer containing the id bytes. Currently 5 bytes large, but can + * @data: buffer containing the id bytes. Currently 6 bytes large, but can * be extended if required * @len: ID length */ @@ -484,9 +555,11 @@ struct spinand_user_otp { /** * enum spinand_bus_interface - SPI NAND bus interface types * @SSDR: Bus configuration supporting all 1S-XX-XX operations, including = dual and quad + * @ODTR: Bus configuration supporting only 8D-8D-8D operations */ enum spinand_bus_interface { SSDR, + ODTR, }; =20 /** @@ -651,6 +724,7 @@ struct spinand_mem_ops { * @id: NAND ID as returned by READ_ID * @flags: NAND flags * @ssdr_op_templates: Templates for all single SDR SPI mem operations + * @odtr_op_templates: Templates for all octal DTR SPI mem operations * @op_templates: Templates for all SPI mem operations * @bus_iface: Current bus interface * @select_target: select a specific target/die. Usually called before sen= ding @@ -687,6 +761,7 @@ struct spinand_device { u32 flags; =20 struct spinand_mem_ops ssdr_op_templates; + struct spinand_mem_ops odtr_op_templates; struct spinand_mem_ops *op_templates; enum spinand_bus_interface bus_iface; =20 --=20 2.51.1 From nobody Mon Feb 9 02:38:22 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 172FE36C5A4 for ; Fri, 9 Jan 2026 17:18:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979141; cv=none; b=jMWNug4m66pZ3gQa2015y95HNHJM4nk8d3YLMIwqn+jgBnz1NCcwWqskNnD2w/QojqPOoZTVS3ZcVcZAJJA+uWHDMtLFVAz9Tp5+tJEHV+/urYe1S6eBJ8seXby18bvmb+fl+FSo5cq2yZfjAzkAdGm57/cyCXk8PpS8ollvPy0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767979141; c=relaxed/simple; bh=n49egCOuT3hbLr1wY7eK3B3fGNpwZaWGiuFQnEjbip0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CkhwACHMPUSUbYwQJUrD8kYOUqH/aQyLMo09UfLSLyDpxG71WwRzj+N/s6YI5POTN6GahzVdhhWnQa4gJYIFz0h8RR1jJhjGcsdTvQfMDQ9kPhwzZOfMXc7ZTe6nxnAvYGne5Ig/iDvg4JbxaTYJniZ8FizOXyRbxHfUeTe5+qg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=rQD3nUtq; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="rQD3nUtq" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id B18AF4E4202C; Fri, 9 Jan 2026 17:18:54 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 86F2D606C6; Fri, 9 Jan 2026 17:18:54 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 0243E103C89AF; Fri, 9 Jan 2026 18:18:52 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767979133; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=kJNVCsG0Zk4FcaaKTxivXNZ2w3c05JJL982sKu8nc/Q=; b=rQD3nUtqDi5mqI219hNgWsJGehQ/YnDBPT4nqtf3sjsYvHpfnL4ckFLMRl7ESjMCt5o8c0 Sffi46oeBEiipnqbzluHSFatlIPyHnQdmxa2IzXasoZhSrhAxQlPKoip2amKIkyOsf9Le0 IJX4aBxDn4Pi45AwKwEo76b3WUOkBGYRBo9MEywZZla0kU8KWWBgArO1YhMHE+TqkAsP8t MXApixlMKDYrfNqhCFrmACPxZkaQcG3NJ4eWbcunpyVRKD1xag1mvauTiGiRR1hqVNFKT/ rptiMvvol+eYNOn8xiavkoSw7ScJOJS7H6HyeyPN8sVFOwlQ6AGWwbH9b61wVw== From: Miquel Raynal Date: Fri, 09 Jan 2026 18:18:25 +0100 Subject: [PATCH v2 27/27] mtd: spinand: winbond: W35N octal DTR support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-winbond-v6-17-rc1-oddr-v2-27-1fff6a2ddb80@bootlin.com> References: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> In-Reply-To: <20260109-winbond-v6-17-rc1-oddr-v2-0-1fff6a2ddb80@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Extend the support for the W35N chip family by supporting the ODTR bus interface. The chip is capable to run in this mode, which brings a significant performance improvement. 1S-8S-8S: # flash_speed /dev/mtd0 -c1 -d eraseblock write speed is 7529 KiB/s eraseblock read speed is 15058 KiB/s 8D-8D-8D: # flash_speed /dev/mtd0 -c1 -d eraseblock write speed is 9481 KiB/s eraseblock read speed is 23272 KiB/s This is +55% read speed and +26% write speed with the same hardware. Tests have been conducted with a TI AM62A7 using the Cadence quad SPI controller. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/winbond.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 90e4ece00cf5..8430ae307be0 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -36,6 +36,8 @@ */ =20 static SPINAND_OP_VARIANTS(read_cache_octal_variants, + SPINAND_PAGE_READ_FROM_CACHE_8D_8D_8D_OP(0, 24, NULL, 0, 120 * HZ_PER_MH= Z), + SPINAND_PAGE_READ_FROM_CACHE_8D_8D_8D_OP(0, 16, NULL, 0, 86 * HZ_PER_MHZ= ), SPINAND_PAGE_READ_FROM_CACHE_1S_1D_8D_OP(0, 3, NULL, 0, 120 * HZ_PER_MHZ= ), SPINAND_PAGE_READ_FROM_CACHE_1S_1D_8D_OP(0, 2, NULL, 0, 105 * HZ_PER_MHZ= ), SPINAND_PAGE_READ_FROM_CACHE_1S_8S_8S_OP(0, 20, NULL, 0, 0), @@ -48,11 +50,13 @@ static SPINAND_OP_VARIANTS(read_cache_octal_variants, SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(0, 1, NULL, 0, 0)); =20 static SPINAND_OP_VARIANTS(write_cache_octal_variants, + SPINAND_PROG_LOAD_8D_8D_8D_OP(true, 0, NULL, 0), SPINAND_PROG_LOAD_1S_8S_8S_OP(true, 0, NULL, 0), SPINAND_PROG_LOAD_1S_1S_8S_OP(0, NULL, 0), SPINAND_PROG_LOAD_1S_1S_1S_OP(true, 0, NULL, 0)); =20 static SPINAND_OP_VARIANTS(update_cache_octal_variants, + SPINAND_PROG_LOAD_8D_8D_8D_OP(false, 0, NULL, 0), SPINAND_PROG_LOAD_1S_8S_8S_OP(false, 0, NULL, 0), SPINAND_PROG_LOAD_1S_1S_1S_OP(false, 0, NULL, 0)); =20 @@ -93,13 +97,22 @@ static SPINAND_OP_VARIANTS(update_cache_variants, SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_OUT(1, buf, 1)) =20 +#define SPINAND_WINBOND_WRITE_VCR_8D_8D_8D(reg, buf) \ + SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x81, 8), \ + SPI_MEM_DTR_OP_ADDR(4, reg, 8), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_DTR_OP_DATA_OUT(2, buf, 8)) + static SPINAND_OP_VARIANTS(winbond_w35_ops, - SPINAND_WINBOND_WRITE_VCR_1S_1S_1S(0, NULL)); + SPINAND_WINBOND_WRITE_VCR_1S_1S_1S(0, NULL), + SPINAND_WINBOND_WRITE_VCR_8D_8D_8D(0, NULL)); =20 static struct spi_mem_op spinand_fill_winbond_write_vcr_op(struct spinand_device *spinand, u8 reg, = void *valptr) { - return (struct spi_mem_op)SPINAND_WINBOND_WRITE_VCR_1S_1S_1S(reg, valptr); + return (spinand->bus_iface =3D=3D SSDR) ? + (struct spi_mem_op)SPINAND_WINBOND_WRITE_VCR_1S_1S_1S(reg, valptr) : + (struct spi_mem_op)SPINAND_WINBOND_WRITE_VCR_8D_8D_8D(reg, valptr); } =20 #define SPINAND_WINBOND_SELECT_TARGET_1S_0_1S(buf) \ @@ -390,6 +403,9 @@ static int w35n0xjw_vcr_cfg(struct spinand_device *spin= and, case SSDR: ref_op =3D spinand->ssdr_op_templates.read_cache; break; + case ODTR: + ref_op =3D spinand->odtr_op_templates.read_cache; + break; default: return -EOPNOTSUPP; }; --=20 2.51.1