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Fri, 9 Jan 2026 10:22:50 +0100 From: Patrice Chotard Date: Fri, 9 Jan 2026 10:22:50 +0100 Subject: [PATCH v4 6/6] arm64: dts: st: Add boot phase tags for STMicroelectronics mp2 boards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260109-upstream_uboot_properties-v4-6-75e06657c600@foss.st.com> References: <20260109-upstream_uboot_properties-v4-0-75e06657c600@foss.st.com> In-Reply-To: <20260109-upstream_uboot_properties-v4-0-75e06657c600@foss.st.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Patrick Delaunay CC: , , , , Patrice Chotard X-Mailer: b4 0.14.3 X-ClientProxiedBy: ENXCAS1NODE2.st.com (10.75.128.138) To STKDAG1NODE1.st.com (10.75.128.132) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM4PEPF00025F96:EE_|DB4PR10MB6237:EE_ X-MS-Office365-Filtering-Correlation-Id: 088764c3-ea22-4bf6-6a4b-08de4f60a9da X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; 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X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: G1gNXv8QHsXAe/+qFcqzFZuu/g/vU4wnQAjWm9IIRAewrgIkJl63qUkI4dJoROJUUBjLPwQIgcHmNmBL7+mfeWI9wMiH9+jGa9HX3gm5+iJLJ68I6JhMiqxUIUI1wlzFbAELxI0tbRNqcjE3Y6lj78RBsYeUOKRBewN5LKnZMYJb6JGt48/dwxv1QhgSMzYyeiPLiPs2HTmIXWzhieEjOt+aaVWosP/JN5vrWpnQzrve9TKq0ahcAIIFTIcrlDfyStBMsyFNzZb0KY4xmNJ99CPuHeSsKyiD1JaFgdYbrPubikSuVl3FXttE3rCRCME5iZO6ZiDGQzxK8HMbMdYFRJen271tJCS5e2st3wKUGp92ilNVGEnQLGvNukZdnbcpAt/5X/xsy+XNAFvyDwy+UdI6n7UbD1id9IfCS2d39iBX2Q/7iDPYoyJxRwWx/JOtJy9GO/ZZKB60Y1wC8FHQWgALUJXzlWiVWzKEx90wHhDKPCFHZBRV178ik1kiiXaASPSRUvshw4EpaPddaHb2rn9YM/7sxbApnuXff9rowM8l/RlRFYuJ2w02bW+WBtsusHCoWQJO1tbk7PKuj9IjOfMoQJFxrRwWcC5UvOpQz4bVTNRHZHEFO/AMGE97eJGZaOHTfl7o7ufBKS//+6IQJf3K4ABWjq7FaC2ERixaEhWrFGlT8aqiMuYgPvb8Ch/T X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2026 09:22:51.7469 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 088764c3-ea22-4bf6-6a4b-08de4f60a9da X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.60];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00025F96.EURPRD83.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB4PR10MB6237 The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm64/boot/dts/st/stm32mp211.dtsi | 7 +++++++ arch/arm64/boot/dts/st/stm32mp215f-dk.dts | 1 + arch/arm64/boot/dts/st/stm32mp231.dtsi | 22 ++++++++++++++++++++++ arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 11 +++++++++++ arch/arm64/boot/dts/st/stm32mp251.dtsi | 25 +++++++++++++++++++++++++ arch/arm64/boot/dts/st/stm32mp255.dtsi | 3 ++- arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 11 +++++++++++ arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 11 +++++++++++ 8 files changed, 90 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/st/stm32mp211.dtsi b/arch/arm64/boot/dts/s= t/stm32mp211.dtsi index bf888d60cd4f..81b6a71fc032 100644 --- a/arch/arm64/boot/dts/st/stm32mp211.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp211.dtsi @@ -50,6 +50,7 @@ firmware { optee { compatible =3D "linaro,optee-tz"; method =3D "smc"; + bootph-all; }; =20 scmi: scmi { @@ -57,15 +58,18 @@ scmi: scmi { #address-cells =3D <1>; #size-cells =3D <0>; linaro,optee-channel-id =3D <0>; + bootph-all; =20 scmi_clk: protocol@14 { reg =3D <0x14>; #clock-cells =3D <1>; + bootph-all; }; =20 scmi_reset: protocol@16 { reg =3D <0x16>; #reset-cells =3D <1>; + bootph-all; }; }; }; @@ -73,6 +77,7 @@ scmi_reset: protocol@16 { psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; + bootph-all; }; =20 timer { @@ -92,6 +97,7 @@ soc@0 { interrupt-parent =3D <&intc>; #address-cells =3D <1>; #size-cells =3D <2>; + bootph-all; =20 rifsc: bus@42080000 { compatible =3D "simple-bus"; @@ -100,6 +106,7 @@ rifsc: bus@42080000 { dma-ranges; #address-cells =3D <1>; #size-cells =3D <2>; + bootph-all; =20 usart2: serial@400e0000 { compatible =3D "st,stm32h7-uart"; diff --git a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts b/arch/arm64/boot/dt= s/st/stm32mp215f-dk.dts index 7bdaeaa5ab0f..bc366639744a 100644 --- a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts @@ -45,5 +45,6 @@ &arm_wdt { }; =20 &usart2 { + bootph-all; status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/s= t/stm32mp231.dtsi index 88e214d395ab..075b4419d3ae 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -57,6 +57,7 @@ optee: optee { method =3D "smc"; interrupt-parent =3D <&intc>; interrupts =3D ; + bootph-all; }; =20 scmi { @@ -64,15 +65,18 @@ scmi { #address-cells =3D <1>; #size-cells =3D <0>; linaro,optee-channel-id =3D <0>; + bootph-all; =20 scmi_clk: protocol@14 { reg =3D <0x14>; #clock-cells =3D <1>; + bootph-all; }; =20 scmi_reset: protocol@16 { reg =3D <0x16>; #reset-cells =3D <1>; + bootph-all; }; =20 scmi_voltd: protocol@17 { @@ -114,6 +118,7 @@ scmi_vdda18adc: regulator@7 { psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; + bootph-all; =20 cpu0_pd: power-domain-cpu0 { #power-domain-cells =3D <0>; @@ -146,6 +151,7 @@ soc@0 { interrupt-parent =3D <&intc>; #address-cells =3D <1>; #size-cells =3D <1>; + bootph-all; =20 hpdma: dma-controller@40400000 { compatible =3D "st,stm32mp25-dma3"; @@ -223,6 +229,7 @@ rifsc: bus@42080000 { #address-cells =3D <1>; #size-cells =3D <1>; #access-controller-cells =3D <1>; + bootph-all; =20 i2s2: audio-controller@400b0000 { compatible =3D "st,stm32mp25-i2s"; @@ -760,6 +767,7 @@ bsec: efuse@44000000 { reg =3D <0x44000000 0x1000>; #address-cells =3D <1>; #size-cells =3D <1>; + bootph-all; =20 part_number_otp@24 { reg =3D <0x24 0x4>; @@ -857,6 +865,7 @@ rcc: clock-controller@44200000 { <&scmi_clk CK_SCMI_PLL3>, <&clk_dsi_txbyte>; access-controllers =3D <&rifsc 156>; + bootph-all; }; =20 exti1: interrupt-controller@44220000 { @@ -955,6 +964,7 @@ exti1: interrupt-controller@44220000 { syscfg: syscon@44230000 { compatible =3D "st,stm32mp23-syscfg", "syscon"; reg =3D <0x44230000 0x10000>; + bootph-all; }; =20 pinctrl: pinctrl@44240000 { @@ -965,6 +975,7 @@ pinctrl: pinctrl@44240000 { interrupt-parent =3D <&exti1>; st,syscfg =3D <&exti1 0x60 0xff>; pins-are-numbered; + bootph-all; =20 gpioa: gpio@44240000 { reg =3D <0x0 0x400>; @@ -974,6 +985,7 @@ gpioa: gpio@44240000 { #interrupt-cells =3D <2>; clocks =3D <&scmi_clk CK_SCMI_GPIOA>; st,bank-name =3D "GPIOA"; + bootph-all; status =3D "disabled"; }; =20 @@ -985,6 +997,7 @@ gpiob: gpio@44250000 { #interrupt-cells =3D <2>; clocks =3D <&scmi_clk CK_SCMI_GPIOB>; st,bank-name =3D "GPIOB"; + bootph-all; status =3D "disabled"; }; =20 @@ -996,6 +1009,7 @@ gpioc: gpio@44260000 { #interrupt-cells =3D <2>; clocks =3D <&scmi_clk CK_SCMI_GPIOC>; st,bank-name =3D "GPIOC"; + bootph-all; status =3D "disabled"; }; =20 @@ -1007,6 +1021,7 @@ gpiod: gpio@44270000 { #interrupt-cells =3D <2>; clocks =3D <&scmi_clk CK_SCMI_GPIOD>; st,bank-name =3D "GPIOD"; + bootph-all; status =3D "disabled"; }; =20 @@ -1018,6 +1033,7 @@ gpioe: gpio@44280000 { #interrupt-cells =3D <2>; clocks =3D <&scmi_clk CK_SCMI_GPIOE>; st,bank-name =3D "GPIOE"; + bootph-all; status =3D "disabled"; }; =20 @@ -1029,6 +1045,7 @@ gpiof: gpio@44290000 { #interrupt-cells =3D <2>; clocks =3D <&scmi_clk CK_SCMI_GPIOF>; st,bank-name =3D "GPIOF"; + bootph-all; status =3D "disabled"; }; =20 @@ -1040,6 +1057,7 @@ gpiog: gpio@442a0000 { #interrupt-cells =3D <2>; clocks =3D <&scmi_clk CK_SCMI_GPIOG>; st,bank-name =3D "GPIOG"; + bootph-all; status =3D "disabled"; }; =20 @@ -1051,6 +1069,7 @@ gpioh: gpio@442b0000 { #interrupt-cells =3D <2>; clocks =3D <&scmi_clk CK_SCMI_GPIOH>; st,bank-name =3D "GPIOH"; + bootph-all; status =3D "disabled"; }; =20 @@ -1062,6 +1081,7 @@ gpioi: gpio@442c0000 { #interrupt-cells =3D <2>; clocks =3D <&scmi_clk CK_SCMI_GPIOI>; st,bank-name =3D "GPIOI"; + bootph-all; status =3D "disabled"; }; }; @@ -1084,6 +1104,7 @@ pinctrl_z: pinctrl@46200000 { interrupt-parent =3D <&exti1>; st,syscfg =3D <&exti1 0x60 0xff>; pins-are-numbered; + bootph-all; =20 gpioz: gpio@46200000 { reg =3D <0 0x400>; @@ -1094,6 +1115,7 @@ gpioz: gpio@46200000 { clocks =3D <&scmi_clk CK_SCMI_GPIOZ>; st,bank-name =3D "GPIOZ"; st,bank-ioport =3D <11>; + bootph-all; status =3D "disabled"; }; =20 diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dt= s/st/stm32mp235f-dk.dts index c3e688068223..391494eda5e6 100644 --- a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts @@ -130,7 +130,18 @@ &usart2 { pinctrl-0 =3D <&usart2_pins_a>; pinctrl-1 =3D <&usart2_idle_pins_a>; pinctrl-2 =3D <&usart2_sleep_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; + +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index a8e6e0f77b83..0cc3ac8bb584 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -66,6 +66,7 @@ optee: optee { method =3D "smc"; interrupt-parent =3D <&intc>; interrupts =3D ; + bootph-all; }; =20 scmi { @@ -73,15 +74,18 @@ scmi { #address-cells =3D <1>; #size-cells =3D <0>; linaro,optee-channel-id =3D <0>; + bootph-all; =20 scmi_clk: protocol@14 { reg =3D <0x14>; #clock-cells =3D <1>; + bootph-all; }; =20 scmi_reset: protocol@16 { reg =3D <0x16>; #reset-cells =3D <1>; + bootph-all; }; =20 scmi_voltd: protocol@17 { @@ -142,6 +146,7 @@ v2m0: v2m@48090000 { psci { compatible =3D "arm,psci-1.0"; method =3D "smc"; + bootph-all; =20 CPU_PD0: power-domain-cpu0 { #power-domain-cells =3D <0>; @@ -174,6 +179,7 @@ soc@0 { #size-cells =3D <1>; interrupt-parent =3D <&intc>; ranges =3D <0x0 0x0 0x0 0x80000000>; + bootph-all; =20 hpdma: dma-controller@40400000 { compatible =3D "st,stm32mp25-dma3"; @@ -305,6 +311,7 @@ rifsc: bus@42080000 { #size-cells =3D <1>; #access-controller-cells =3D <1>; ranges; + bootph-all; =20 timers2: timer@40000000 { compatible =3D "st,stm32mp25-timers"; @@ -1577,6 +1584,7 @@ ltdc: display-controller@48010000 { clock-names =3D "lcd", "bus"; resets =3D <&rcc LTDC_R>; access-controllers =3D <&rifsc 80>; + bootph-all; status =3D "disabled"; }; =20 @@ -1738,6 +1746,7 @@ bsec: efuse@44000000 { reg =3D <0x44000000 0x1000>; #address-cells =3D <1>; #size-cells =3D <1>; + bootph-all; =20 part_number_otp@24 { reg =3D <0x24 0x4>; @@ -1842,6 +1851,7 @@ rcc: clock-controller@44200000 { <&scmi_clk CK_SCMI_PLL3>, <&clk_dsi_txbyte>; access-controllers =3D <&rifsc 156>; + bootph-all; }; =20 exti1: interrupt-controller@44220000 { @@ -1941,6 +1951,7 @@ syscfg: syscon@44230000 { compatible =3D "st,stm32mp25-syscfg", "syscon"; reg =3D <0x44230000 0x10000>; #clock-cells =3D <0>; + bootph-all; }; =20 pinctrl: pinctrl@44240000 { @@ -1951,6 +1962,7 @@ pinctrl: pinctrl@44240000 { interrupt-parent =3D <&exti1>; st,syscfg =3D <&exti1 0x60 0xff>; pins-are-numbered; + bootph-all; =20 gpioa: gpio@44240000 { gpio-controller; @@ -1960,6 +1972,7 @@ gpioa: gpio@44240000 { reg =3D <0x0 0x400>; clocks =3D <&scmi_clk CK_SCMI_GPIOA>; st,bank-name =3D "GPIOA"; + bootph-all; status =3D "disabled"; }; =20 @@ -1971,6 +1984,7 @@ gpiob: gpio@44250000 { reg =3D <0x10000 0x400>; clocks =3D <&scmi_clk CK_SCMI_GPIOB>; st,bank-name =3D "GPIOB"; + bootph-all; status =3D "disabled"; }; =20 @@ -1982,6 +1996,7 @@ gpioc: gpio@44260000 { reg =3D <0x20000 0x400>; clocks =3D <&scmi_clk CK_SCMI_GPIOC>; st,bank-name =3D "GPIOC"; + bootph-all; status =3D "disabled"; }; =20 @@ -1993,6 +2008,7 @@ gpiod: gpio@44270000 { reg =3D <0x30000 0x400>; clocks =3D <&scmi_clk CK_SCMI_GPIOD>; st,bank-name =3D "GPIOD"; + bootph-all; status =3D "disabled"; }; =20 @@ -2004,6 +2020,7 @@ gpioe: gpio@44280000 { reg =3D <0x40000 0x400>; clocks =3D <&scmi_clk CK_SCMI_GPIOE>; st,bank-name =3D "GPIOE"; + bootph-all; status =3D "disabled"; }; =20 @@ -2015,6 +2032,7 @@ gpiof: gpio@44290000 { reg =3D <0x50000 0x400>; clocks =3D <&scmi_clk CK_SCMI_GPIOF>; st,bank-name =3D "GPIOF"; + bootph-all; status =3D "disabled"; }; =20 @@ -2026,6 +2044,7 @@ gpiog: gpio@442a0000 { reg =3D <0x60000 0x400>; clocks =3D <&scmi_clk CK_SCMI_GPIOG>; st,bank-name =3D "GPIOG"; + bootph-all; status =3D "disabled"; }; =20 @@ -2037,6 +2056,7 @@ gpioh: gpio@442b0000 { reg =3D <0x70000 0x400>; clocks =3D <&scmi_clk CK_SCMI_GPIOH>; st,bank-name =3D "GPIOH"; + bootph-all; status =3D "disabled"; }; =20 @@ -2048,6 +2068,7 @@ gpioi: gpio@442c0000 { reg =3D <0x80000 0x400>; clocks =3D <&scmi_clk CK_SCMI_GPIOI>; st,bank-name =3D "GPIOI"; + bootph-all; status =3D "disabled"; }; =20 @@ -2059,6 +2080,7 @@ gpioj: gpio@442d0000 { reg =3D <0x90000 0x400>; clocks =3D <&scmi_clk CK_SCMI_GPIOJ>; st,bank-name =3D "GPIOJ"; + bootph-all; status =3D "disabled"; }; =20 @@ -2070,6 +2092,7 @@ gpiok: gpio@442e0000 { reg =3D <0xa0000 0x400>; clocks =3D <&scmi_clk CK_SCMI_GPIOK>; st,bank-name =3D "GPIOK"; + bootph-all; status =3D "disabled"; }; }; @@ -2092,6 +2115,7 @@ pinctrl_z: pinctrl@46200000 { interrupt-parent =3D <&exti1>; st,syscfg =3D <&exti1 0x60 0xff>; pins-are-numbered; + bootph-all; =20 gpioz: gpio@46200000 { gpio-controller; @@ -2102,6 +2126,7 @@ gpioz: gpio@46200000 { clocks =3D <&scmi_clk CK_SCMI_GPIOZ>; st,bank-name =3D "GPIOZ"; st,bank-ioport =3D <11>; + bootph-all; status =3D "disabled"; }; }; diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/s= t/stm32mp255.dtsi index 7a598f53a2a0..7b2e07613030 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -21,6 +21,7 @@ lvds: lvds@48060000 { resets =3D <&rcc LVDS_R>; access-controllers =3D <&rifsc 84>; power-domains =3D <&CLUSTER_PD>; + bootph-all; status =3D "disabled"; }; =20 @@ -40,4 +41,4 @@ venc: venc@480e0000 { clocks =3D <&rcc CK_BUS_VENC>; access-controllers =3D <&rifsc 90>; }; -}; \ No newline at end of file +}; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dt= s/st/stm32mp257f-dk.dts index e718d888ce21..69bac9e719d7 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -130,7 +130,18 @@ &usart2 { pinctrl-0 =3D <&usart2_pins_a>; pinctrl-1 =3D <&usart2_idle_pins_a>; pinctrl-2 =3D <&usart2_sleep_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; + +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/d= ts/st/stm32mp257f-ev1.dts index 6e165073f732..307b9692b00a 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -477,11 +477,22 @@ &usart2 { pinctrl-0 =3D <&usart2_pins_a>; pinctrl-1 =3D <&usart2_idle_pins_a>; pinctrl-2 =3D <&usart2_sleep_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status =3D "okay"; }; =20 +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usart6 { pinctrl-names =3D "default", "idle", "sleep"; pinctrl-0 =3D <&usart6_pins_a>; --=20 2.43.0