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Fri, 9 Jan 2026 10:22:47 +0100 From: Patrice Chotard Date: Fri, 9 Jan 2026 10:22:45 +0100 Subject: [PATCH v4 1/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f4 boards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260109-upstream_uboot_properties-v4-1-75e06657c600@foss.st.com> References: <20260109-upstream_uboot_properties-v4-0-75e06657c600@foss.st.com> In-Reply-To: <20260109-upstream_uboot_properties-v4-0-75e06657c600@foss.st.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Patrick Delaunay CC: , , , , Patrice Chotard X-Mailer: b4 0.14.3 X-ClientProxiedBy: ENXCAS1NODE2.st.com (10.75.128.138) To STKDAG1NODE1.st.com (10.75.128.132) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM4PEPF00025F95:EE_|PAXPR10MB5711:EE_ X-MS-Office365-Filtering-Correlation-Id: 859e6ef0-6daa-4f6b-37ba-08de4f60a76f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; 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X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: RjwaV6lK/iFhVQM3Z86rUAeOJFBufmwpVR2lSdzCaQEivE6wS5JscXp2C2yjqBxWspwWXnINPu+gIrAGRaJ6OhBy9NATYb98H+HGdW0spbIUmEron5IYHCu8iOmJDFHeVjKw76EnK4xDcMOVlaT2ktuub5K1gKDSC7mX9BZyyr/RvG10ypoogIiZSJsVscn2glyo8Ftkegcn3emGhK+yRoqPUt5QHrgfZ0RQEF2geFwxFYEyDCpT9y24Df7+XjBbMBFY2hjhtlAUaybNXLEWYLbuamwXyEFaXg+Ci7AsieP3oWKFYGBdAbMGQ+hN5p3xpb3XzkhXWFJ7FjcnGVsg9Xa9FIpgDhu84vdVD2rOTsqDSkg0Q1kApJwgmCsqo+1JRpM3r0j6qz8AbaijROEyKbPkkpxpsO4h8SJELO1umew0gtar0S2igR/HoQykLm3W7MO6hvA+FcqAWGNxWomrMxrkknJFigHuM+FbADrpkQ9GI0p/Tj3rG+m0+U8ExG4rQpG/hmZtEeq8pCKFAY+vvAJvcXVQ2Kg03unQGFsknkAB0+yKLT5Fy9JCIJPznaBhAYR77vEZ9jZK2Tx5MBy5ViO6Chh2dpV1aJEw5SdtdtqGk228/uV8wwQhnSkmtJneCgZce22dwouyi8mCrbjPXDQD3kXuSmyCkpgZtJeNaJWB07nlTC1cD+rDV1MSqwG5 X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2026 09:22:47.6927 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 859e6ef0-6daa-4f6b-37ba-08de4f60a76f X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.60];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00025F95.EURPRD83.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR10MB5711 The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stm32429i-eval.dts | 11 +++++++++++ arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi | 12 ++++++++++++ arch/arm/boot/dts/st/stm32f429-disco.dts | 11 +++++++++++ arch/arm/boot/dts/st/stm32f429.dtsi | 9 +++++++++ arch/arm/boot/dts/st/stm32f469-disco.dts | 12 ++++++++++++ 5 files changed, 55 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32429i-eval.dts b/arch/arm/boot/dts/st= /stm32429i-eval.dts index afa417b34b25..3b6151fcb070 100644 --- a/arch/arm/boot/dts/st/stm32429i-eval.dts +++ b/arch/arm/boot/dts/st/stm32429i-eval.dts @@ -312,6 +312,7 @@ &timers5 { /* Override timer5 to act as clockevent */ compatible =3D "st,stm32-timer"; interrupts =3D <50>; + bootph-all; status =3D "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -326,6 +327,16 @@ &usart1 { status =3D "okay"; }; =20 +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { dr_mode =3D "host"; phys =3D <&usbotg_hs_phy>; diff --git a/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/= st/stm32f4-pinctrl.dtsi index 3bb812d6399e..bcaed4618738 100644 --- a/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi @@ -51,6 +51,7 @@ pinctrl: pinctrl@40020000 { ranges =3D <0 0x40020000 0x3000>; interrupt-parent =3D <&exti>; st,syscfg =3D <&syscfg 0x8>; + bootph-all; =20 gpioa: gpio@40020000 { gpio-controller; @@ -60,6 +61,7 @@ gpioa: gpio@40020000 { reg =3D <0x0 0x400>; clocks =3D <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>; st,bank-name =3D "GPIOA"; + bootph-all; }; =20 gpiob: gpio@40020400 { @@ -70,6 +72,7 @@ gpiob: gpio@40020400 { reg =3D <0x400 0x400>; clocks =3D <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>; st,bank-name =3D "GPIOB"; + bootph-all; }; =20 gpioc: gpio@40020800 { @@ -80,6 +83,7 @@ gpioc: gpio@40020800 { reg =3D <0x800 0x400>; clocks =3D <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>; st,bank-name =3D "GPIOC"; + bootph-all; }; =20 gpiod: gpio@40020c00 { @@ -90,6 +94,7 @@ gpiod: gpio@40020c00 { reg =3D <0xc00 0x400>; clocks =3D <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>; st,bank-name =3D "GPIOD"; + bootph-all; }; =20 gpioe: gpio@40021000 { @@ -100,6 +105,7 @@ gpioe: gpio@40021000 { reg =3D <0x1000 0x400>; clocks =3D <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>; st,bank-name =3D "GPIOE"; + bootph-all; }; =20 gpiof: gpio@40021400 { @@ -110,6 +116,7 @@ gpiof: gpio@40021400 { reg =3D <0x1400 0x400>; clocks =3D <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>; st,bank-name =3D "GPIOF"; + bootph-all; }; =20 gpiog: gpio@40021800 { @@ -120,6 +127,7 @@ gpiog: gpio@40021800 { reg =3D <0x1800 0x400>; clocks =3D <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>; st,bank-name =3D "GPIOG"; + bootph-all; }; =20 gpioh: gpio@40021c00 { @@ -130,6 +138,7 @@ gpioh: gpio@40021c00 { reg =3D <0x1c00 0x400>; clocks =3D <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>; st,bank-name =3D "GPIOH"; + bootph-all; }; =20 gpioi: gpio@40022000 { @@ -140,6 +149,7 @@ gpioi: gpio@40022000 { reg =3D <0x2000 0x400>; clocks =3D <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>; st,bank-name =3D "GPIOI"; + bootph-all; }; =20 gpioj: gpio@40022400 { @@ -150,6 +160,7 @@ gpioj: gpio@40022400 { reg =3D <0x2400 0x400>; clocks =3D <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>; st,bank-name =3D "GPIOJ"; + bootph-all; }; =20 gpiok: gpio@40022800 { @@ -160,6 +171,7 @@ gpiok: gpio@40022800 { reg =3D <0x2800 0x400>; clocks =3D <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>; st,bank-name =3D "GPIOK"; + bootph-all; }; =20 usart1_pins_a: usart1-0 { diff --git a/arch/arm/boot/dts/st/stm32f429-disco.dts b/arch/arm/boot/dts/s= t/stm32f429-disco.dts index a3cb4aabdd5a..39a80a9caa5f 100644 --- a/arch/arm/boot/dts/st/stm32f429-disco.dts +++ b/arch/arm/boot/dts/st/stm32f429-disco.dts @@ -209,6 +209,7 @@ &timers5 { /* Override timer5 to act as clockevent */ compatible =3D "st,stm32-timer"; interrupts =3D <50>; + bootph-all; status =3D "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -223,6 +224,16 @@ &usart1 { status =3D "okay"; }; =20 +&usart1_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_hs { compatible =3D "st,stm32f4x9-fsotg"; dr_mode =3D "host"; diff --git a/arch/arm/boot/dts/st/stm32f429.dtsi b/arch/arm/boot/dts/st/stm= 32f429.dtsi index ad91b74ddd0d..51c931f7b9d5 100644 --- a/arch/arm/boot/dts/st/stm32f429.dtsi +++ b/arch/arm/boot/dts/st/stm32f429.dtsi @@ -54,16 +54,20 @@ / { #size-cells =3D <1>; =20 clocks { + bootph-all; + clk_hse: clk-hse { #clock-cells =3D <0>; compatible =3D "fixed-clock"; clock-frequency =3D <0>; + bootph-all; }; =20 clk_lse: clk-lse { #clock-cells =3D <0>; compatible =3D "fixed-clock"; clock-frequency =3D <32768>; + bootph-all; }; =20 clk_lsi: clk-lsi { @@ -76,10 +80,12 @@ clk_i2s_ckin: i2s-ckin { #clock-cells =3D <0>; compatible =3D "fixed-clock"; clock-frequency =3D <0>; + bootph-all; }; }; =20 soc { + bootph-all; romem: efuse@1fff7800 { compatible =3D "st,stm32f4-otp"; reg =3D <0x1fff7800 0x400>; @@ -580,6 +586,7 @@ syscfg: syscon@40013800 { compatible =3D "st,stm32-syscfg", "syscon"; reg =3D <0x40013800 0x400>; clocks =3D <&rcc 0 STM32F4_APB2_CLOCK(SYSCFG)>; + bootph-all; }; =20 exti: interrupt-controller@40013c00 { @@ -666,6 +673,7 @@ spi6: spi@40015400 { pwrcfg: power-config@40007000 { compatible =3D "st,stm32-power-config", "syscon"; reg =3D <0x40007000 0x400>; + bootph-all; }; =20 ltdc: display-controller@40016800 { @@ -694,6 +702,7 @@ rcc: rcc@40023800 { st,syscfg =3D <&pwrcfg>; assigned-clocks =3D <&rcc 1 CLK_HSE_RTC>; assigned-clock-rates =3D <1000000>; + bootph-all; }; =20 dma1: dma-controller@40026000 { diff --git a/arch/arm/boot/dts/st/stm32f469-disco.dts b/arch/arm/boot/dts/s= t/stm32f469-disco.dts index 8a4f8ddd083d..de025a385e9e 100644 --- a/arch/arm/boot/dts/st/stm32f469-disco.dts +++ b/arch/arm/boot/dts/st/stm32f469-disco.dts @@ -169,6 +169,7 @@ dsi_panel_in: endpoint { }; =20 <dc { + bootph-all; status =3D "okay"; =20 port { @@ -225,6 +226,7 @@ &timers5 { /* Override timer5 to act as clockevent */ compatible =3D "st,stm32-timer"; interrupts =3D <50>; + bootph-all; status =3D "okay"; /delete-property/#address-cells; /delete-property/#size-cells; @@ -239,6 +241,16 @@ &usart3 { status =3D "okay"; }; =20 +&usart3_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usbotg_fs { dr_mode =3D "host"; pinctrl-0 =3D <&usbotg_fs_pins_a>; --=20 2.43.0