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[2a01:cb04:5e8:3a00:cb3:8cfe:2980:7c1e]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b842a230db0sm1195426266b.2.2026.01.09.09.30.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jan 2026 09:30:20 -0800 (PST) From: Mary Guillemard Date: Fri, 09 Jan 2026 18:30:11 +0100 Subject: [PATCH 2/3] drm/nouveau: Unify GPFIFO ring buffer max count query Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-nouveau-gpfifo-increase-v1-2-ed0be9822878@mary.zone> References: <20260109-nouveau-gpfifo-increase-v1-0-ed0be9822878@mary.zone> In-Reply-To: <20260109-nouveau-gpfifo-increase-v1-0-ed0be9822878@mary.zone> To: Lyude Paul , Danilo Krummrich , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, nouveau@lists.freedesktop.org, linux-kernel@vger.kernel.org, Mary Guillemard X-Mailer: b4 0.14.3 Previously, the max count for the GPFIFO ring buffer was hardcoded in two different places. This patch adds a new function nouveau_channel_get_gpfifo_entries_count to share the logic between the two side of the codebase allowing us to later on increase the limit. Signed-off-by: Mary Guillemard --- drivers/gpu/drm/nouveau/nouveau_abi16.c | 15 +++++++++++++-- drivers/gpu/drm/nouveau/nouveau_chan.c | 3 ++- drivers/gpu/drm/nouveau/nouveau_chan.h | 12 ++++++++++++ drivers/gpu/drm/nouveau/nouveau_dma.h | 3 --- 4 files changed, 27 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouv= eau/nouveau_abi16.c index a3ba07fc48a0..a5445e97179f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c @@ -232,15 +232,26 @@ nouveau_abi16_fini(struct nouveau_abi16 *abi16) static inline int getparam_dma_ib_max(struct nvif_device *device) { - const struct nvif_mclass dmas[] =3D { + const struct nvif_mclass hosts[] =3D { { NV03_CHANNEL_DMA, 0 }, { NV10_CHANNEL_DMA, 0 }, { NV17_CHANNEL_DMA, 0 }, { NV40_CHANNEL_DMA, 0 }, {} }; + int cid; + u32 res; =20 - return nvif_mclass(&device->object, dmas) < 0 ? NV50_DMA_IB_MAX : 0; + cid =3D nvif_mclass(&device->object, hosts); + if (cid < 0) + res =3D NV50_CHANNEL_GPFIFO_ENTRIES_MAX_COUNT; + else + res =3D nouveau_channel_get_gpfifo_entries_count(hosts[cid].oclass); + + if (res =3D=3D 0) + return 0; + + return res - 1; } =20 int diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouve= au/nouveau_chan.c index b646212a34b3..8695b5d6aefc 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -274,7 +274,7 @@ nouveau_channel_ctor(struct nouveau_cli *cli, bool priv= , u64 runm, struct nouveau_channel *chan; const u64 plength =3D 0x10000; const u64 ioffset =3D plength; - const u64 ilength =3D 0x02000; + u64 ilength; int cid, ret; u64 size; =20 @@ -282,6 +282,7 @@ nouveau_channel_ctor(struct nouveau_cli *cli, bool priv= , u64 runm, if (cid < 0) return cid; =20 + ilength =3D nouveau_channel_get_gpfifo_entries_count(hosts[cid].oclass) *= 8; if (hosts[cid].oclass < NV50_CHANNEL_GPFIFO) size =3D plength; else diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.h b/drivers/gpu/drm/nouve= au/nouveau_chan.h index 9839de8da985..294d061497c0 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.h +++ b/drivers/gpu/drm/nouveau/nouveau_chan.h @@ -4,6 +4,7 @@ #include #include #include +#include struct nvif_device; =20 struct nouveau_channel { @@ -65,6 +66,17 @@ void nouveau_channel_del(struct nouveau_channel **); int nouveau_channel_idle(struct nouveau_channel *); void nouveau_channel_kill(struct nouveau_channel *); =20 +/* Maximum GPFIFO entries per channel. */ +#define NV50_CHANNEL_GPFIFO_ENTRIES_MAX_COUNT (0x02000 / 8) + +static inline u32 nouveau_channel_get_gpfifo_entries_count(u32 oclass) +{ + if (oclass < NV50_CHANNEL_GPFIFO) + return 0; + + return NV50_CHANNEL_GPFIFO_ENTRIES_MAX_COUNT; +} + extern int nouveau_vram_pushbuf; =20 #endif diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouvea= u/nouveau_dma.h index c25ef9a54b9f..7f8445014e4d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -47,9 +47,6 @@ int nouveau_dma_wait(struct nouveau_channel *, int size); /* Maximum push buffer size. */ #define NV50_DMA_PUSH_MAX_LENGTH 0x7fffff =20 -/* Maximum IBs per ring. */ -#define NV50_DMA_IB_MAX ((0x02000 / 8) - 1) - /* Object handles - for stuff that's doesn't use handle =3D=3D oclass. */ enum { NvDmaFB =3D 0x80000002, --=20 2.52.0