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[34.141.175.244]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6507be651a4sm10642182a12.16.2026.01.09.09.27.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jan 2026 09:27:27 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Fri, 09 Jan 2026 17:27:23 +0000 Subject: [PATCH 1/3] clk: samsung: avoid warning message on legacy Exynos (auto clock gating) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-clk-samsung-autoclk-updates-v1-1-2394dcf242a9@linaro.org> References: <20260109-clk-samsung-autoclk-updates-v1-0-2394dcf242a9@linaro.org> In-Reply-To: <20260109-clk-samsung-autoclk-updates-v1-0-2394dcf242a9@linaro.org> To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd Cc: Peter Griffin , Tudor Ambarus , Will McVicker , Juan Yescas , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Andr=C3=A9_Draszik?= , Marek Szyprowski X-Mailer: b4 0.14.2 We currently print a warning message that the IO memory size is not compatible with automatic clock gating for many Exynos-based boards, including legacy ones, even if not requested to enable automatic clock gating in the first place. Change the test in question to avoid that warning. Fixes: 298fac4f4b96 ("clk: samsung: Implement automatic clock gating mode f= or CMUs") Reported-by: Marek Szyprowski Closes: https://lore.kernel.org/all/8b2c412d-3e1e-4be0-a9d5-ef67f6f0d409@sa= msung.com/ Suggested-by: Marek Szyprowski Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Peter Griffin --- drivers/clk/samsung/clk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c index 06ea5deef4ee2ffb87dcd14102561886ea80b7bc..417ec1786b5e77e17dda4022b41= 7c1c6b79c59ab 100644 --- a/drivers/clk/samsung/clk.c +++ b/drivers/clk/samsung/clk.c @@ -462,7 +462,7 @@ void __init samsung_cmu_register_clocks(struct samsung_= clk_provider *ctx, const struct samsung_cmu_info *cmu, struct device_node *np) { - if (samsung_is_auto_capable(np) && cmu->auto_clock_gate) + if (cmu->auto_clock_gate && samsung_is_auto_capable(np)) ctx->auto_clock_gate =3D cmu->auto_clock_gate; =20 ctx->gate_dbg_offset =3D cmu->gate_dbg_offset; --=20 2.52.0.457.g6b5491de43-goog From nobody Mon Feb 9 21:22:27 2026 Received: from mail-ed1-f51.google.com (mail-ed1-f51.google.com [209.85.208.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BFD3366552 for ; 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[34.141.175.244]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6507be651a4sm10642182a12.16.2026.01.09.09.27.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jan 2026 09:27:27 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Fri, 09 Jan 2026 17:27:24 +0000 Subject: [PATCH 2/3] clk: samsung: fix sysreg save/restore when PM is enabled for CMU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-clk-samsung-autoclk-updates-v1-2-2394dcf242a9@linaro.org> References: <20260109-clk-samsung-autoclk-updates-v1-0-2394dcf242a9@linaro.org> In-Reply-To: <20260109-clk-samsung-autoclk-updates-v1-0-2394dcf242a9@linaro.org> To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd Cc: Peter Griffin , Tudor Ambarus , Will McVicker , Juan Yescas , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 Currently, sysreg registers of a CMU that has PM and automatic clock gating enabled are not saved / restored during runtime PM (RPM) or s2idle. During normal suspend, they are accessed too late, after the CMU (and potentially power domain) have been shut down, causing an SError. The reason is that these registers are registered to be saved/restored via a syscore suspend handler which doesn't run during RPM or s2idle. During normal suspend, this handler runs after the CMU has been shut down. This registration happens as part of samsung_clk_extended_sleep_init() via samsung_en_dyn_root_clk_gating(). When PM is enabled for a CMU, registers must be saved/restored via exynos_arm64_cmu_suspend() / exynos_arm64_cmu_resume() respectively instead. These use their own data structures and are unrelated to anything that samsung_clk_extended_sleep_init() does. Calling it unconditionally from samsung_en_dyn_root_clk_gating() therefore isn't useful. Update the code to prepare sysreg save / restore in a similar way to how it handles other clock registers in the PM case already. exynos_arm64_cmu_suspend() / exynos_arm64_cmu_resume() already handle sysreg save/restore, just the setup was incorrect. Fixes: 298fac4f4b96 ("clk: samsung: Implement automatic clock gating mode f= or CMUs") Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Peter Griffin --- drivers/clk/samsung/clk-exynos-arm64.c | 32 ++++++++++++++++++++++++++----= -- drivers/clk/samsung/clk.c | 19 +++++++++++++------ drivers/clk/samsung/clk.h | 3 ++- 3 files changed, 41 insertions(+), 13 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos-arm64.c b/drivers/clk/samsung/c= lk-exynos-arm64.c index 11e4d49f2390ba714eff5a329bb1f427cd6437b9..35d4de233cc1b4aa25490ff20d0= f0372b8d3d0d6 100644 --- a/drivers/clk/samsung/clk-exynos-arm64.c +++ b/drivers/clk/samsung/clk-exynos-arm64.c @@ -174,7 +174,7 @@ static int __init exynos_arm64_cmu_prepare_pm(struct de= vice *dev, const struct samsung_cmu_info *cmu) { struct exynos_arm64_cmu_data *data =3D dev_get_drvdata(dev); - int i; + int i, ret; =20 data->clk_save =3D samsung_clk_alloc_reg_dump(cmu->clk_regs, cmu->nr_clk_regs); @@ -182,8 +182,22 @@ static int __init exynos_arm64_cmu_prepare_pm(struct d= evice *dev, return -ENOMEM; =20 data->nr_clk_save =3D cmu->nr_clk_regs; + + if (cmu->nr_sysreg_clk_regs) { + data->clk_sysreg_save =3D + samsung_clk_alloc_reg_dump(cmu->sysreg_clk_regs, + cmu->nr_sysreg_clk_regs); + if (!data->clk_sysreg_save) { + ret =3D -ENOMEM; + goto free_clk_save; + } + + data->nr_clk_sysreg =3D cmu->nr_sysreg_clk_regs; + } + data->clk_suspend =3D cmu->suspend_regs; data->nr_clk_suspend =3D cmu->nr_suspend_regs; + data->nr_pclks =3D of_clk_get_parent_count(dev->of_node); if (!data->nr_pclks) return 0; @@ -191,23 +205,29 @@ static int __init exynos_arm64_cmu_prepare_pm(struct = device *dev, data->pclks =3D devm_kcalloc(dev, sizeof(struct clk *), data->nr_pclks, GFP_KERNEL); if (!data->pclks) { - kfree(data->clk_save); - return -ENOMEM; + ret =3D -ENOMEM; + goto free_sysreg_save; } =20 for (i =3D 0; i < data->nr_pclks; i++) { struct clk *clk =3D of_clk_get(dev->of_node, i); =20 if (IS_ERR(clk)) { - kfree(data->clk_save); while (--i >=3D 0) clk_put(data->pclks[i]); - return PTR_ERR(clk); + ret =3D PTR_ERR(clk); + goto free_sysreg_save; } data->pclks[i] =3D clk; } =20 return 0; + +free_sysreg_save: + kfree(data->clk_sysreg_save); +free_clk_save: + kfree(data->clk_save); + return ret; } =20 /** @@ -305,7 +325,7 @@ int __init exynos_arm64_register_cmu_pm(struct platform= _device *pdev, samsung_cmu_register_clocks(data->ctx, cmu, np); samsung_clk_of_add_provider(dev->of_node, data->ctx); /* sysreg DT nodes reference a clock in this CMU */ - samsung_en_dyn_root_clk_gating(np, data->ctx, cmu); + samsung_en_dyn_root_clk_gating(np, data->ctx, cmu, true); pm_runtime_put_sync(dev); =20 return 0; diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c index 417ec1786b5e77e17dda4022b417c1c6b79c59ab..9f68f079fd552f8dfb6898dbfb4= 7dec0e84c626c 100644 --- a/drivers/clk/samsung/clk.c +++ b/drivers/clk/samsung/clk.c @@ -496,7 +496,8 @@ void __init samsung_cmu_register_clocks(struct samsung_= clk_provider *ctx, /* Enable Dynamic Root Clock Gating (DRCG) of bus components */ void samsung_en_dyn_root_clk_gating(struct device_node *np, struct samsung_clk_provider *ctx, - const struct samsung_cmu_info *cmu) + const struct samsung_cmu_info *cmu, + bool cmu_has_pm) { if (!ctx->auto_clock_gate) return; @@ -513,10 +514,16 @@ void samsung_en_dyn_root_clk_gating(struct device_nod= e *np, regmap_write_bits(ctx->sysreg, ctx->memclk_offset, MEMCLK_EN, 0x0); =20 - samsung_clk_extended_sleep_init(NULL, ctx->sysreg, - cmu->sysreg_clk_regs, - cmu->nr_sysreg_clk_regs, - NULL, 0); + if (!cmu_has_pm) + /* + * When a CMU has PM support, clocks are saved/restored + * via its PM handlers, so only register them with the + * syscore suspend / resume paths if PM is not in use. + */ + samsung_clk_extended_sleep_init(NULL, ctx->sysreg, + cmu->sysreg_clk_regs, + cmu->nr_sysreg_clk_regs, + NULL, 0); } } =20 @@ -548,7 +555,7 @@ struct samsung_clk_provider * __init samsung_cmu_regist= er_one( samsung_clk_of_add_provider(np, ctx); =20 /* sysreg DT nodes reference a clock in this CMU */ - samsung_en_dyn_root_clk_gating(np, ctx, cmu); + samsung_en_dyn_root_clk_gating(np, ctx, cmu, false); =20 return ctx; } diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index a56aa3be54d817cd24bf2bc29427e783a1a9a859..b1192ca03db5035cc485771ff55= 97cf132234a2a 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -476,7 +476,8 @@ struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump( =20 void samsung_en_dyn_root_clk_gating(struct device_node *np, struct samsung_clk_provider *ctx, - const struct samsung_cmu_info *cmu); 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[34.141.175.244]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6507be651a4sm10642182a12.16.2026.01.09.09.27.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jan 2026 09:27:27 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Fri, 09 Jan 2026 17:27:25 +0000 Subject: [PATCH 3/3] clk: samsung: allow runtime PM with auto clock gating Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260109-clk-samsung-autoclk-updates-v1-3-2394dcf242a9@linaro.org> References: <20260109-clk-samsung-autoclk-updates-v1-0-2394dcf242a9@linaro.org> In-Reply-To: <20260109-clk-samsung-autoclk-updates-v1-0-2394dcf242a9@linaro.org> To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd Cc: Peter Griffin , Tudor Ambarus , Will McVicker , Juan Yescas , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 When automatic clock gating is enabled, runtime PM (RPM) isn't entered even if enabled for a CMU if a sysreg clock exists and is provided by this CMU (as is generally the case). The reason is that this driver acquires a CMU's sysreg registers using syscon_regmap_lookup_by_phandle() which ends up preparing the sysreg clock. Given the sysreg clock is provided by this CMU, this CMU's usage count is therefore bumped and RPM can not be entered as this CMU never becomes idle. Switch to using device_node_to_regmap() which doesn't handle resources (the clock), leaving the CMU's usage count unaffected. Note1: sysreg clock handling is completely removed with this commit because sysreg register access is only required during suspend/resume. In the runtime suspend case, we would have to enable the clock to read the registers, but we can not do that as that would cause a resume of this driver which is not allowed. This is not a problem because we would only need to handle the clock manually if automatic clock gating wasn't enabled in the first. This code is only relevant if automatic clock gating is enabled, though. Fixes: 298fac4f4b96 ("clk: samsung: Implement automatic clock gating mode f= or CMUs") Signed-off-by: Andr=C3=A9 Draszik --- drivers/clk/samsung/clk.c | 92 +++++++++++++++++++++++++++++++++++--------= ---- drivers/clk/samsung/clk.h | 2 ++ 2 files changed, 71 insertions(+), 23 deletions(-) diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c index 9f68f079fd552f8dfb6898dbfb47dec0e84c626c..6515df81fcbc79b90f5262843e6= 7575f6a4e0dda 100644 --- a/drivers/clk/samsung/clk.c +++ b/drivers/clk/samsung/clk.c @@ -9,11 +9,13 @@ */ =20 #include +#include #include #include #include #include #include +#include #include #include #include @@ -489,6 +491,50 @@ void __init samsung_cmu_register_clocks(struct samsung= _clk_provider *ctx, samsung_clk_register_cpu(ctx, cmu->cpu_clks, cmu->nr_cpu_clks); } =20 +static int samsung_get_sysreg_regmap(struct device_node *np, + struct samsung_clk_provider *ctx) +{ + struct device_node *sysreg_np; + struct clk *sysreg_clk; + struct regmap *regmap; + int ret; + + sysreg_np =3D of_parse_phandle(np, "samsung,sysreg", 0); + if (!sysreg_np) + return -ENODEV; + + sysreg_clk =3D of_clk_get(sysreg_np, 0); + if (IS_ERR(sysreg_clk)) { + ret =3D PTR_ERR(sysreg_clk); + /* clock is optional */ + if (ret !=3D -ENOENT) { + pr_warn("%pOF: Unable to get sysreg clock: %d\n", np, + ret); + goto put_sysreg_np; + } + sysreg_clk =3D NULL; + } + + regmap =3D device_node_to_regmap(sysreg_np); + if (IS_ERR(regmap)) { + ret =3D PTR_ERR(regmap); + pr_warn("%pOF: Unable to get CMU sysreg: %d\n", np, ret); + goto put_clk; + } + + ctx->sysreg_clk =3D sysreg_clk; + ctx->sysreg =3D regmap; + + of_node_put(sysreg_np); + return 0; + +put_clk: + clk_put(sysreg_clk); +put_sysreg_np: + of_node_put(sysreg_np); + return ret; +} + /* Each bit enable/disables DRCG of a bus component */ #define DRCG_EN_MSK GENMASK(31, 0) #define MEMCLK_EN BIT(0) @@ -499,32 +545,32 @@ void samsung_en_dyn_root_clk_gating(struct device_nod= e *np, const struct samsung_cmu_info *cmu, bool cmu_has_pm) { + int ret; + if (!ctx->auto_clock_gate) return; =20 - ctx->sysreg =3D syscon_regmap_lookup_by_phandle(np, "samsung,sysreg"); - if (IS_ERR(ctx->sysreg)) { - pr_warn("%pOF: Unable to get CMU sysreg\n", np); - ctx->sysreg =3D NULL; - } else { - /* Enable DRCG for all bus components */ - regmap_write(ctx->sysreg, ctx->drcg_offset, DRCG_EN_MSK); - /* Enable memclk gate (not present on all sysreg) */ - if (ctx->memclk_offset) - regmap_write_bits(ctx->sysreg, ctx->memclk_offset, - MEMCLK_EN, 0x0); - - if (!cmu_has_pm) - /* - * When a CMU has PM support, clocks are saved/restored - * via its PM handlers, so only register them with the - * syscore suspend / resume paths if PM is not in use. - */ - samsung_clk_extended_sleep_init(NULL, ctx->sysreg, - cmu->sysreg_clk_regs, - cmu->nr_sysreg_clk_regs, - NULL, 0); - } + ret =3D samsung_get_sysreg_regmap(np, ctx); + if (ret) + return; + + /* Enable DRCG for all bus components */ + regmap_write(ctx->sysreg, ctx->drcg_offset, DRCG_EN_MSK); + /* Enable memclk gate (not present on all sysreg) */ + if (ctx->memclk_offset) + regmap_write_bits(ctx->sysreg, ctx->memclk_offset, + MEMCLK_EN, 0x0); + + if (!cmu_has_pm) + /* + * When a CMU has PM support, clocks are saved/restored via its + * PM handlers, so only register them with the syscore + * suspend / resume paths if PM is not in use. + */ + samsung_clk_extended_sleep_init(NULL, ctx->sysreg, + cmu->sysreg_clk_regs, + cmu->nr_sysreg_clk_regs, + NULL, 0); } =20 /* diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index b1192ca03db5035cc485771ff5597cf132234a2a..deb426fbb0942f21b63c583f0ad= 55738239b04e4 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -21,6 +21,7 @@ * @reg_base: virtual address for the register base * @dev: clock provider device needed for runtime PM * @sysreg: syscon regmap for clock-provider sysreg controller + * @sysreg_clk: clock for sysreg access, if required * @lock: maintains exclusion between callbacks for a given clock-provider * @auto_clock_gate: enable auto clk mode for all clocks in clock-provider * @gate_dbg_offset: gate debug reg offset. Used for all gates in auto clk= mode @@ -33,6 +34,7 @@ struct samsung_clk_provider { void __iomem *reg_base; struct device *dev; struct regmap *sysreg; + struct clk *sysreg_clk; spinlock_t lock; bool auto_clock_gate; u32 gate_dbg_offset; --=20 2.52.0.457.g6b5491de43-goog