From nobody Sun Feb 8 00:49:27 2026 Received: from out30-98.freemail.mail.aliyun.com (out30-98.freemail.mail.aliyun.com [115.124.30.98]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19CDF39A811 for ; Thu, 8 Jan 2026 13:49:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.98 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767880153; cv=none; b=Kg82yZZdJ+U94hmJha9uZX7TSLnXmxQdmmtrWXsSQx9id0PP2X0nCf+17aOo5ciXt61HGdRz6906VF0PPnqtp0lnPfqgE9A2KLT5Q0kXbPNSsqGGvn60oJEkk8zRf+gkybl/KwYiN5BTmghL8F6R9Wn+TWU/OSSqMhhDcg/C5js= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767880153; c=relaxed/simple; bh=IP6v91sqECvO+CLDQQ/CAC75x1XVtVY9Hf/auCzttIU=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=pR4yJzXHSPs4BnPlOPCV+I3tl29CqhN7zW5+G+1ur94ND4Ogz/mnasz2sEmGS1jLVuolM079R8NJrXDHxy9bzp9MMViPyE5AYVnz7AZrGmHgVQCc3f1J0jrWIcp3Z8Jla2HeaIiMoFcwPxH5CSbLIT9vNLlLu9CK+6kiTBlHoNY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=pidhXKH6; arc=none smtp.client-ip=115.124.30.98 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="pidhXKH6" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1767880141; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=/DggpkpQ+sZ9M+sA9W097wq5BtxSRcjoGTAICDIz5D0=; b=pidhXKH66NEnahnl443Bvmeiyu3J4Dvb7nX3D/GdzTHeJrvzXFZjfY2e+92HpQjNGm2Fob1HClwL3pmpqgruLp8CEp5SdWbrbATtM6Ei9POop+Ot2g6GLXG+0oQd/GvDKefBZsyWDK9SY3vwx5M76gDcuUyLFDR13qMn5LZgGxs= Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0WwcviKM_1767880138 cluster:ay36) by smtp.aliyun-inc.com; Thu, 08 Jan 2026 21:49:00 +0800 From: fangyu.yu@linux.alibaba.com To: tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr Cc: guoren@kernel.org, ajones@ventanamicro.com, iommu@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Fangyu Yu Subject: [PATCH] iommu/riscv: Add IOTINVAL after updating DDT/PDT entries Date: Thu, 8 Jan 2026 21:48:55 +0800 Message-Id: <20260108134855.91341-1-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fangyu Yu Add riscv_iommu_iodir_iotinval() to perform required TLB and context cache invalidations after updating DDT or PDT entries, as mandated by the RISC-V IOMMU specification (Section 6.3.1 and 6.3.2). Signed-off-by: Fangyu Yu Reviewed-by: Andrew Jones --- drivers/iommu/riscv/iommu.c | 85 +++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index d9429097a2b5..2900170133fc 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -996,7 +996,82 @@ static void riscv_iommu_iotlb_inval(struct riscv_iommu= _domain *domain, } =20 #define RISCV_IOMMU_FSC_BARE 0 +/* + * This function sends IOTINVAL commands as required by the RISC-V + * IOMMU specification (Section 6.3.1 and 6.3.2 in 1.0 spec version) + * after modifying DDT or PDT entries + */ +static void riscv_iommu_iodir_iotinval(struct riscv_iommu_device *iommu, + bool inval_pdt, unsigned long iohgatp, + struct riscv_iommu_dc *dc, struct riscv_iommu_pc *pc) +{ + struct riscv_iommu_command cmd; =20 + if (FIELD_GET(RISCV_IOMMU_DC_IOHGATP_MODE, iohgatp) =3D=3D + RISCV_IOMMU_DC_IOHGATP_MODE_BARE) { + if (inval_pdt) { + /* + * IOTINVAL.VMA with GV=3DAV=3D0, and PSCV=3D1, and + * PSCID=3DPC.PSCID + */ + riscv_iommu_cmd_inval_vma(&cmd); + riscv_iommu_cmd_inval_set_pscid(&cmd, + FIELD_GET(RISCV_IOMMU_PC_TA_PSCID, pc->ta)); + } else { + if (FIELD_GET(RISCV_IOMMU_DC_TC_PDTV, dc->tc) || ( + FIELD_GET(RISCV_IOMMU_DC_FSC_MODE, dc->fsc) =3D=3D + RISCV_IOMMU_DC_FSC_MODE_BARE)) { + /* IOTINVAL.VMA with GV=3DAV=3DPSCV=3D0 */ + riscv_iommu_cmd_inval_vma(&cmd); + } else { + /* + * IOTINVAL.VMA with GV=3DAV=3D0, and PSCV=3D1, and + * PSCID=3DDC.ta.PSCID + */ + riscv_iommu_cmd_inval_vma(&cmd); + riscv_iommu_cmd_inval_set_pscid(&cmd, + FIELD_GET(RISCV_IOMMU_DC_TA_PSCID, dc->ta)); + } + } + } else { + if (inval_pdt) { + /* + * IOTINVAL.VMA with GV=3D1, AV=3D0, and PSCV=3D1, and + * GSCID=3DDC.iohgatp.GSCID, PSCID=3DPC.PSCID + */ + riscv_iommu_cmd_inval_vma(&cmd); + riscv_iommu_cmd_inval_set_gscid(&cmd, + FIELD_GET(RISCV_IOMMU_DC_IOHGATP_GSCID, iohgatp)); + riscv_iommu_cmd_inval_set_pscid(&cmd, + FIELD_GET(RISCV_IOMMU_PC_TA_PSCID, pc->ta)); + } else { + /* + * IOTINVAL.VMA with GV=3D1,AV=3DPSCV=3D0,and + * GSCID=3DDC.iohgatp.GSCID + */ + riscv_iommu_cmd_inval_vma(&cmd); + riscv_iommu_cmd_inval_set_gscid(&cmd, + FIELD_GET(RISCV_IOMMU_DC_IOHGATP_GSCID, iohgatp)); + + /* + * IOTINVAL.GVMA with GV=3D1,AV=3D0,and + * GSCID=3DDC.iohgatp.GSCID + */ + /* + * For now, the Second-Stage feature have not yet been merged, so + * let's comment out the code first. + */ +#if 0 + riscv_iommu_cmd_send(iommu, &cmd); + memset(&cmd, 0, sizeof(cmd)); + riscv_iommu_cmd_inval_gvma(&cmd); + riscv_iommu_cmd_inval_set_gscid(&cmd, + FIELD_GET(RISCV_IOMMU_DC_IOHGATP_GSCID, iohgatp)); +#endif + } + } + riscv_iommu_cmd_send(iommu, &cmd); +} /* * Update IODIR for the device. * @@ -1031,6 +1106,11 @@ static void riscv_iommu_iodir_update(struct riscv_io= mmu_device *iommu, riscv_iommu_cmd_iodir_inval_ddt(&cmd); riscv_iommu_cmd_iodir_set_did(&cmd, fwspec->ids[i]); riscv_iommu_cmd_send(iommu, &cmd); + /* + * For now, the SVA and PASID features have not yet been merged, the + * default configuration is inval_pdt=3Dfalse and pc=3DNULL. + */ + riscv_iommu_iodir_iotinval(iommu, false, dc->iohgatp, dc, NULL); sync_required =3D true; } =20 @@ -1055,6 +1135,11 @@ static void riscv_iommu_iodir_update(struct riscv_io= mmu_device *iommu, /* Invalidate device context after update */ riscv_iommu_cmd_iodir_inval_ddt(&cmd); riscv_iommu_cmd_iodir_set_did(&cmd, fwspec->ids[i]); + /* + * For now, the SVA and PASID features have not yet been merged, the + * default configuration is inval_pdt=3Dfalse and pc=3DNULL. + */ + riscv_iommu_iodir_iotinval(iommu, false, dc->iohgatp, dc, NULL); riscv_iommu_cmd_send(iommu, &cmd); } =20 --=20 2.50.1