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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jan 2026 08:54:13.4511 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 14665c1d-777a-4f32-4405-08de4e937f40 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.194];Helo=[lewvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR10MB997550 Content-Type: text/plain; charset="utf-8" Each A72 core has one watchdog instance associated with it. Since J742S2 has 4 A72 cores, it is incorrect to have 8 watchdog instances in the j742s2-j784s4 common file. Remove the last 4 extra watchdogs from the common file and add them only for J784S4 which has 8 A72 cores and thus 8 watchdog instances associated with them. Fixes: 9cc161a4509c ("arm64: dts: ti: Refactor J784s4 SoC files to a common= file") Signed-off-by: Abhash Kumar Jha --- Changes in v3: - Improve the commit description and subject. - Link to v2: https://lore.kernel.org/all/20260105050557.3459321-1-a-kumar2= @ti.com/ Changes in v2: - Added fixes tag in the commit message. - Link to v1: https://lore.kernel.org/all/20251224055410.208516-1-a-kumar2@= ti.com/T/#u .../dts/ti/k3-j784s4-j742s2-main-common.dtsi | 36 ------------------- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 36 +++++++++++++++++++ 2 files changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arc= h/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index 9cc0901d58fb..c2636e624f18 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -2378,42 +2378,6 @@ watchdog3: watchdog@2230000 { assigned-clock-parents =3D <&k3_clks 351 4>; }; =20 - watchdog4: watchdog@2240000 { - compatible =3D "ti,j7-rti-wdt"; - reg =3D <0x00 0x2240000 0x00 0x100>; - clocks =3D <&k3_clks 352 0>; - power-domains =3D <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks =3D <&k3_clks 352 0>; - assigned-clock-parents =3D <&k3_clks 352 4>; - }; - - watchdog5: watchdog@2250000 { - compatible =3D "ti,j7-rti-wdt"; - reg =3D <0x00 0x2250000 0x00 0x100>; - clocks =3D <&k3_clks 353 0>; - power-domains =3D <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks =3D <&k3_clks 353 0>; - assigned-clock-parents =3D <&k3_clks 353 4>; - }; - - watchdog6: watchdog@2260000 { - compatible =3D "ti,j7-rti-wdt"; - reg =3D <0x00 0x2260000 0x00 0x100>; - clocks =3D <&k3_clks 354 0>; - power-domains =3D <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks =3D <&k3_clks 354 0>; - assigned-clock-parents =3D <&k3_clks 354 4>; - }; - - watchdog7: watchdog@2270000 { - compatible =3D "ti,j7-rti-wdt"; - reg =3D <0x00 0x2270000 0x00 0x100>; - clocks =3D <&k3_clks 355 0>; - power-domains =3D <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks =3D <&k3_clks 355 0>; - assigned-clock-parents =3D <&k3_clks 355 4>; - }; - /* * The following RTI instances are coupled with MCU R5Fs, c7x and * GPU so keeping them reserved as these will be used by their diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index 0160fe0da983..ffc61ec77635 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -113,6 +113,42 @@ serdes2: serdes@5020000 { status =3D "disabled"; }; }; + + watchdog4: watchdog@2240000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x2240000 0x00 0x100>; + clocks =3D <&k3_clks 352 0>; + power-domains =3D <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 352 0>; + assigned-clock-parents =3D <&k3_clks 352 4>; + }; + + watchdog5: watchdog@2250000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x2250000 0x00 0x100>; + clocks =3D <&k3_clks 353 0>; + power-domains =3D <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 353 0>; + assigned-clock-parents =3D <&k3_clks 353 4>; + }; + + watchdog6: watchdog@2260000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x2260000 0x00 0x100>; + clocks =3D <&k3_clks 354 0>; + power-domains =3D <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 354 0>; + assigned-clock-parents =3D <&k3_clks 354 4>; + }; + + watchdog7: watchdog@2270000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x2270000 0x00 0x100>; + clocks =3D <&k3_clks 355 0>; + power-domains =3D <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 355 0>; + assigned-clock-parents =3D <&k3_clks 355 4>; + }; }; =20 &scm_conf { --=20 2.34.1