From nobody Mon Feb 9 08:29:51 2026 Received: from lgeamrelo12.lge.com (lgeamrelo12.lge.com [156.147.23.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72FB534AAF9 for ; Thu, 8 Jan 2026 08:53:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=156.147.23.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767862389; cv=none; b=oElR9fo4KYEoqJSL5zkkXEpmgANG4RLZWDN9R+RNd59NrHP83po7VUduusfBuPdtHZ7yCZf3E2gRnWPogaLeWJSAZeb0IpY9gf8ypYhT21tzQutdwtK/EVr5XoBGShzje2VrR6TvxzMRkolbKdPy+5Qd7j9LieDKKM8JRXoi1es= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767862389; c=relaxed/simple; bh=QYzkqc3TtzgYt12H2CQUxGunuxqyRvPE+I9IezaYiCA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=IMmWPpskWd0XqC/Kt5qpJzaFtY49wry5+DtSnl+ixAAanLn3agdwuaBLJiK+5hDUMsdAvunSjfg5REKq/hSSvc7JIXUkf8YHdUdN35JIvYdhfIJH5lr4nYKzioTVvUyBta9eNCwdD2ATYRIid0iG7CI+op2zLXrGj/oYA6bRjpg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lge.com; spf=pass smtp.mailfrom=lge.com; arc=none smtp.client-ip=156.147.23.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lge.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lge.com Received: from unknown (HELO lgeamrelo04.lge.com) (156.147.1.127) by 156.147.23.52 with ESMTP; 8 Jan 2026 17:22:59 +0900 X-Original-SENDERIP: 156.147.1.127 X-Original-MAILFROM: chanho.min@lge.com Received: from unknown (HELO localhost.localdomain) (10.178.31.96) by 156.147.1.127 with ESMTP; 8 Jan 2026 17:22:59 +0900 X-Original-SENDERIP: 10.178.31.96 X-Original-MAILFROM: chanho.min@lge.com From: Chanho Min To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Neil Armstrong , Kever Yang , Kael D'Alcamo , Manivannan Sadhasivam , Lad Prabhakar Cc: Chanho Min , Gunho Lee , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/3] arm64: dts: lg: Initial support for LG1215 SoC and reference board Date: Thu, 8 Jan 2026 17:22:13 +0900 Message-Id: <20260108082213.6545-4-chanho.min@lge.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260108082213.6545-1-chanho.min@lge.com> References: <20260108082213.6545-1-chanho.min@lge.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add initial device tree support for LG Electronics LG1215 SoC and its reference development board. This patch introduces: - lg1215.dtsi : SoC level device tree include file - lg1215-ref.dts : Reference board specific file - Makefile update to build lg1215-ref.dtb Currently supported minimal hardware description: - Quad ARM Cortex-A78 CPU - gic-400 interrupt controller - ARMv8 architected timer - pmu (Performance Monitoring Unit) - pl011 UARTs - pl080 DMA controller - sp804 timers, sp805 watchdog timers - Generic DWMAC ethernet controller This is the minimal initial bring-up version. More peripherals (mmc, gpio, pinctrl, etc.) will be added in follow-up patches. Signed-off-by: Chanho Min --- arch/arm64/boot/dts/lg/Makefile | 1 + arch/arm64/boot/dts/lg/lg1215-ref.dts | 34 +++ arch/arm64/boot/dts/lg/lg1215.dtsi | 304 ++++++++++++++++++++++++++ 3 files changed, 339 insertions(+) create mode 100644 arch/arm64/boot/dts/lg/lg1215-ref.dts create mode 100644 arch/arm64/boot/dts/lg/lg1215.dtsi diff --git a/arch/arm64/boot/dts/lg/Makefile b/arch/arm64/boot/dts/lg/Makef= ile index 4c3959e24e1b..e60a5bd35327 100644 --- a/arch/arm64/boot/dts/lg/Makefile +++ b/arch/arm64/boot/dts/lg/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_LG1K) +=3D lg1312-ref.dtb dtb-$(CONFIG_ARCH_LG1K) +=3D lg1313-ref.dtb +dtb-$(CONFIG_ARCH_LG1K) +=3D lg1215-ref.dtb diff --git a/arch/arm64/boot/dts/lg/lg1215-ref.dts b/arch/arm64/boot/dts/lg= /lg1215-ref.dts new file mode 100644 index 000000000000..fd24ed450037 --- /dev/null +++ b/arch/arm64/boot/dts/lg/lg1215-ref.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for lg1215 Reference Board. + * + * Copyright (C) 2026, LG Electronics + */ + +/dts-v1/; + +#include "lg1215.dtsi" + +/ { + model =3D "LG Electronics, TV SoC LG1215 Reference Board"; + compatible =3D "lge,lg1215-ref", "lge,lg1215"; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + serial2 =3D &uart2; + }; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x0 0x00000000 0x0 0xbc400000>; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&uart0 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/lg/lg1215.dtsi b/arch/arm64/boot/dts/lg/lg= 1215.dtsi new file mode 100644 index 000000000000..2f926395ae8a --- /dev/null +++ b/arch/arm64/boot/dts/lg/lg1215.dtsi @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for lg1215 SoC + * + * Copyright (C) 2026, LG Electronics + */ + +#include +#include + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + + interrupt-parent =3D <&gic>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x00000000>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu0_opp_table>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x00010000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x00010000>; + next-level-cache =3D <&L2_0>; + L2_0: l2-cache@0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + cache-size =3D <0x00040000>; + cache-unified; + next-level-cache =3D <&L3>; + }; + }; + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x00000100>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu0_opp_table>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x00010000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x00010000>; + next-level-cache =3D <&L2_1>; + L2_1: l2-cache@100 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + cache-size =3D <0x00040000>; + cache-unified; + next-level-cache =3D <&L3>; + }; + }; + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x00000200>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu0_opp_table>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x00010000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x00010000>; + next-level-cache =3D <&L2_2>; + L2_2: l2-cache@200 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + cache-size =3D <0x00040000>; + cache-unified; + next-level-cache =3D <&L3>; + }; + }; + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x00000300>; + enable-method =3D "psci"; + operating-points-v2 =3D <&cpu0_opp_table>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + d-cache-size =3D <0x00010000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + i-cache-size =3D <0x00010000>; + next-level-cache =3D <&L2_3>; + L2_3: l2-cache@300 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + cache-size =3D <0x00040000>; + cache-unified; + next-level-cache =3D <&L3>; + }; + }; + L3: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + cache-size =3D <0x00100000>; + cache-unified; + }; + }; + + psci { + compatible =3D "arm,psci"; + method =3D "smc"; + cpu_suspend =3D <0xc4000001>; + cpu_off =3D <0xc4000002>; + cpu_on =3D <0xc4000003>; + }; + + cpu0_opp_table: opp_table@0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-default { + opp-hz =3D /bits/ 64 <1600000000>; + }; + }; + + gic: interrupt-controller@c0000000 { + compatible =3D "arm,gic-400"; + reg =3D <0x0 0xc0001000 0x0 0x1000>, /* GICD */ + <0x0 0xc0002000 0x0 0x2000>, /* GICC */ + <0x0 0xc0004000 0x0 0x2000>, /* GICH */ + <0x0 0xc0006000 0x0 0x2000>; /* GICV */ + #interrupt-cells =3D <3>; + #address-cells =3D <0>; + interrupts =3D ; + + interrupt-controller; + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D , + , + , + ; + interrupt-affinity =3D <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + clks { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clk_xtal: clk-xtal { + compatible =3D "fixed-clock"; + clock-output-names =3D "xtal"; + clock-frequency =3D <50000000>; + + #clock-cells =3D <0>; + }; + + clk_bus: clk-bus { + compatible =3D "fixed-factor-clock"; + clocks =3D <&clk_xtal>; + clock-names =3D "xtal"; + clock-output-names =3D "busclk"; + clock-div =3D <1>; + clock-mult =3D <4>; + + #clock-cells =3D <0>; + }; + }; + + soc { + compatible =3D "simple-bus"; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + interrupt-parent =3D <&gic>; + + dwmac_axi_config: dwmac-axi-config { + snps,rd_osr_lmt =3D <0x07>; + snps,wr_osr_lmt =3D <0x07>; + snps,blen =3D <0 0 16 0 0 0 0>; + }; + ethernet@ca370000 { + compatible =3D "snps,dwmac"; + reg =3D <0x0 0xca370000 0x0 0x2000>; + interrupts =3D ; + interrupt-names =3D "macirq"; + clocks =3D <&clk_bus>, <&clk_bus>; + clock-names =3D "stmmaceth", "pclk"; + max-frame-size =3D <1500>; + phy-mode =3D "mii"; + snps,pbl =3D <2>; + snps,fixed-burst; + snps,multicast-filter-bins =3D <64>; + snps,perfect-filter-entries =3D <32>; + snps,axi-config =3D <&dwmac_axi_config>; + mac-address =3D [ 00 00 00 00 00 00 ]; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethernet-phy@1c { + compatible =3D "ethernet-phy-id001c.c800"; + reg =3D <0x1c>; + interrupts =3D ; + }; + }; + + }; + + amba { + #address-cells =3D <2>; + #size-cells =3D <2>; + + compatible =3D "simple-bus"; + interrupt-parent =3D <&gic>; + ranges; + + timers0: timer@fd100000 { + compatible =3D "arm,sp804", "arm,primecell"; + reg =3D <0x0 0xfd100000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&clk_bus>, <&clk_bus>, <&clk_bus>; + clock-names =3D "timer0clk", "timer1clk", "apb_pclk"; + }; + timers1: timer@fd110000 { + compatible =3D "arm,sp804", "arm,primecell"; + reg =3D <0x0 0xfd110000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&clk_bus>, <&clk_bus>, <&clk_bus>; + clock-names =3D "timer0clk", "timer1clk", "apb_pclk"; + status =3D "disabled"; + }; + wdog: watchdog@fd200000 { + compatible =3D "arm,sp805", "arm,primecell"; + reg =3D <0x0 0xfd200000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + }; + uart0: serial@fe000000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x0 0xfe000000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&clk_bus>, <&clk_bus>; + clock-names =3D "uartclk", "apb_pclk"; + }; + uart1: serial@fe100000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x0 0xfe100000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&clk_bus>, <&clk_bus>; + clock-names =3D "uartclk", "apb_pclk"; + }; + uart2: serial@fe200000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x0 0xfe200000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&clk_bus>, <&clk_bus>; + clock-names =3D "uartclk", "apb_pclk"; + }; + dma: dma@ff200000 { + compatible =3D "arm,pl080", "arm,primecell"; + reg =3D <0x0 0xff200000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&clk_bus>; + clock-names =3D "apb_pclk"; + }; + }; +};