From nobody Tue Feb 10 08:31:35 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E5A63346A6 for ; Thu, 8 Jan 2026 16:59:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767891588; cv=none; b=dFC483yroPJr8D+/Qp2fgnLEwoEQLAx5D/9HToQ+lossFLCPfx9bBSW7najqXZRkFooqxWv/FfcU7TxmG/q1WxCdnu3yK1n+NciZYxAv4XZsgr/sB00Gub3m7/C6Ptysq/P/VOs4+0tMuU6Fvh4dYSP0n+JdHwATCpB28CUHS5E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767891588; c=relaxed/simple; bh=Yl80iODVgcF61pX+l543yMYgtqmrTciYNzPD8N0Aq4o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=m+W8SZva79+M5JFrfpfhVIsG4Hwi2Y3IdFh5zBncPaAY1GOwyQf7CCqWgQB9JI5MGIsbOWtVotg2bbJMNE3A20K2aJwPjfHm5ss96yTYtI/vPagdFcofebUAOfT9tZTU7x22uNn5VG3DqDzjG5y/6/ZYfa5wz+Li1tlBLh1kWVo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=uPcQ2bLA; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="uPcQ2bLA" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 0431F4E42004; Thu, 8 Jan 2026 16:59:46 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id CB5256072B; Thu, 8 Jan 2026 16:59:45 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 267B3103C8889; Thu, 8 Jan 2026 17:59:43 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1767891585; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=QsgGWiMFLmhabGIErgqJOAUgQ784tBeVIxY9n1SL9Sk=; b=uPcQ2bLACBAJu0oM3HVxOs5YQ/P95XBhbQZHy8NnNNiHp4xqvabeUrvNiWlbN1MTb59383 GN5bAKdjv7A8HvNeAtVsG16u4l8PDiCO3CwdQHMNUwDCE7zuI21cXlingDpwiLzUqKJblk 6u8Qs25y91JkLAcdzQuP7MfX4F1tVVB51tP2qt5qcghyUlC5f1r8snTYpZuzVfvlKUMS8u uSskmVQjHhHO0MdzKaW8P3/0Bx+WOxuhzJru/8ISL6hW1CpuWTV7NPdZVSdk1Z4Cm+QITP x+/LEkp5VKTptB54b5DjJrupbCQpm+JWQTd07hnTcc+0HWIHi5rnitf9RNHGrw== From: Miquel Raynal Date: Thu, 08 Jan 2026 17:57:58 +0100 Subject: [PATCH v2 25/27] mtd: spi-nor: winbond: Add W25H01NWxxIQ CMP locking support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260108-winbond-v6-18-rc1-spi-nor-swp-v2-25-c462ef806130@bootlin.com> References: <20260108-winbond-v6-18-rc1-spi-nor-swp-v2-0-c462ef806130@bootlin.com> In-Reply-To: <20260108-winbond-v6-18-rc1-spi-nor-swp-v2-0-c462ef806130@bootlin.com> To: Tudor Ambarus , Pratyush Yadav , Michael Walle , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet Cc: Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 This chip has support for the locking complement (CMP) feature. Add the relevant bit to enable it. Unfortunately, this chip also comes with an incorrect BFPT table, indicating the Control Register cannot be read back. This is wrong, reading back the register works and has no (observed) side effect. The datasheet clearly indicates supporting the 35h command and all bits from the CR are marked readable. QE and CMP bits are inside, and can be properly read back. Add a fixup for this, otherwise it would defeat the use of the CMP feature. Signed-off-by: Miquel Raynal --- Test run with W25H01NWxxIQ: $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 $bs $all_but_one # all but the first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0000ffff | unlocked | 1 00010000-07ffffff | locked | 2047 $ flash_lock -u /dev/mtd0 $bs 1 # all but the two first $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-0001ffff | unlocked | 2 00020000-07ffffff | locked | 2046 $ flash_lock -u /dev/mtd0 $ flash_lock -l /dev/mtd0 0 $all_but_one # same from the other side $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-07feffff | locked | 2047 07ff0000-07ffffff | unlocked | 1 $ flash_lock -u /dev/mtd0 $(($size - (2 * $bs))) 1 # alll but two $ show_sectors locked sectors region (in hex) | status | #blocks ------------------+----------+-------- 00000000-07fdffff | locked | 2046 07fe0000-07ffffff | unlocked | 2 --- drivers/mtd/spi-nor/winbond.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 959fd4f46eb5..373c0af9daa2 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -366,7 +366,9 @@ static const struct flash_info winbond_nor_parts[] =3D { }, { /* W25Q01NWxxIQ */ .id =3D SNOR_ID(0xef, 0x60, 0x21), - .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_= NOR_4BIT_BP, + .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | + SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP, + .fixups =3D &winbond_rdcr_fixup, }, { /* W25Q01NWxxIM */ .id =3D SNOR_ID(0xef, 0x80, 0x21), --=20 2.51.1