From nobody Mon Feb 9 19:06:07 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 281E14779A9; Thu, 8 Jan 2026 14:22:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767882143; cv=none; b=U5e4hmwJ/UqlPmjjT/bDHXTnSXNaa4DoNcRaz3VFJ5SDi0w5VPHfkoyFyyIav0409VwQhFWOk7FcEw70JMKglPJl0MrPpHcCS/YgvBtGD+L6uJ90VPwYlL8HsMrZx6Pwwn6prt48QDCBQWIHJBRQ0Bm9cH+3NspND1xwROgLvss= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767882143; c=relaxed/simple; bh=0hY9JelA00ZEkrC7+2oNgWXngE5MpTczcLOf3S0rzvw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HR9OBLo0F5XaGDdd4XhYZyNb/tQP4RT4L+6slno0RO/jXeviwc/+3SHrYxnukHDW5nM7g3swq2Ze8TsYRn8WV1FyPvlfd/i84BnZe5ljOaSL6condqNzL7/SGee9DICxAJ3Sl/vJuqO5ts8fZWH+tkz+p7oUn0Au3jr3qIX/YHU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Xa9p18R/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Xa9p18R/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 03F8FC116C6; Thu, 8 Jan 2026 14:22:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1767882143; bh=0hY9JelA00ZEkrC7+2oNgWXngE5MpTczcLOf3S0rzvw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Xa9p18R/CYw8HZX364CEj6bdpfUoIngst996QFzwnZloIOVlrs4JYPOlV5Lf13+f5 u3arwHIrXUjSlndMHQKztRmek++C5yUfk+Uh/j3CJ4+WbFm860ithOP6OkNWMZMwww Kq63DW5zMPtffqiXbQlZJECGHgjpI1qwStauFUezVUIeeVS+x2aC2EnRtFs7GoPaOU AduV82cD28JT+NSTSXFkXZIHrU5HgMZV8dCqsqYUgJ0iNbxUhYBLeObfAYt5Wz+6hR YZz1A98/1h7+Wj+7WjsS0H8Deqc6oc/4zPTOljkM7ZXqxWya76k9Pq+4R/Zlv5FNvS 4KXK+b03at1rw== From: Konrad Dybcio Date: Thu, 08 Jan 2026 15:21:52 +0100 Subject: [PATCH v3 3/3] drm/msm/adreno: Trust the SSoT UBWC config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260108-topic-smem_dramc-v3-3-6b64df58a017@oss.qualcomm.com> References: <20260108-topic-smem_dramc-v3-0-6b64df58a017@oss.qualcomm.com> In-Reply-To: <20260108-topic-smem_dramc-v3-0-6b64df58a017@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Kees Cook , "Gustavo A. R. Silva" , Rob Clark , Sean Paul , Akhil P Oommen , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767882123; l=5689; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=aTiejsPtfF2C+UvMvN1X8HZ/alQLAnwLRugfA9Gd7pc=; b=UjmQRKA9IH21fUaxqBYt5irSAUkUhy+Es7pOm2Z5NFVDKfc2ml4W4kBdGRaHyAs8d7AV7G92I e/hv5XcKzAFCpChVUBWNSPKYA5MDbmS55KybMHemL3qJ/ZlFy/m3Dwl X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Now that the highest_bank_bit value is retrieved from the running system and the global config has been part of the tree for a couple of releases, there is no reason to keep any hardcoded values inside the GPU driver. Get rid of them. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Reviewed-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 11 ++--- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 82 ++---------------------------= ---- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 -- 3 files changed, 6 insertions(+), 92 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a5xx_gpu.c index 56eaff2ee4e4..eba6e74d0084 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1728,7 +1728,6 @@ static struct msm_gpu *a5xx_gpu_init(struct drm_devic= e *dev) struct msm_drm_private *priv =3D dev->dev_private; struct platform_device *pdev =3D priv->gpu_pdev; struct adreno_platform_config *config =3D pdev->dev.platform_data; - const struct qcom_ubwc_cfg_data *common_cfg; struct a5xx_gpu *a5xx_gpu =3D NULL; struct adreno_gpu *adreno_gpu; struct msm_gpu *gpu; @@ -1766,13 +1765,9 @@ static struct msm_gpu *a5xx_gpu_init(struct drm_devi= ce *dev) a5xx_preempt_init(gpu); =20 /* Inherit the common config and make some necessary fixups */ - common_cfg =3D qcom_ubwc_config_get_data(); - if (IS_ERR(common_cfg)) - return ERR_CAST(common_cfg); - - /* Copy the data into the internal struct to drop the const qualifier (te= mporarily) */ - adreno_gpu->_ubwc_config =3D *common_cfg; - adreno_gpu->ubwc_config =3D &adreno_gpu->_ubwc_config; + adreno_gpu->ubwc_config =3D qcom_ubwc_config_get_data(); + if (IS_ERR(adreno_gpu->ubwc_config)) + return ERR_CAST(adreno_gpu->ubwc_config); =20 adreno_gpu->uche_trap_base =3D 0x0001ffffffff0000ull; =20 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 2129d230a92b..3a2429632225 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -729,82 +729,6 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs= [i]); } =20 -static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) -{ - const struct qcom_ubwc_cfg_data *common_cfg; - struct qcom_ubwc_cfg_data *cfg =3D &gpu->_ubwc_config; - - /* Inherit the common config and make some necessary fixups */ - common_cfg =3D qcom_ubwc_config_get_data(); - if (IS_ERR(common_cfg)) - return PTR_ERR(common_cfg); - - /* Copy the data into the internal struct to drop the const qualifier (te= mporarily) */ - *cfg =3D *common_cfg; - - /* Use common config as is for A8x */ - if (!adreno_is_a8xx(gpu)) { - cfg->ubwc_swizzle =3D 0x6; - cfg->highest_bank_bit =3D 15; - } - - if (adreno_is_a610(gpu)) { - cfg->highest_bank_bit =3D 13; - cfg->ubwc_swizzle =3D 0x7; - } - - if (adreno_is_a612(gpu)) - cfg->highest_bank_bit =3D 14; - - if (adreno_is_a618(gpu)) - cfg->highest_bank_bit =3D 14; - - if (adreno_is_a619(gpu)) - /* TODO: Should be 14 but causes corruption at e.g. 1920x1200 on DP */ - cfg->highest_bank_bit =3D 13; - - if (adreno_is_a619_holi(gpu)) - cfg->highest_bank_bit =3D 13; - - if (adreno_is_a621(gpu)) - cfg->highest_bank_bit =3D 13; - - if (adreno_is_a623(gpu)) - cfg->highest_bank_bit =3D 16; - - if (adreno_is_a650(gpu) || - adreno_is_a660(gpu) || - adreno_is_a690(gpu) || - adreno_is_a730(gpu) || - adreno_is_a740_family(gpu)) { - /* TODO: get ddr type from bootloader and use 15 for LPDDR4 */ - cfg->highest_bank_bit =3D 16; - } - - if (adreno_is_a663(gpu)) { - cfg->highest_bank_bit =3D 13; - cfg->ubwc_swizzle =3D 0x4; - } - - if (adreno_is_7c3(gpu)) - cfg->highest_bank_bit =3D 14; - - if (adreno_is_a702(gpu)) - cfg->highest_bank_bit =3D 14; - - if (cfg->highest_bank_bit !=3D common_cfg->highest_bank_bit) - DRM_WARN_ONCE("Inconclusive highest_bank_bit value: %u (GPU) vs %u (UBWC= _CFG)\n", - cfg->highest_bank_bit, common_cfg->highest_bank_bit); - - if (cfg->ubwc_swizzle !=3D common_cfg->ubwc_swizzle) - DRM_WARN_ONCE("Inconclusive ubwc_swizzle value: %u (GPU) vs %u (UBWC_CFG= )\n", - cfg->ubwc_swizzle, common_cfg->ubwc_swizzle); - - gpu->ubwc_config =3D &gpu->_ubwc_config; - - return 0; -} - static void a6xx_set_ubwc_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); @@ -2721,10 +2645,10 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_dev= ice *dev) msm_mmu_set_fault_handler(to_msm_vm(gpu->vm)->mmu, gpu, adreno_gpu->funcs->mmu_fault_handler); =20 - ret =3D a6xx_calc_ubwc_config(adreno_gpu); - if (ret) { + adreno_gpu->ubwc_config =3D qcom_ubwc_config_get_data(); + if (IS_ERR(adreno_gpu->ubwc_config)) { a6xx_destroy(&(a6xx_gpu->base.base)); - return ERR_PTR(ret); + return ERR_CAST(adreno_gpu->ubwc_config); } =20 /* Set up the preemption specific bits and pieces for each ringbuffer */ diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 1d0145f8b3ec..da9a6da7c108 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -237,12 +237,7 @@ struct adreno_gpu { /* firmware: */ const struct firmware *fw[ADRENO_FW_MAX]; =20 - /* - * The migration to the central UBWC config db is still in flight - keep - * a copy containing some local fixups until that's done. - */ const struct qcom_ubwc_cfg_data *ubwc_config; - struct qcom_ubwc_cfg_data _ubwc_config; =20 /* * Register offsets are different between some GPUs. --=20 2.52.0