From nobody Sun Feb 8 18:14:15 2026 Received: from mail-dy1-f174.google.com (mail-dy1-f174.google.com [74.125.82.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07FBA37F11B for ; Thu, 8 Jan 2026 08:58:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.82.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767862731; cv=none; b=CIMq0I4NnuPOgqQp9fyHhKAKR/xfUisZlkpO2Z99n2RVg6hrQJr6BNliWK5Nh6/zFGgzdC0VKSkEn/uWhSgL7ZnxsiuYP56nFyIlgE0ij6xwFBPb4IEtltEXkWbGocvZYrGcqBA4YsAN9j0mngSoeuIVvwIYItlVr7bdeFuVihA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767862731; c=relaxed/simple; bh=oBHErEHnkA1paCau1ARwAjUjnMxGWXWutTLtcVvMytk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mKlI2IoM39tNuOqBoWalAPE+R8bVmvhhUsv30fd2VwN0iI9NAXaik4bBpeG0mkDd6uVxK0mUQFhZVnWejHfPxXgHomR9uQM1iqieEOBqW7H4nC2bdcoRozHolGZCqZeS//vNxsw9kh9r4cln+jHI3AT8tqmae8b1H+nYbAyai+U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=DeRAOpHh; arc=none smtp.client-ip=74.125.82.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="DeRAOpHh" Received: by mail-dy1-f174.google.com with SMTP id 5a478bee46e88-2b04fcfc0daso2609717eec.0 for ; Thu, 08 Jan 2026 00:58:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1767862719; x=1768467519; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=YHgXYcn6j9hrIoVhqdjOMXkUH+ey28hNkJayufBoRxM=; b=DeRAOpHhqS3ZvoI17I8zTfvIojGTJ495HqIPj56MxWS2457Ss6+G3+81H511y89JUs Dr/h5aF75pZqQAzUB7S+ggQ0q/dxE+hKujNSoQxPLgss/pWpGWBIKb0gkzCOcG0FM5Np y3W6Adg0evIDSCn+pkcz2RsptQ+q0+W9Vrc7dYqxeo5AgbZd/jy+B3+1DfoqWM5nxc9j 9DEjqWH8h8kvi2UJZTQ0lGz97uKmt4ia3iSrdTSOaRAXEIB06SOHoDwdoxQ2eJzNyYXr rP8vUwV6AQd5Kek0CO59gU47tlRuv2ZoW5fsVMuiA21TzsUQHwnhq+xOQf941W6R30Vm aSjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767862719; x=1768467519; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=YHgXYcn6j9hrIoVhqdjOMXkUH+ey28hNkJayufBoRxM=; b=KU+It4bMbMZk6OYwQIOLpUkm+55sg3aw1jDPPhQKQwzd5hsdaCywjWZyxa1cBQu1XK 2SfnBnagzYJcq8c4B+T5CjsAfCBLVPJb1OjtCvXq9gjg6UCx4sVZ8tWX3EUFBUzoTDax DyldJvKOc/VxnBA5E0L7cq7zVbKLKKDTTPtt/L4xsJNvZdvguiLtE3VwlZeaYWcJ5OBU IGtwyISRwkshGsaidZg6DOI3/Mb8IyJ516tqib2DQ81ZsJchqsNTyUf5NKrYybkR944U IW2+Nud/yjRhMmcESuXVhKjgnrsNeWkX9rSWFUmFb5NEds7mpHYhMyLAKPaUJJf6KadC dxpA== X-Gm-Message-State: AOJu0YzHuKK6ybUmH9Hk+N/6yHIczg0h0TleIoAsTyAfXjap4cFbwmj5 3TYsHdCbA6DqYtyOZxBX7MYLohpUVVydfM6LH0NS9GyKOSFTUYZsQ6T4ZOssLa6nXm8= X-Gm-Gg: AY/fxX5e9aSz/fWtfbWCAp81bM9yZeYU5uEWOl55Q8zm4EpoOuv2Y8LluPky124giO+ Dm37Zov4MoLQdxpUHmzXY6ucFqCZSgv2hChD51Ko0nlrQFbQLEjbr6PC8gPiBS1keYBcQjhEHS7 5mQs48FpbWFKLwS2yn0Ek72Lo7WJU2ssKvUWHwMcng+ynZQrvHVYDd/feFM74Y51mZSAkw28HeU 04r12AZPh2kq6TFbVCkqirAIt8m6h/DNMPw4gmj7W6hy3ibroe7JYHDjdubsRs7oD4/DaDvl5h3 2UjOVYWD2M0ka8cafwImDLDaIrR25hCsO5ulGQosSAFqImqPWs7+YwIRUehhlXR/XCBIiDB1SiX gkjxVFk1H0Xp86/M0+f58KJ9XKFDqOW21oFW5BYqIg+A2LvSD1XMViQzBhygBAlJYg35G2GgNWc uqDFMQmS+bq287y0kM/wlkR7c= X-Google-Smtp-Source: AGHT+IG+4Su03prYbt6n5qR1nTAfW+7RTrG8/tcfMCDl8OXrQiz833IsM6Hd3eTjjbNcqhMNkJD8+A== X-Received: by 2002:a05:7300:8290:b0:2ae:598e:abe5 with SMTP id 5a478bee46e88-2b17d321a6dmr2554912eec.35.1767862718478; Thu, 08 Jan 2026 00:58:38 -0800 (PST) Received: from sw07.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b170675076sm8833634eec.2.2026.01.08.00.58.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 00:58:37 -0800 (PST) From: Nick Hu Date: Thu, 08 Jan 2026 00:58:24 -0800 Subject: [PATCH v4 1/3] cpuidle: riscv-sbi: Split PM domain init out of the cpuidle driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260108-sifive-pd-drivers-v4-1-2a523d7d51a0@sifive.com> References: <20260108-sifive-pd-drivers-v4-0-2a523d7d51a0@sifive.com> In-Reply-To: <20260108-sifive-pd-drivers-v4-0-2a523d7d51a0@sifive.com> To: "Rafael J. Wysocki" , Daniel Lezcano , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Anup Patel , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Cyan Yang , Nick Hu Cc: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.3 Move the PM domain initialization logic from the RISC-V SBI CPU idle driver into a separate driver. This decouples the power domain setup from cpuidle and allows the generic PM domain framework to be used independently. This change also enables external power domain drivers to operate with the RISC-V SBI CPU idle driver Signed-off-by: Nick Hu --- MAINTAINERS | 2 + drivers/cpuidle/Kconfig.riscv | 13 ++- drivers/cpuidle/Makefile | 1 + drivers/cpuidle/cpuidle-riscv-sbi-domain.c | 176 +++++++++++++++++++++++++= +++ drivers/cpuidle/cpuidle-riscv-sbi.c | 178 ++-----------------------= ---- drivers/cpuidle/cpuidle-riscv-sbi.h | 29 +++++ 6 files changed, 228 insertions(+), 171 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index a0dd762f5648..b52f11602271 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6632,7 +6632,9 @@ M: Anup Patel L: linux-pm@vger.kernel.org L: linux-riscv@lists.infradead.org S: Maintained +F: drivers/cpuidle/cpuidle-riscv-sbi-domain.c F: drivers/cpuidle/cpuidle-riscv-sbi.c +F: drivers/cpuidle/cpuidle-riscv-sbi.h =20 CPUMASK API [RUST] M: Viresh Kumar diff --git a/drivers/cpuidle/Kconfig.riscv b/drivers/cpuidle/Kconfig.riscv index 78518c26af74..b813018ce401 100644 --- a/drivers/cpuidle/Kconfig.riscv +++ b/drivers/cpuidle/Kconfig.riscv @@ -8,8 +8,17 @@ config RISCV_SBI_CPUIDLE depends on RISCV_SBI select DT_IDLE_STATES select CPU_IDLE_MULTIPLE_DRIVERS - select DT_IDLE_GENPD if PM_GENERIC_DOMAINS_OF help Select this option to enable RISC-V SBI firmware based CPU idle - driver for RISC-V systems. This drivers also supports hierarchical + driver for RISC-V systems. + +config RISCV_SBI_CPUIDLE_DOMAIN + bool "RISC-V SBI CPU idle Domain" + depends on RISCV_SBI_CPUIDLE + depends on PM_GENERIC_DOMAINS_OF + select DT_IDLE_GENPD + default y + help + Select this option to enable RISC-V SBI firmware based CPU idle + driver to use PM domains, which is needed to support the hierarchical DT based layout of the idle state. diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile index 1de9e92c5b0f..82595849b75d 100644 --- a/drivers/cpuidle/Makefile +++ b/drivers/cpuidle/Makefile @@ -42,3 +42,4 @@ obj-$(CONFIG_POWERNV_CPUIDLE) +=3D cpuidle-powernv.o ##########################################################################= ##### # RISC-V drivers obj-$(CONFIG_RISCV_SBI_CPUIDLE) +=3D cpuidle-riscv-sbi.o +obj-$(CONFIG_RISCV_SBI_CPUIDLE_DOMAIN) +=3D cpuidle-riscv-sbi-domain.o diff --git a/drivers/cpuidle/cpuidle-riscv-sbi-domain.c b/drivers/cpuidle/c= puidle-riscv-sbi-domain.c new file mode 100644 index 000000000000..24cb70700c22 --- /dev/null +++ b/drivers/cpuidle/cpuidle-riscv-sbi-domain.c @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PM domains for CPUs via genpd - managed by cpuidle-riscv-sbi. + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + * Copyright (c) 2022 Ventana Micro Systems Inc. + */ + +#define pr_fmt(fmt) "cpuidle-riscv-sbi-domain: " fmt + +#include +#include + +#include "cpuidle-riscv-sbi.h" +#include "dt_idle_genpd.h" + +struct sbi_pd_provider { + struct list_head link; + struct device_node *node; +}; + +static LIST_HEAD(sbi_pd_providers); + +static int sbi_cpuidle_pd_power_off(struct generic_pm_domain *pd) +{ + struct genpd_power_state *state =3D &pd->states[pd->state_idx]; + u32 *pd_state; + + if (!state->data) + return 0; + + /* OSI mode is enabled, set the corresponding domain state. */ + pd_state =3D state->data; + sbi_set_domain_state(*pd_state); + + return 0; +} + +static int sbi_pd_init(struct device_node *np, bool use_osi) +{ + struct generic_pm_domain *pd; + struct sbi_pd_provider *pd_provider; + struct dev_power_governor *pd_gov; + int ret =3D -ENOMEM; + + pd =3D dt_idle_pd_alloc(np, sbi_dt_parse_state_node); + if (!pd) + goto out; + + pd_provider =3D kzalloc(sizeof(*pd_provider), GFP_KERNEL); + if (!pd_provider) + goto free_pd; + + pd->flags |=3D GENPD_FLAG_IRQ_SAFE | GENPD_FLAG_CPU_DOMAIN; + + /* Allow power off when OSI is available. */ + if (use_osi) + pd->power_off =3D sbi_cpuidle_pd_power_off; + else + pd->flags |=3D GENPD_FLAG_ALWAYS_ON; + + /* Use governor for CPU PM domains if it has some states to manage. */ + pd_gov =3D pd->states ? &pm_domain_cpu_gov : NULL; + + ret =3D pm_genpd_init(pd, pd_gov, false); + if (ret) + goto free_pd_prov; + + ret =3D of_genpd_add_provider_simple(np, pd); + if (ret) + goto remove_pd; + + pd_provider->node =3D of_node_get(np); + list_add(&pd_provider->link, &sbi_pd_providers); + + pr_debug("init PM domain %s\n", pd->name); + return 0; + +remove_pd: + pm_genpd_remove(pd); +free_pd_prov: + kfree(pd_provider); +free_pd: + dt_idle_pd_free(pd); +out: + pr_err("failed to init PM domain ret=3D%d %pOF\n", ret, np); + return ret; +} + +static void sbi_pd_remove(void) +{ + struct sbi_pd_provider *pd_provider, *it; + struct generic_pm_domain *genpd; + + list_for_each_entry_safe(pd_provider, it, &sbi_pd_providers, link) { + of_genpd_del_provider(pd_provider->node); + + genpd =3D of_genpd_remove_last(pd_provider->node); + if (!IS_ERR(genpd)) + kfree(genpd); + + of_node_put(pd_provider->node); + list_del(&pd_provider->link); + kfree(pd_provider); + } +} + +static int sbi_genpd_probe(struct device_node *np, bool use_osi) +{ + int ret =3D 0, pd_count =3D 0; + + if (!np) + return -ENODEV; + + /* + * Parse child nodes for the "#power-domain-cells" property and + * initialize a genpd/genpd-of-provider pair when it's found. + */ + for_each_child_of_node_scoped(np, node) { + if (!of_property_present(node, "#power-domain-cells")) + continue; + + ret =3D sbi_pd_init(node, use_osi); + if (ret) + goto remove_pd; + + pd_count++; + } + + /* Bail out if not using the hierarchical CPU topology. */ + if (!pd_count) + goto no_pd; + + /* Link genpd masters/subdomains to model the CPU topology. */ + ret =3D dt_idle_pd_init_topology(np); + if (ret) + goto remove_pd; + + return 0; + +remove_pd: + sbi_pd_remove(); + pr_err("failed to create CPU PM domains ret=3D%d\n", ret); +no_pd: + return ret; +} + +static int __init riscv_sbi_idle_init_domains(void) +{ + bool use_osi =3D true; + int cpu; + + /* Detect OSI support based on CPU DT nodes */ + for_each_possible_cpu(cpu) { + struct device_node *np __free(device_node) =3D of_cpu_device_node_get(cp= u); + if (np && + of_property_present(np, "power-domains") && + of_property_present(np, "power-domain-names")) { + continue; + } else { + use_osi =3D false; + break; + } + } + + sbi_set_osi_mode(use_osi); + + /* Populate generic power domains from DT nodes */ + struct device_node *pds_node __free(device_node) =3D + of_find_node_by_path("/cpus/power-domains"); + if (!pds_node) + return 0; + + return sbi_genpd_probe(pds_node, use_osi); +} +core_initcall(riscv_sbi_idle_init_domains); diff --git a/drivers/cpuidle/cpuidle-riscv-sbi.c b/drivers/cpuidle/cpuidle-= riscv-sbi.c index 19be6475d356..95a837a1ba31 100644 --- a/drivers/cpuidle/cpuidle-riscv-sbi.c +++ b/drivers/cpuidle/cpuidle-riscv-sbi.c @@ -28,6 +28,7 @@ #include =20 #include "cpuidle.h" +#include "cpuidle-riscv-sbi.h" #include "dt_idle_states.h" #include "dt_idle_genpd.h" =20 @@ -46,7 +47,12 @@ static DEFINE_PER_CPU(struct sbi_domain_state, domain_st= ate); static bool sbi_cpuidle_use_osi; static bool sbi_cpuidle_use_cpuhp; =20 -static inline void sbi_set_domain_state(u32 state) +void sbi_set_osi_mode(bool use_osi) +{ + sbi_cpuidle_use_osi =3D use_osi; +} + +void sbi_set_domain_state(u32 state) { struct sbi_domain_state *data =3D this_cpu_ptr(&domain_state); =20 @@ -188,7 +194,7 @@ static const struct of_device_id sbi_cpuidle_state_matc= h[] =3D { { }, }; =20 -static int sbi_dt_parse_state_node(struct device_node *np, u32 *state) +int sbi_dt_parse_state_node(struct device_node *np, u32 *state) { int err =3D of_property_read_u32(np, "riscv,sbi-suspend-param", state); =20 @@ -345,177 +351,11 @@ static int sbi_cpuidle_init_cpu(struct device *dev, = int cpu) return ret; } =20 -#ifdef CONFIG_DT_IDLE_GENPD - -static int sbi_cpuidle_pd_power_off(struct generic_pm_domain *pd) -{ - struct genpd_power_state *state =3D &pd->states[pd->state_idx]; - u32 *pd_state; - - if (!state->data) - return 0; - - /* OSI mode is enabled, set the corresponding domain state. */ - pd_state =3D state->data; - sbi_set_domain_state(*pd_state); - - return 0; -} - -struct sbi_pd_provider { - struct list_head link; - struct device_node *node; -}; - -static LIST_HEAD(sbi_pd_providers); - -static int sbi_pd_init(struct device_node *np) -{ - struct generic_pm_domain *pd; - struct sbi_pd_provider *pd_provider; - struct dev_power_governor *pd_gov; - int ret =3D -ENOMEM; - - pd =3D dt_idle_pd_alloc(np, sbi_dt_parse_state_node); - if (!pd) - goto out; - - pd_provider =3D kzalloc(sizeof(*pd_provider), GFP_KERNEL); - if (!pd_provider) - goto free_pd; - - pd->flags |=3D GENPD_FLAG_IRQ_SAFE | GENPD_FLAG_CPU_DOMAIN; - - /* Allow power off when OSI is available. */ - if (sbi_cpuidle_use_osi) - pd->power_off =3D sbi_cpuidle_pd_power_off; - else - pd->flags |=3D GENPD_FLAG_ALWAYS_ON; - - /* Use governor for CPU PM domains if it has some states to manage. */ - pd_gov =3D pd->states ? &pm_domain_cpu_gov : NULL; - - ret =3D pm_genpd_init(pd, pd_gov, false); - if (ret) - goto free_pd_prov; - - ret =3D of_genpd_add_provider_simple(np, pd); - if (ret) - goto remove_pd; - - pd_provider->node =3D of_node_get(np); - list_add(&pd_provider->link, &sbi_pd_providers); - - pr_debug("init PM domain %s\n", pd->name); - return 0; - -remove_pd: - pm_genpd_remove(pd); -free_pd_prov: - kfree(pd_provider); -free_pd: - dt_idle_pd_free(pd); -out: - pr_err("failed to init PM domain ret=3D%d %pOF\n", ret, np); - return ret; -} - -static void sbi_pd_remove(void) -{ - struct sbi_pd_provider *pd_provider, *it; - struct generic_pm_domain *genpd; - - list_for_each_entry_safe(pd_provider, it, &sbi_pd_providers, link) { - of_genpd_del_provider(pd_provider->node); - - genpd =3D of_genpd_remove_last(pd_provider->node); - if (!IS_ERR(genpd)) - kfree(genpd); - - of_node_put(pd_provider->node); - list_del(&pd_provider->link); - kfree(pd_provider); - } -} - -static int sbi_genpd_probe(struct device_node *np) -{ - int ret =3D 0, pd_count =3D 0; - - if (!np) - return -ENODEV; - - /* - * Parse child nodes for the "#power-domain-cells" property and - * initialize a genpd/genpd-of-provider pair when it's found. - */ - for_each_child_of_node_scoped(np, node) { - if (!of_property_present(node, "#power-domain-cells")) - continue; - - ret =3D sbi_pd_init(node); - if (ret) - goto remove_pd; - - pd_count++; - } - - /* Bail out if not using the hierarchical CPU topology. */ - if (!pd_count) - goto no_pd; - - /* Link genpd masters/subdomains to model the CPU topology. */ - ret =3D dt_idle_pd_init_topology(np); - if (ret) - goto remove_pd; - - return 0; - -remove_pd: - sbi_pd_remove(); - pr_err("failed to create CPU PM domains ret=3D%d\n", ret); -no_pd: - return ret; -} - -#else - -static inline int sbi_genpd_probe(struct device_node *np) -{ - return 0; -} - -#endif - static int sbi_cpuidle_probe(struct platform_device *pdev) { int cpu, ret; struct cpuidle_driver *drv; struct cpuidle_device *dev; - struct device_node *pds_node; - - /* Detect OSI support based on CPU DT nodes */ - sbi_cpuidle_use_osi =3D true; - for_each_possible_cpu(cpu) { - struct device_node *np __free(device_node) =3D of_cpu_device_node_get(cp= u); - if (np && - of_property_present(np, "power-domains") && - of_property_present(np, "power-domain-names")) { - continue; - } else { - sbi_cpuidle_use_osi =3D false; - break; - } - } - - /* Populate generic power domains from DT nodes */ - pds_node =3D of_find_node_by_path("/cpus/power-domains"); - if (pds_node) { - ret =3D sbi_genpd_probe(pds_node); - of_node_put(pds_node); - if (ret) - return ret; - } =20 /* Initialize CPU idle driver for each present CPU */ for_each_present_cpu(cpu) { @@ -576,4 +416,4 @@ static int __init sbi_cpuidle_init(void) =20 return 0; } -arch_initcall(sbi_cpuidle_init); +device_initcall(sbi_cpuidle_init); diff --git a/drivers/cpuidle/cpuidle-riscv-sbi.h b/drivers/cpuidle/cpuidle-= riscv-sbi.h new file mode 100644 index 000000000000..f9a0e81d1417 --- /dev/null +++ b/drivers/cpuidle/cpuidle-riscv-sbi.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __CPUIDLE_RISCV_SBI_H +#define __CPUIDLE_RISCV_SBI_H + +#ifdef CONFIG_RISCV_SBI_CPUIDLE + +void sbi_set_osi_mode(bool use_osi); +void sbi_set_domain_state(u32 state); +int sbi_dt_parse_state_node(struct device_node *np, u32 *state); + +#else + +static inline void sbi_set_osi_mode(bool use_osi) +{ +} + +static inline void sbi_set_domain_state(u32 state) +{ +} + +static inline int sbi_dt_parse_state_node(struct device_node *np, u32 *sta= te) +{ + return 0; +} + +#endif + +#endif /* __CPUIDLE_RISCV_SBI_H */ --=20 2.43.7 From nobody Sun Feb 8 18:14:15 2026 Received: from mail-dy1-f178.google.com (mail-dy1-f178.google.com [74.125.82.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BEFC37E2F0 for ; Thu, 8 Jan 2026 08:58:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.82.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767862730; cv=none; b=jkdFBlGTieLkzoL6g/f0XR0FB6ggPnqhnYlhk1GaxS6dYEkn5wnPHLeKRRkn+F2lNCRpcBxkFlu04lm1jhP5EZpEofuFXoNGbpstu5IhdcFAAC6IjuxQya/gCqoqmyxWfdiEDgcgfZnOf7VQPi1hPBH4+oQ8bYu/dY9hCjcsx9k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767862730; c=relaxed/simple; bh=g6bPLC0uhgJGfGzdr7jciYO1TYQnfhcR7gx4FwvNLV0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cN1qT6c216ADw71ePkVnEB3r4kAUjTB/eOfK1Yx+Snz8Lp+o4uI4cWPcBrR0oOJFU6ptO4XQuL3Sy3geivYdjo1IkzeSfMx9FJqjPZbMsPbky2UH2fAqZZpx9jQG2z3ZDhKX8LrjpbIbIb+LipqO0Sf6yNYHE2Y9xRPBHBtHaoA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=WRwvQoOl; arc=none smtp.client-ip=74.125.82.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="WRwvQoOl" Received: by mail-dy1-f178.google.com with SMTP id 5a478bee46e88-2ae255ac8bdso3533743eec.0 for ; Thu, 08 Jan 2026 00:58:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1767862720; x=1768467520; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=OPMKY7Ve7//uye45o8kcyRKc3naps5DDhGu7uTz/qYs=; b=WRwvQoOlSBPKAnSmbospln+srPGi8OdXfmt+UX42zam33NA29NOmRIGR3x2nAfiWRp xCdbjmTUpJtn7RUn9oUPkTQZea7xVpUifZ5F7ymYrSE1vZY98Ux/ej8ou9RoH/sFpsG6 z8lh8GHzWPP3ZZID67LdlkfoSn6FPaOsSFHf25BS3rbA7sL3EEXisb8uGhnldxE2/OPO 6T/Dwba/IpRRGhxG3Tvxh/64dOv5euUbmdwQkG9VW52J0d00vaAx3kRuuTyIVAYRdW3S Ig1lbN/jMeMjwcuWhdEmyqsUU8xueOhCMXpEbr7gpakoDmnkdCsYAmAt1QJrSYka1UKX R6ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767862720; x=1768467520; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=OPMKY7Ve7//uye45o8kcyRKc3naps5DDhGu7uTz/qYs=; b=n31brrkRSqdhHDpyqu4i4Pjm0Z98ZqyFs8taJHWYyluEXoZRik2CYMDkY8HSES4vlj jQRQOSwXHFL1Y7ck4yggHgA+okj0yjJBEq2YEnqQVZwfD1OO8q2Rpl2cJUf2//kS8E34 PN7hEuCUaUf/ZFSG8FcWwJS5advHuaL+YFeP5lESYg0O6du+h0+Xu3EGN6riaiVLGPBH BMD85/fxAdmfstS9jaB6D9GT4zkJIbAVk+I1sKou16I4gcN77W+T+BC8ZzvV0NaEddwD X4PwAZdm8Kii7mGJ9aBBXxqi25+4J2fJ+uEOI7+yLVNxiWDBwa8EvYn6UfTlYlOQSXlU IlXA== X-Gm-Message-State: AOJu0YzLxlwpTvT2ajkjEo577/aLq0F0cBdn7AXjImBN8le1i3hhkDjQ 0KtCaqj9iAie44wsneAK72888QC8ElKYy3sAcI0yhEZAsOoNrHNKXy6jW2ZDPbVa/9E= X-Gm-Gg: AY/fxX4J/wacKEEugcuW2Vvq5NX9PIG5K89CR3/ftSzqymVcHHbaNQkRdSZtgPi99KY LDUzZp/Y691HFrz6YK2mahuoqsuObUlH0Cs4ANNvJwdCu9MwrPuUg+ETYGbthGlLWz3GPzwsGbh 8OGALElR9+ONeyE9oFsD5Bg7hI2OuQvuCsIX//B96wM43AuzswtSbAOXl8D7ANaCts80EXfssca FE/CKtvJdzRWkf/1DEQJuMaBsYot9fj9OmDhEhMl26UZ0qPmpd+k2928lhdmh7ijroDlsJxM5MW z2TLLmxZNSEJRbGvm+u+4jcb/Pe1eQUZu7IM1sjK0O42mAubMR+7FQq/RHiEhLwoaqxTMCYZlB4 AOaR7Z560vPO8jPnNv+srg0XkJPZBSHa/EQlivZ5Oo0Uk+M5NcOZpJXQZ+WrgeHAODWpR6I7g1t Slk91cKpo6+OdARml/tocIFug= X-Google-Smtp-Source: AGHT+IGeM165oEvyVrh+jJ+fHeTSLxMLf2ir5ZaGZt7O8WdBQ16xZQI4McJDAnPHI+CXjXuTmYlcRg== X-Received: by 2002:a05:7300:b09c:b0:2b0:4e86:8163 with SMTP id 5a478bee46e88-2b17d240aeamr3454843eec.13.1767862719638; Thu, 08 Jan 2026 00:58:39 -0800 (PST) Received: from sw07.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b170675076sm8833634eec.2.2026.01.08.00.58.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 00:58:39 -0800 (PST) From: Nick Hu Date: Thu, 08 Jan 2026 00:58:25 -0800 Subject: [PATCH v4 2/3] dt-bindings: power: Add SiFive Domain Management controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260108-sifive-pd-drivers-v4-2-2a523d7d51a0@sifive.com> References: <20260108-sifive-pd-drivers-v4-0-2a523d7d51a0@sifive.com> In-Reply-To: <20260108-sifive-pd-drivers-v4-0-2a523d7d51a0@sifive.com> To: "Rafael J. Wysocki" , Daniel Lezcano , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Anup Patel , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Cyan Yang , Nick Hu Cc: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.3 SiFive Domain Management controller includes the following components - SiFive Tile Management Controller - SiFive Cluster Management Controller - SiFive Core Complex Management Controller These controllers control the clock and power domain of the corresponding domain. Add `- {}` for the first entry [1][2]. Once the SoCs are ready, we will add the SoC compatible string at that time. Links: - [1] https://lore.kernel.org/lkml/20250311195953.GA14239-robh@kernel.org/ - [2] https://lore.kernel.org/lkml/CAKddAkAzDGL-7MbroRqQnZzPXOquUMKNuGGppqB= -d_XZXbcvBA@mail.gmail.com/T/#t Reviewed-by: Samuel Holland Reviewed-by: Rob Herring (Arm) Signed-off-by: Nick Hu --- .../devicetree/bindings/power/sifive,tmc.yaml | 58 ++++++++++++++++++= ++++ 1 file changed, 58 insertions(+) diff --git a/Documentation/devicetree/bindings/power/sifive,tmc.yaml b/Docu= mentation/devicetree/bindings/power/sifive,tmc.yaml new file mode 100644 index 000000000000..4ab2b94785f4 --- /dev/null +++ b/Documentation/devicetree/bindings/power/sifive,tmc.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/sifive,tmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive Domain Management Controller + +maintainers: + - Cyan Yang + - Nick Hu + - Samuel Holland + +description: | + SiFive Domain Management Controllers includes the following components + - Tile Management Controller (TMC) + - Cluster Management Controller (CMC) + - Subsystem Management Controller (SMC) + These controllers manage both the clock and power domains of the + associated components. They support the SiFive Quiet Interface Protocol + (SQIP) starting from Version 1. The control method differs from Version + 0, making them incompatible. + +allOf: + - $ref: power-domain.yaml# + +properties: + compatible: + oneOf: + - items: + - {} # Leave a empty for future SoC specific compatible string + - const: sifive,cmc2 + - items: + - {} # Leave a empty for future SoC specific compatible string + - const: sifive,smc0 + - items: + - {} # Leave a empty for future SoC specific compatible string + - const: sifive,smc1 + - items: + - {} # Leave a empty for future SoC specific compatible string + - const: sifive,tmc0 + - items: + - {} # Leave a empty for future SoC specific compatible string + - const: sifive,tmc1 + + reg: + maxItems: 1 + + "#power-domain-cells": + const: 0 + +required: + - compatible + - reg + +additionalProperties: false + +# The example will be added once the SoCs are ready --=20 2.43.7 From nobody Sun Feb 8 18:14:15 2026 Received: from mail-dy1-f175.google.com (mail-dy1-f175.google.com [74.125.82.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0E7836A02E for ; Thu, 8 Jan 2026 08:58:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.82.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767862731; cv=none; b=ujDO2c4C3h+2HCgw34onUvhHXEXIbfCWvwZG6vR99hJqMkVgrXlo7gbWpwkQeLFRgMkDaBjQSv7mVyEnxuBf/vu8iJyWDiFO+VO5Dl/xExKDuzdtqNUHPldtJTe1r5Fjm56xm4wX7EH/fEbWDneW3IJsD0g03dd02+B/HHYLtUg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767862731; c=relaxed/simple; bh=sIkymDyCEmbvxV9ZGQHY++Ov+nqP2mtyu2/hVCGij0w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LWjLtu9NF1RFoUkSdmOFLPYNoY1a9EsAiN3L+66ppoJys3NVxSWmgKVgeNvGGDk/7Rj3625vmk849CqZzVU8ab6Y+FlourbfQz10peE+udBZq6SAjhofSmOzxoguoncD6X3k11lOVLTqolZatPFFEhr5AtzgR66t87sv6XQGanI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=mQGHSmEn; arc=none smtp.client-ip=74.125.82.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="mQGHSmEn" Received: by mail-dy1-f175.google.com with SMTP id 5a478bee46e88-2b04a410f42so2219425eec.0 for ; Thu, 08 Jan 2026 00:58:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1767862721; x=1768467521; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+qYO/gxPTzZ1gsudLMySBCma6iHYfPz33KQqAWsXtts=; b=mQGHSmEnic+S0mS7xgLg+o+6wdYRXY+vt1KLwNdWi3ebWIs4RzQU8a7QTxZiGHLuyD ZjG0ZbcHq/2TyuIcxp09X8FymPW8d0sznQogZikC0C1/ugNg4aS1X256mgLR9imOr+Ht NVvx5LFLoDuLgxMCC5RwXsRJjH1ksxbXPIQegQxFL5/z7esv1jZGTOewvIcUMOaj2Dsr x7DNyg6gs1Fm6COvrfCisZWVcCKEFG/x8muLeWOOHOwMfqr7fFbcll98jgjP/36MZn62 EUyIeVhev/vI6uWH1Zz3i13dn3YOCUWf6vCyhUACXp+VqfP24lvi8LaF/RilD5pDYyXr eJpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767862721; x=1768467521; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=+qYO/gxPTzZ1gsudLMySBCma6iHYfPz33KQqAWsXtts=; b=qpvXrxo2kD13NZHbwsTmt0jSq81EnGZwI5cBgRvYl/ZW+nH1F4YpmqXV7WRR/AU1Qi 4qZLLCkKnuYXpBVN9AYUgXdaNe1PNyvt8oE+W4TKmcTNo8QxiCFNUwL3zxyC6KVVOXns QfAmxPEFVLn4hrbuPMUvw2VJbgKb87BP2CIdFPo2KPD2PQg2m2+oNY2h1ow1gLVJoQrK asg5RTHoIZlTP+MSBoG0iMTh23fQwZC9lEAjgEeeJ8Oh7hqlqklaUUUlxmEdkiwrgBQU MsaUc4zBFSdzGTNHjw16RNH4c8co4WNOWX5HT5kYQ5VscGv28Iw3E+JSFPNsALdOZnSJ pDQQ== X-Gm-Message-State: AOJu0Yy5H4Pgsmhz3p5b1kd2lgAUlbergBrPQHeAaUA6N7DpbrjSA7W2 y7L7aLfNXepg0pTmR83pFBpJ+wbIPCqOWK89L3qRFf/FMiGzjVRix8aCEQFqFYQEZ/Q= X-Gm-Gg: AY/fxX497LHtBFfD6v/NW1L1an9Wk0mwP1YCNai4b14t6rInep1+DAE5tv9W3aGxHok YAlzM1SJx/JGK9o9ozNP7nLTBwfDQlhLoqCAM1VrDDOvS0rkSpIhb/iIuoP5KIVmyXpTAUG02HX FWSwkO2VpLXagTy0IOwDK8qL6Bh+qa9YMu3y7TtB75Gi8Kl24btpBnCIHWGLSI2JhdFI0WfZc6S pFWFe2WWfBuYqcenYb1HUE/sDLSMZWQYYrzT5eB/HCaGLmU7U8OJz9keAQHXe2dLvafx/v3P9o6 BseBG0ai33aVBw7iZWPxG9YRbVtueVSw+WV+jkbr1Cc2KAHDdpxyBCgd3QfAAOLvieNU2aK2h34 ma1hXGvfDpaxDlkDU4UCNBxFwIf9kR4Vy5jBgNbWMJzncKM+Aaw/W011kZCmLTdrCDyBEZSu4ew VqW3F39eA7dkRSx5IjoW35ung= X-Google-Smtp-Source: AGHT+IE1ZYycZa8LfJgM/0T5ClhaC/Ln6YDrHSVxn+Bb2E0ZQUAhY5IK4YTUt16wFaSjFCweu0L/Dw== X-Received: by 2002:a05:693c:40db:b0:2ae:55f1:8201 with SMTP id 5a478bee46e88-2b17d23964bmr4070425eec.1.1767862721007; Thu, 08 Jan 2026 00:58:41 -0800 (PST) Received: from sw07.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b170675076sm8833634eec.2.2026.01.08.00.58.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jan 2026 00:58:40 -0800 (PST) From: Nick Hu Date: Thu, 08 Jan 2026 00:58:26 -0800 Subject: [PATCH v4 3/3] cpuidle: Add SiFive power provider driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260108-sifive-pd-drivers-v4-3-2a523d7d51a0@sifive.com> References: <20260108-sifive-pd-drivers-v4-0-2a523d7d51a0@sifive.com> In-Reply-To: <20260108-sifive-pd-drivers-v4-0-2a523d7d51a0@sifive.com> To: "Rafael J. Wysocki" , Daniel Lezcano , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Anup Patel , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Cyan Yang , Nick Hu Cc: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.3 The SiFive DMC is the power provider of the devices that inside the SiFive CPU power domains, which include Tile, Cluster and Core Complex power domains. Before the cpu entering the firmware-based idle state, each devices that inside the corresponding domain should be suspended properly. this driver will create the power provider and set the correct domain idle state. Signed-off-by: Nick Hu --- drivers/cpuidle/Kconfig.riscv | 12 +++ drivers/cpuidle/Makefile | 1 + drivers/cpuidle/cpuidle-sifive-dmc-domain.c | 124 ++++++++++++++++++++++++= ++++ 3 files changed, 137 insertions(+) diff --git a/drivers/cpuidle/Kconfig.riscv b/drivers/cpuidle/Kconfig.riscv index b813018ce401..2fe0912f8027 100644 --- a/drivers/cpuidle/Kconfig.riscv +++ b/drivers/cpuidle/Kconfig.riscv @@ -22,3 +22,15 @@ config RISCV_SBI_CPUIDLE_DOMAIN Select this option to enable RISC-V SBI firmware based CPU idle driver to use PM domains, which is needed to support the hierarchical DT based layout of the idle state. + +config SIFIVE_DMC_CPUIDLE_DOMAIN + bool "SiFive DMC CPU idle Domain" + depends on ARCH_SIFIVE + depends on RISCV_SBI_CPUIDLE + depends on PM_GENERIC_DOMAINS_OF + select DT_IDLE_GENPD + default y + help + Select this option to enable RISC-V SBI firmware based CPU idle + driver to use PM domains on SiFive Platforms, which is needed to + support the hierarchical DT based layout of the idle state. diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile index 82595849b75d..eead4c049414 100644 --- a/drivers/cpuidle/Makefile +++ b/drivers/cpuidle/Makefile @@ -43,3 +43,4 @@ obj-$(CONFIG_POWERNV_CPUIDLE) +=3D cpuidle-powernv.o # RISC-V drivers obj-$(CONFIG_RISCV_SBI_CPUIDLE) +=3D cpuidle-riscv-sbi.o obj-$(CONFIG_RISCV_SBI_CPUIDLE_DOMAIN) +=3D cpuidle-riscv-sbi-domain.o +obj-$(CONFIG_SIFIVE_DMC_CPUIDLE_DOMAIN) +=3D cpuidle-sifive-dmc-domain.o diff --git a/drivers/cpuidle/cpuidle-sifive-dmc-domain.c b/drivers/cpuidle/= cpuidle-sifive-dmc-domain.c new file mode 100644 index 000000000000..5174bc525a13 --- /dev/null +++ b/drivers/cpuidle/cpuidle-sifive-dmc-domain.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * SiFive CPUIDLE DMC driver + */ + +#define pr_fmt(fmt) "sifive_dmc_cpuidle_domain: " fmt + +#include +#include +#include +#include + +#include "cpuidle-riscv-sbi.h" +#include "dt_idle_genpd.h" + +static bool use_osi =3D true; + +static int sifive_cpuidle_dmc_power_off(struct generic_pm_domain *pd) +{ + struct genpd_power_state *state =3D &pd->states[pd->state_idx]; + u32 *pd_state; + + if (!state->data) + return 0; + + /* OSI mode is enabled, set the corresponding domain state. */ + pd_state =3D state->data; + sbi_set_domain_state(*pd_state); + + return 0; +} + +static int sifive_dmc_probe(struct platform_device *pdev) +{ + struct device_node *np =3D pdev->dev.of_node; + struct of_phandle_args child, parent; + struct device *dev =3D &pdev->dev; + struct generic_pm_domain *pd; + int ret =3D -ENOMEM; + + pd =3D dt_idle_pd_alloc(np, sbi_dt_parse_state_node); + if (!pd) + goto out; + + pd->flags |=3D GENPD_FLAG_IRQ_SAFE | GENPD_FLAG_CPU_DOMAIN; + if (use_osi) + pd->power_off =3D sifive_cpuidle_dmc_power_off; + else + pd->flags |=3D GENPD_FLAG_ALWAYS_ON; + + ret =3D pm_genpd_init(pd, &pm_domain_cpu_gov, false); + if (ret) + goto free_pd; + + ret =3D of_genpd_add_provider_simple(np, pd); + if (ret) + goto remove_pd; + + if (!of_parse_phandle_with_args(np, "power-domains", "#power-domain-cells= ", 0, &parent)) { + child.np =3D np; + child.args_count =3D 0; + + ret =3D of_genpd_add_subdomain(&parent, &child); + of_node_put(parent.np); + if (ret) { + pr_err("%pOF failed to add subdomain: %pOF\n", parent.np, child.np); + goto remove_pd; + } + } + + pm_runtime_enable(dev); + pr_info("init PM domain %s\n", dev_name(dev)); + return 0; + +remove_pd: + pm_genpd_remove(pd); +free_pd: + dt_idle_pd_free(pd); +out: + pr_err("failed to init PM domain ret=3D%d %pOF\n", ret, np); + return ret; +} + +static const struct of_device_id sifive_dmc_of_match[] =3D { + { .compatible =3D "sifive,tmc1", }, + { .compatible =3D "sifive,tmc0", }, + { .compatible =3D "sifive,smc1", }, + { .compatible =3D "sifive,smc0", }, + { .compatible =3D "sifive,cmc2", }, + {} +}; + +static struct platform_driver sifive_dmc_driver =3D { + .probe =3D sifive_dmc_probe, + .driver =3D { + .name =3D "sifive_dmc", + .of_match_table =3D sifive_dmc_of_match, + .suppress_bind_attrs =3D true, + }, +}; + +static int __init sifive_dmc_domain_init(void) +{ + int cpu; + + /* Detect OSI support based on CPU DT nodes */ + for_each_possible_cpu(cpu) { + struct device_node *np __free(device_node) =3D of_cpu_device_node_get(cp= u); + if (np && + of_property_present(np, "power-domains") && + of_property_present(np, "power-domain-names")) { + continue; + } else { + use_osi =3D false; + break; + } + } + + sbi_set_osi_mode(use_osi); + + /* Only probe the DMCs when OSI supported */ + return platform_driver_register(&sifive_dmc_driver); +} +core_initcall(sifive_dmc_domain_init); --=20 2.43.7