From nobody Sun Feb 8 18:18:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D474D4A1E15; Thu, 8 Jan 2026 12:15:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767874516; cv=none; b=OZIpJ4KyCWO/zQAOdoaKXkL50kVlLsBYnwrHSjqENLQ4eqZeUogFqCcfOK6XN/sOshPU7cfqgEye5llNsSkWvDHwSQtlVLv+w3EoiJRUz8uyCGe4P4btdCKdOkejUh376/enNqLEpxZ99EsSEpZmYylziHGI+A6COw/qxFNRC5A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767874516; c=relaxed/simple; bh=TEG6cwJeJtdzv5Tb7hQRvbWoPURes4QOAf+K6qmOJAI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Hvx08t7EWlqryHp3ojWpJUVuGK9froPiIxKqNphF2LzOu3jk332aq/i7Ls5Td3SXjZdNbiQotmudyVkvBJr53t1asNX+jGGFBA2DIJVqYlc0Pg7JUkmiNAMEP20ZR6ETYnbFxhqvVM9AYTRO7rCvWSu0rRRiFffD8tLxaQ2kUWw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eEIkfYGW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eEIkfYGW" Received: by smtp.kernel.org (Postfix) with ESMTPS id 32F59C16AAE; Thu, 8 Jan 2026 12:15:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1767874515; bh=TEG6cwJeJtdzv5Tb7hQRvbWoPURes4QOAf+K6qmOJAI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=eEIkfYGWXBU6vQTa3uJiX6IPXaDlxbGUJV+lCflbZwXZFKVj3UmS21mOf2TakKH9A jfAPWG7ud5D8qS9/UiMNyu8TOYqGAy4/F+dyCr7w62W+HcEioQXZL4AlgI0D2aM5ZQ U7m++Xeu+u26l0jM+sq4OS5M52lOH51AOd4u/1QG5OeQdr9XKTHwvh7DT1gszrp8p2 SHhs98gVT8SRKCHWMgx3Mxn4lIA4Sr+Hpok/kNme57Wqmn8ZjdMxVvv7D47K5Z7Ch+ kw67U76H0wzuSJnkKosko9+Jy8tI+B+HHIaqy4NBvXXuNpq8VsulzCuSOSazOhMn77 Sn1JwVXlmXUQA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22872D185EA; Thu, 8 Jan 2026 12:15:15 +0000 (UTC) From: Rodrigo Alencar via B4 Relay Date: Thu, 08 Jan 2026 12:14:50 +0000 Subject: [PATCH v3 1/6] dt-bindings: iio: frequency: add adf41513 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260108-adf41513-iio-driver-v3-1-23d1371aef48@analog.com> References: <20260108-adf41513-iio-driver-v3-0-23d1371aef48@analog.com> In-Reply-To: <20260108-adf41513-iio-driver-v3-0-23d1371aef48@analog.com> To: linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org Cc: Jonathan Cameron , David Lechner , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767874513; l=9816; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=RkYFwfwpIbWObutljU10GCF9MkgVk7HmsBR75v8hyUQ=; b=5pbNfMuSI+NJCrFb/lLf0L+Dn8gHdUtsVfEtVnwwrDPyR4BGsyqYmy4BRiy892Ds+Ay3wxpXb APP+EQ45dkxDOH9pcV3kpdmGbN1gkUrg1R75fgvZJezK+xz7XX44jUK X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar DT-bindings for ADF41513, an ultralow noise PLL frequency synthesizer that can be used to implement local oscillators (LOs) as high as 26.5 GHz. Most properties are based upon an existing PLL device properties (e.g. ADF4350). Signed-off-by: Rodrigo Alencar Reviewed-by: Krzysztof Kozlowski --- .../bindings/iio/frequency/adi,adf41513.yaml | 234 +++++++++++++++++= ++++ MAINTAINERS | 7 + 2 files changed, 241 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/frequency/adi,adf41513.y= aml b/Documentation/devicetree/bindings/iio/frequency/adi,adf41513.yaml new file mode 100644 index 000000000000..d3ae99f95f30 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/frequency/adi,adf41513.yaml @@ -0,0 +1,234 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/frequency/adi,adf41513.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADF41513 PLL Frequency Synthesizer + +maintainers: + - Rodrigo Alencar + +description: + The ADF41513 is an ultralow noise frequency synthesizer that can be used= to + implement local oscillators (LOs) as high as 26.5 GHz in the upconversio= n and + downconversion sections of wireless receivers and transmitters. The ADF4= 1510 + supports frequencies up to 10 GHz. + + https://www.analog.com/en/products/adf41510.html + https://www.analog.com/en/products/adf41513.html + +$ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - adi,adf41510 + - adi,adf41513 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 25000000 + + clocks: + maxItems: 1 + description: Clock that provides the reference input frequency. + + avdd1-supply: + description: PFD and Up and Down Digital Driver Power Supply (3.3 V) + + avdd2-supply: + description: RF Buffer and Prescaler Power Supply (3.3 V) + + avdd3-supply: + description: N Divider Power Supply (3.3 V) + + avdd4-supply: + description: R Divider and Lock Detector Power Supply (3.3 V) + + avdd5-supply: + description: Sigma-Delta Modulator and SPI Power Supply (3.3 V) + + vp-supply: + description: Charge Pump Power Supply (3.3 V) + + enable-gpios: + description: + GPIO that controls the chip enable pin. A logic low on this pin + powers down the device and puts the charge pump output into + three-state mode. + maxItems: 1 + + lock-detect-gpios: + description: + GPIO for lock detect functionality. When configured for digital lock + detect, this pin will output a logic high when the PLL is locked. + maxItems: 1 + + adi,power-up-frequency-mhz: + minimum: 1000 + maximum: 26500 + default: 10000 + description: + The PLL tunes to this frequency during the initialization sequence. + This property should be set to a frequency supported by the loop fil= ter + and VCO used in the design. Range is 1 GHz to 26.5 GHz for ADF41513, + and 1 GHz to 10 GHz for ADF41510. + + adi,reference-div-factor: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 32 + default: 1 + description: + Value for the reference division factor (R Counter). The driver will + increment R Counter as needed to achieve a PFD frequency within the + allowed range. High R counter values will reduce the PFD frequency, = which + lowers the frequency resolution, and affects phase noise performance. + As it affects the PFD frequency, this value depends on the loop filt= er + design. + + adi,reference-doubler-enable: + description: + Enables the reference doubler when deriving the PFD frequency. + The maximum reference frequency when the doubler is enabled is 225 M= Hz. + As it affects the PFD frequency, this value depends on the loop filt= er + design. + type: boolean + + adi,reference-div2-enable: + description: + Enables the reference divide-by-2 function when deriving the PFD + frequency. As it affects the PFD frequency, this value depends on the + loop filter design. + type: boolean + + adi,charge-pump-resistor-ohms: + minimum: 1800 + maximum: 10000 + default: 2700 + description: + External charge pump resistor (R_SET) value in ohms. This sets the m= aximum + charge pump current along with the charge pump current setting. + + adi,charge-pump-current-microamp: + description: + Charge pump current (I_CP) in microamps. The value will be rounded t= o the + nearest supported value. Range of acceptable values depends on the + charge pump resistor value, such that 810 mV <=3D I_CP * R_SET <=3D = 12960 mV. + This value depends on the loop filter and the VCO design. + + adi,logic-level-1v8-enable: + description: + Set MUXOUT and DLD logic levels to 1.8V. Default is 3.3V. + type: boolean + + adi,phase-detector-polarity-positive-enable: + description: + Set phase detector polarity to positive. Default is negative. + Use positive polarity with non-inverting loop filter and VCO with + positive tuning slope, or with inverting loop filter and VCO with + negative tuning slope. + type: boolean + + adi,lock-detector-count: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 64 + description: + Sets the value for Lock Detector count of the PLL, which determines = the + number of consecutive phase detector cycles that must be within the = lock + detector window before lock is declared. Lower values increase the l= ock + detection sensitivity, while higher values provides a more stable lo= ck + detection. Applications that consume the lock detect signal may requ= ire + different settings based on system requirements. + enum: [2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192] + + adi,phase-resync-period-ns: + default: 0 + description: + When this value is non-zero, enable phase resync functionality, which + produces a consistent output phase offset with respect to the input + reference. The value specifies the resync period in nanoseconds, used + to configure clock dividers with respect to the PFD frequency. This = value + should be set to a value that is at least as long as the worst case = lock + time, i.e., it depends mostly on the loop filter design. + + adi,le-sync-enable: + description: + Synchronizes Load Enable (LE) transitions with the reference signal = to + avoid asynchronous glitches in the output. This is recommended when = using + the PLL as a frequency synthesizer, where the reference signal will = always + be present while the device is being configured. When using the PLL = as a + frequency tracker, where the reference signal may be absent, LE sync + should be left disabled. + type: boolean + +required: + - compatible + - reg + - clocks + - avdd1-supply + - avdd2-supply + - avdd3-supply + - avdd4-supply + - avdd5-supply + - vp-supply + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + pll@0 { + compatible =3D "adi,adf41513"; + reg =3D <0>; + spi-max-frequency =3D <10000000>; + clocks =3D <&ref_clk>; + avdd1-supply =3D <&vdd_3v3>; + avdd2-supply =3D <&vdd_3v3>; + avdd3-supply =3D <&vdd_3v3>; + avdd4-supply =3D <&vdd_3v3>; + avdd5-supply =3D <&vdd_3v3>; + vp-supply =3D <&vdd_3v3>; + + adi,power-up-frequency-mhz =3D <12000>; + adi,charge-pump-current-microamp =3D <2400>; + adi,phase-detector-polarity-positive-enable; + }; + }; + - | + #include + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + pll@0 { + compatible =3D "adi,adf41513"; + reg =3D <0>; + spi-max-frequency =3D <25000000>; + clocks =3D <&ref_clk>; + avdd1-supply =3D <&avdd1_3v3>; + avdd2-supply =3D <&avdd2_3v3>; + avdd3-supply =3D <&avdd3_3v3>; + avdd4-supply =3D <&avdd4_3v3>; + avdd5-supply =3D <&avdd5_3v3>; + vp-supply =3D <&vp_3v3>; + enable-gpios =3D <&gpio0 10 GPIO_ACTIVE_HIGH>; + lock-detect-gpios =3D <&gpio0 11 GPIO_ACTIVE_HIGH>; + + adi,power-up-frequency-mhz =3D <15500>; + adi,charge-pump-current-microamp =3D <3600>; + adi,charge-pump-resistor-ohms =3D <2700>; + adi,reference-doubler-enable; + adi,lock-detector-count =3D <64>; + adi,phase-resync-period-ns =3D <0>; + adi,phase-detector-polarity-positive-enable; + adi,le-sync-enable; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 2e8825b8ccef..64906c26142d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1610,6 +1610,13 @@ W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/amplifiers/adi,ada4250.yaml F: drivers/iio/amplifiers/ada4250.c =20 +ANALOG DEVICES INC ADF41513 DRIVER +M: Rodrigo Alencar +L: linux-iio@vger.kernel.org +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/frequency/adi,adf41513.yaml + ANALOG DEVICES INC ADF4377 DRIVER M: Antoniu Miclaus L: linux-iio@vger.kernel.org --=20 2.43.0 From nobody Sun Feb 8 18:18:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 024F648707D; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260108-adf41513-iio-driver-v3-2-23d1371aef48@analog.com> References: <20260108-adf41513-iio-driver-v3-0-23d1371aef48@analog.com> In-Reply-To: <20260108-adf41513-iio-driver-v3-0-23d1371aef48@analog.com> To: linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org Cc: Jonathan Cameron , David Lechner , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767874513; l=40768; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=ps2qaIEYyofi9SxbInG+k7Bq3PZzctDzrgjlL1HZTu8=; b=zAfQ4yGkVVt0XlG67xilFDu8ATXckV7Ax0FTQtsOR4xIAvZ+OcjOq6dTdNMiB9eokT27eZs7J 5I9AnEMeITmDgJOUVAdD7v25zSeNJMX9mkC6mxUowAO+O7Fu29L3Q9b X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar The driver is based on existing PLL drivers in the IIO subsystem and implements the following key features: - Integer-N and fractional-N (fixed/variable modulus) synthesis modes - High-resolution frequency calculations using microhertz (=C2=B5Hz) precis= ion to handle sub-Hz resolution across multi-GHz frequency ranges - IIO debugfs interface for direct register access - FW property parsing from devicetree including charge pump settings, reference path configuration and muxout options - Power management support with suspend/resume callbacks - Lock detect GPIO monitoring The driver uses 64-bit microhertz values throughout PLL calculations to maintain precision when working with frequencies that exceed 32-bit Hz representation while requiring fractional Hz resolution. Signed-off-by: Rodrigo Alencar --- MAINTAINERS | 1 + drivers/iio/frequency/Kconfig | 10 + drivers/iio/frequency/Makefile | 1 + drivers/iio/frequency/adf41513.c | 1170 ++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 1182 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 64906c26142d..a5c5f76f47c6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1616,6 +1616,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/frequency/adi,adf41513.yaml +F: drivers/iio/frequency/adf41513.c =20 ANALOG DEVICES INC ADF4377 DRIVER M: Antoniu Miclaus diff --git a/drivers/iio/frequency/Kconfig b/drivers/iio/frequency/Kconfig index 583cbdf4e8cd..90c6304c4bcd 100644 --- a/drivers/iio/frequency/Kconfig +++ b/drivers/iio/frequency/Kconfig @@ -29,6 +29,16 @@ endmenu =20 menu "Phase-Locked Loop (PLL) frequency synthesizers" =20 +config ADF41513 + tristate "Analog Devices ADF41513 PLL Frequency Synthesizer" + depends on SPI + help + Say yes here to build support for Analog Devices ADF41513 + 26.5 GHz Integer-N/Fractional-N PLL Frequency Synthesizer. + + To compile this driver as a module, choose M here: the + module will be called adf41513. + config ADF4350 tristate "Analog Devices ADF4350/ADF4351 Wideband Synthesizers" depends on SPI diff --git a/drivers/iio/frequency/Makefile b/drivers/iio/frequency/Makefile index 70d0e0b70e80..53b4d01414d8 100644 --- a/drivers/iio/frequency/Makefile +++ b/drivers/iio/frequency/Makefile @@ -5,6 +5,7 @@ =20 # When adding new entries keep the list in alphabetical order obj-$(CONFIG_AD9523) +=3D ad9523.o +obj-$(CONFIG_ADF41513) +=3D adf41513.o obj-$(CONFIG_ADF4350) +=3D adf4350.o obj-$(CONFIG_ADF4371) +=3D adf4371.o obj-$(CONFIG_ADF4377) +=3D adf4377.o diff --git a/drivers/iio/frequency/adf41513.c b/drivers/iio/frequency/adf41= 513.c new file mode 100644 index 000000000000..69dcbbc1f393 --- /dev/null +++ b/drivers/iio/frequency/adf41513.c @@ -0,0 +1,1170 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * ADF41513 SPI PLL Frequency Synthesizer driver + * + * Copyright 2026 Analog Devices Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Registers */ +#define ADF41513_REG0 0 +#define ADF41513_REG1 1 +#define ADF41513_REG2 2 +#define ADF41513_REG3 3 +#define ADF41513_REG4 4 +#define ADF41513_REG5 5 +#define ADF41513_REG6 6 +#define ADF41513_REG7 7 +#define ADF41513_REG8 8 +#define ADF41513_REG9 9 +#define ADF41513_REG10 10 +#define ADF41513_REG11 11 +#define ADF41513_REG12 12 +#define ADF41513_REG13 13 +#define ADF41513_REG_NUM 14 + +#define ADF41513_SYNC_REG0 BIT(ADF41513_REG0) +#define ADF41513_SYNC_REG1 BIT(ADF41513_REG1) +#define ADF41513_SYNC_REG2 BIT(ADF41513_REG2) +#define ADF41513_SYNC_REG3 BIT(ADF41513_REG3) +#define ADF41513_SYNC_REG4 BIT(ADF41513_REG4) +#define ADF41513_SYNC_REG5 BIT(ADF41513_REG5) +#define ADF41513_SYNC_REG6 BIT(ADF41513_REG6) +#define ADF41513_SYNC_REG7 BIT(ADF41513_REG7) +#define ADF41513_SYNC_REG9 BIT(ADF41513_REG9) +#define ADF41513_SYNC_REG11 BIT(ADF41513_REG11) +#define ADF41513_SYNC_REG12 BIT(ADF41513_REG12) +#define ADF41513_SYNC_REG13 BIT(ADF41513_REG13) +#define ADF41513_SYNC_DIFF 0 +#define ADF41513_SYNC_ALL GENMASK(ADF41513_REG13, ADF41513_REG0) + +/* REG0 Bit Definitions */ +#define ADF41513_REG0_CTRL_BITS_MSK GENMASK(3, 0) +#define ADF41513_REG0_INT_MSK GENMASK(19, 4) +#define ADF41513_REG0_VAR_MOD_MSK BIT(28) + +/* REG1 Bit Definitions */ +#define ADF41513_REG1_FRAC1_MSK GENMASK(28, 4) +#define ADF41513_REG1_DITHER2_MSK BIT(31) + +/* REG2 Bit Definitions */ +#define ADF41513_REG2_PHASE_VAL_MSK GENMASK(15, 4) +#define ADF41513_REG2_PHASE_ADJ_MSK BIT(31) + +/* REG3 Bit Definitions */ +#define ADF41513_REG3_FRAC2_MSK GENMASK(27, 4) + +/* REG4 Bit Definitions */ +#define ADF41513_REG4_MOD2_MSK GENMASK(27, 4) + +/* REG5 Bit Definitions */ +#define ADF41513_REG5_CLK1_DIV_MSK GENMASK(15, 4) +#define ADF41513_REG5_R_CNT_MSK GENMASK(20, 16) +#define ADF41513_REG5_REF_DOUBLER_MSK BIT(21) +#define ADF41513_REG5_RDIV2_MSK BIT(22) +#define ADF41513_REG5_PRESCALER_MSK BIT(23) +#define ADF41513_REG5_LSB_P1_MSK BIT(24) +#define ADF41513_REG5_CP_CURRENT_MSK GENMASK(28, 25) +#define ADF41513_REG5_DLD_MODES_MSK GENMASK(31, 30) + +/* REG6 Bit Definitions */ +#define ADF41513_REG6_COUNTER_RESET_MSK BIT(4) +#define ADF41513_REG6_CP_TRISTATE_MSK BIT(5) +#define ADF41513_REG6_POWER_DOWN_MSK BIT(6) +#define ADF41513_REG6_PD_POLARITY_MSK BIT(7) +#define ADF41513_REG6_LDP_MSK GENMASK(9, 8) +#define ADF41513_REG6_CP_TRISTATE_PD_ON_MSK BIT(16) +#define ADF41513_REG6_SD_RESET_MSK BIT(17) +#define ADF41513_REG6_LOL_ENABLE_MSK BIT(18) +#define ADF41513_REG6_ABP_MSK BIT(19) +#define ADF41513_REG6_INT_MODE_MSK BIT(20) +#define ADF41513_REG6_BLEED_ENABLE_MSK BIT(22) +#define ADF41513_REG6_BLEED_POLARITY_MSK BIT(23) +#define ADF41513_REG6_BLEED_CURRENT_MSK GENMASK(31, 24) + +/* REG7 Bit Definitions */ +#define ADF41513_REG7_CLK2_DIV_MSK GENMASK(17, 6) +#define ADF41513_REG7_CLK_DIV_MODE_MSK GENMASK(19, 18) +#define ADF41513_REG7_PS_BIAS_MSK GENMASK(21, 20) +#define ADF41513_REG7_N_DELAY_MSK GENMASK(23, 22) +#define ADF41513_REG7_LD_CLK_SEL_MSK BIT(26) +#define ADF41513_REG7_LD_COUNT_MSK GENMASK(29, 27) + +/* REG9 Bit Definitions */ +#define ADF41513_REG9_LD_BIAS_MSK GENMASK(31, 30) + +/* REG11 Bit Definitions */ +#define ADF41513_REG11_POWER_DOWN_SEL_MSK BIT(31) + +/* REG12 Bit Definitions */ +#define ADF41513_REG12_READBACK_SEL_MSK GENMASK(19, 14) +#define ADF41513_REG12_LE_SELECT_MSK BIT(20) +#define ADF41513_REG12_MASTER_RESET_MSK BIT(22) +#define ADF41513_REG12_LOGIC_LEVEL_MSK BIT(27) +#define ADF41513_REG12_MUXOUT_MSK GENMASK(31, 28) + +/* MUXOUT Selection */ +#define ADF41513_MUXOUT_TRISTATE 0x0 +#define ADF41513_MUXOUT_DVDD 0x1 +#define ADF41513_MUXOUT_DGND 0x2 +#define ADF41513_MUXOUT_R_DIV 0x3 +#define ADF41513_MUXOUT_N_DIV 0x4 +#define ADF41513_MUXOUT_DIG_LD 0x6 +#define ADF41513_MUXOUT_SDO 0x7 +#define ADF41513_MUXOUT_READBACK 0x8 +#define ADF41513_MUXOUT_CLK1_DIV 0xA +#define ADF41513_MUXOUT_R_DIV2 0xD +#define ADF41513_MUXOUT_N_DIV2 0xE + +/* DLD Mode Selection */ +#define ADF41513_DLD_TRISTATE 0x0 +#define ADF41513_DLD_DIG_LD 0x1 +#define ADF41513_DLD_LOW 0x2 +#define ADF41513_DLD_HIGH 0x3 + +/* Prescaler Selection */ +#define ADF41513_PRESCALER_4_5 0 +#define ADF41513_PRESCALER_8_9 1 +#define ADF41513_PRESCALER_AUTO 2 + +/* Specifications */ +#define ADF41510_MAX_RF_FREQ (10000ULL * HZ_PER_MHZ) +#define ADF41513_MIN_RF_FREQ (1000ULL * HZ_PER_MHZ) +#define ADF41513_MAX_RF_FREQ (26500ULL * HZ_PER_MHZ) + +#define ADF41513_MIN_REF_FREQ (10U * HZ_PER_MHZ) +#define ADF41513_MAX_REF_FREQ (800U * HZ_PER_MHZ) +#define ADF41513_MAX_REF_FREQ_DOUBLER (225U * HZ_PER_MHZ) + +#define ADF41513_MAX_PFD_FREQ_INT_N_UHZ (250ULL * HZ_PER_MHZ * MICROHZ_PE= R_HZ) +#define ADF41513_MAX_PFD_FREQ_FRAC_N_UHZ (125ULL * HZ_PER_MHZ * MICROHZ_PE= R_HZ) +#define ADF41513_MAX_FREQ_RESOLUTION_UHZ (100ULL * HZ_PER_KHZ * MICROHZ_PE= R_HZ) + +#define ADF41513_MIN_INT_4_5 20 +#define ADF41513_MAX_INT_4_5 511 +#define ADF41513_MIN_INT_8_9 64 +#define ADF41513_MAX_INT_8_9 1023 + +#define ADF41513_MIN_INT_FRAC_4_5 23 +#define ADF41513_MIN_INT_FRAC_8_9 75 + +#define ADF41513_MIN_R_CNT 1 +#define ADF41513_MAX_R_CNT 32 + +#define ADF41513_MIN_R_SET 1800 +#define ADF41513_DEFAULT_R_SET 2700 +#define ADF41513_MAX_R_SET 10000 + +#define ADF41513_MIN_CP_VOLTAGE_mV 810 +#define ADF41513_DEFAULT_CP_VOLTAGE_mV 6480 +#define ADF41513_MAX_CP_VOLTAGE_mV 12960 + +#define ADF41513_MAX_CLK_DIVIDER 4095 +#define ADF41513_LD_COUNT_FAST_MIN 2 +#define ADF41513_LD_COUNT_FAST_LIMIT 64 +#define ADF41513_LD_COUNT_MIN 64 +#define ADF41513_LD_COUNT_MAX 8192 + +#define ADF41513_FIXED_MODULUS BIT(25) +#define ADF41513_MAX_MOD2 (BIT(24) - 1) +#define ADF41513_MAX_PHASE_VAL (BIT(12) - 1) + +#define ADF41513_HZ_DECIMAL_PRECISION 6 +#define ADF41513_MAX_PHASE_MICRORAD 6283185UL +#define ADF41513_PS_BIAS_INIT 0x2 + +enum { + ADF41513_FREQ, + ADF41513_POWER_DOWN, + ADF41513_FREQ_RESOLUTION, +}; + +enum adf41513_pll_mode { + ADF41513_MODE_INVALID, + ADF41513_MODE_INTEGER_N, + ADF41513_MODE_FIXED_MODULUS, + ADF41513_MODE_VARIABLE_MODULUS, +}; + +struct adf41513_chip_info { + bool has_prescaler_8_9; + u64 max_rf_freq_hz; +}; + +struct adf41513_data { + u64 power_up_frequency_hz; + u64 freq_resolution_uhz; + u32 charge_pump_voltage_mv; + u32 lock_detect_count; + + u8 ref_div_factor; + bool ref_doubler_en; + bool ref_div2_en; + bool phase_detector_polarity; + + bool logic_lvl_1v8_en; +}; + +struct adf41513_pll_settings { + enum adf41513_pll_mode mode; + + /* reference path parameters */ + u8 r_counter; + u8 ref_doubler; + u8 ref_div2; + u8 prescaler; + + /* frequency parameters */ + u64 target_frequency_uhz; + u64 actual_frequency_uhz; + u64 pfd_frequency_uhz; + + /* pll parameters */ + u16 int_value; + u32 frac1; + u32 frac2; + u32 mod2; +}; + +struct adf41513_state { + const struct adf41513_chip_info *chip_info; + struct spi_device *spi; + struct gpio_desc *lock_detect; + struct gpio_desc *chip_enable; + struct clk *ref_clk; + u32 ref_freq_hz; + + /* + * Lock for accessing device registers. Some operations require + * multiple consecutive R/W operations, during which the device + * shouldn't be interrupted. The buffers are also shared across + * all operations so need to be protected on stand alone reads and + * writes. + */ + struct mutex lock; + + /* Cached register values */ + u32 regs[ADF41513_REG_NUM]; + u32 regs_hw[ADF41513_REG_NUM]; + + struct adf41513_data data; + struct adf41513_pll_settings settings; + + /* + * DMA (thus cache coherency maintenance) may require that + * transfer buffers live in their own cache lines. + */ + __be32 buf __aligned(IIO_DMA_MINALIGN); +}; + +static const char * const adf41513_power_supplies[] =3D { + "avdd1", "avdd2", "avdd3", "avdd4", "avdd5", "vp" +}; + +/** + * adf41513_parse_uhz() - parse fixed point frequency string into microher= tz + * @str: input string with frequency in Hz (supports 6 decimal places) + * @freq_uhz: output frequency in microhertz + * + * This driver supports sub-Hz frequency resolution with frequency ranges + * up to several GHz (> 2^32). To achieve this, frequency calculations are + * done in microhertz using u64 variables. iio core parse helpers only sup= port + * 64-bit integers or 32-bit integers plus fractional part. Here, we need + * 64-bit integer plus fractional part (6 decimal places) to achieve lower + * frequency resolutions. + * See iio_write_channel_info and __iio_str_to_fixpoint in + * drivers/iio/industrialio-core.c + * + * Returns: + * 0 on success, -EINVAL on parsing error. + */ +static int adf41513_parse_uhz(const char *str, u64 *freq_uhz) +{ + u64 uhz =3D 0; + int f_count =3D ADF41513_HZ_DECIMAL_PRECISION; + bool frac_part =3D false; + + if (str[0] =3D=3D '+') + str++; + + while (*str && f_count > 0) { + if ('0' <=3D *str && *str <=3D '9') { + uhz =3D uhz * 10 + *str - '0'; + if (frac_part) + f_count--; + } else if (*str =3D=3D '\n') { + if (*(str + 1) =3D=3D '\0') + break; + return -EINVAL; + } else if (*str =3D=3D '.' && !frac_part) { + frac_part =3D true; + } else { + return -EINVAL; + } + str++; + } + + for (; f_count > 0; f_count--) + uhz *=3D 10; + + *freq_uhz =3D uhz; + + return 0; +} + +static int adf41513_uhz_to_str(u64 freq_uhz, char *buf) +{ + u32 frac_part; + u64 int_part =3D div_u64_rem(freq_uhz, MICROHZ_PER_HZ, &frac_part); + + return sysfs_emit(buf, "%llu.%06u\n", int_part, frac_part); +} + +static int adf41513_sync_config(struct adf41513_state *st, u16 sync_mask) +{ + int ret; + int i; + + /* write registers in reverse order (R13 to R0)*/ + for (i =3D ADF41513_REG13; i >=3D ADF41513_REG0; i--) { + if (st->regs_hw[i] =3D=3D st->regs[i] && !(sync_mask & BIT(i))) + continue; + + st->buf =3D cpu_to_be32(st->regs[i] | i); + ret =3D spi_write(st->spi, &st->buf, sizeof(st->buf)); + if (ret < 0) + return ret; + st->regs_hw[i] =3D st->regs[i]; + dev_dbg(&st->spi->dev, "REG%d <=3D 0x%08X\n", i, st->regs[i] | i); + } + + return 0; +} + +static u64 adf41513_pll_get_rate(struct adf41513_state *st) +{ + struct adf41513_pll_settings *cfg =3D &st->settings; + + if (cfg->mode !=3D ADF41513_MODE_INVALID) + return cfg->actual_frequency_uhz; + + /* get pll settings from regs_hw */ + cfg->int_value =3D FIELD_GET(ADF41513_REG0_INT_MSK, st->regs_hw[ADF41513_= REG0]); + cfg->frac1 =3D FIELD_GET(ADF41513_REG1_FRAC1_MSK, st->regs_hw[ADF41513_RE= G1]); + cfg->frac2 =3D FIELD_GET(ADF41513_REG3_FRAC2_MSK, st->regs_hw[ADF41513_RE= G3]); + cfg->mod2 =3D FIELD_GET(ADF41513_REG4_MOD2_MSK, st->regs_hw[ADF41513_REG4= ]); + cfg->r_counter =3D FIELD_GET(ADF41513_REG5_R_CNT_MSK, st->regs_hw[ADF4151= 3_REG5]); + cfg->ref_doubler =3D FIELD_GET(ADF41513_REG5_REF_DOUBLER_MSK, st->regs_hw= [ADF41513_REG5]); + cfg->ref_div2 =3D FIELD_GET(ADF41513_REG5_RDIV2_MSK, st->regs_hw[ADF41513= _REG5]); + cfg->prescaler =3D FIELD_GET(ADF41513_REG5_PRESCALER_MSK, st->regs_hw[ADF= 41513_REG5]); + + /* calculate pfd frequency */ + cfg->pfd_frequency_uhz =3D (u64)st->ref_freq_hz * MICROHZ_PER_HZ; + if (cfg->ref_doubler) + cfg->pfd_frequency_uhz <<=3D 1; + if (cfg->ref_div2) + cfg->pfd_frequency_uhz >>=3D 1; + cfg->pfd_frequency_uhz =3D div_u64(cfg->pfd_frequency_uhz, + cfg->r_counter); + cfg->actual_frequency_uhz =3D (u64)cfg->int_value * cfg->pfd_frequency_uh= z; + + /* check if int mode is selected */ + if (FIELD_GET(ADF41513_REG6_INT_MODE_MSK, st->regs_hw[ADF41513_REG6])) { + cfg->mode =3D ADF41513_MODE_INTEGER_N; + } else { + cfg->actual_frequency_uhz +=3D mul_u64_u64_div_u64(cfg->frac1, + cfg->pfd_frequency_uhz, + ADF41513_FIXED_MODULUS); + + /* check if variable modulus is selected */ + if (FIELD_GET(ADF41513_REG0_VAR_MOD_MSK, st->regs_hw[ADF41513_REG0])) { + cfg->actual_frequency_uhz +=3D + mul_u64_u64_div_u64(cfg->frac2, + cfg->pfd_frequency_uhz, + ADF41513_FIXED_MODULUS * cfg->mod2); + + cfg->mode =3D ADF41513_MODE_VARIABLE_MODULUS; + } else { + /* LSB_P1 offset */ + if (!FIELD_GET(ADF41513_REG5_LSB_P1_MSK, st->regs_hw[ADF41513_REG5])) + cfg->actual_frequency_uhz +=3D + div_u64(cfg->pfd_frequency_uhz, + ADF41513_FIXED_MODULUS * 2); + cfg->mode =3D ADF41513_MODE_FIXED_MODULUS; + } + } + + cfg->target_frequency_uhz =3D cfg->actual_frequency_uhz; + + return cfg->actual_frequency_uhz; +} + +static int adf41513_calc_pfd_frequency(struct adf41513_state *st, + struct adf41513_pll_settings *result, + u64 fpfd_limit_uhz) +{ + result->ref_div2 =3D st->data.ref_div2_en ? 1 : 0; + result->ref_doubler =3D st->data.ref_doubler_en ? 1 : 0; + + if (st->data.ref_doubler_en && st->ref_freq_hz > ADF41513_MAX_REF_FREQ_DO= UBLER) { + result->ref_doubler =3D 0; + dev_warn(&st->spi->dev, "Disabling ref doubler due to high reference fre= quency\n"); + } + + result->r_counter =3D st->data.ref_div_factor - 1; + do { + result->r_counter++; + /* f_PFD =3D REF_IN =C3=97 ((1 + D)/(R =C3=97 (1 + T))) */ + result->pfd_frequency_uhz =3D (u64)st->ref_freq_hz * MICROHZ_PER_HZ; + if (result->ref_doubler) + result->pfd_frequency_uhz <<=3D 1; + if (result->ref_div2) + result->pfd_frequency_uhz >>=3D 1; + result->pfd_frequency_uhz =3D div_u64(result->pfd_frequency_uhz, + result->r_counter); + } while (result->pfd_frequency_uhz > fpfd_limit_uhz); + + if (result->r_counter > ADF41513_MAX_R_CNT) { + dev_err(&st->spi->dev, "Cannot optimize PFD frequency\n"); + return -ERANGE; + } + + return 0; +} + +static int adf41513_calc_integer_n(struct adf41513_state *st, + struct adf41513_pll_settings *result) +{ + u16 max_int =3D (st->chip_info->has_prescaler_8_9) ? + ADF41513_MAX_INT_8_9 : ADF41513_MAX_INT_4_5; + u64 freq_error_uhz; + u16 int_value =3D div64_u64_rem(result->target_frequency_uhz, result->pfd= _frequency_uhz, + &freq_error_uhz); + + /* check if freq error is within a tolerance of 1/2 resolution */ + if (freq_error_uhz > (result->pfd_frequency_uhz >> 1) && int_value < max_= int) { + int_value++; + freq_error_uhz =3D result->pfd_frequency_uhz - freq_error_uhz; + } + + if (freq_error_uhz > st->data.freq_resolution_uhz) + return -ERANGE; + + /* set prescaler */ + if (st->chip_info->has_prescaler_8_9 && int_value >=3D ADF41513_MIN_INT_8= _9 && + int_value <=3D ADF41513_MAX_INT_8_9) + result->prescaler =3D 1; + else if (int_value >=3D ADF41513_MIN_INT_4_5 && int_value <=3D ADF41513_M= AX_INT_4_5) + result->prescaler =3D 0; + else + return -ERANGE; + + result->actual_frequency_uhz =3D (u64)int_value * result->pfd_frequency_u= hz; + result->mode =3D ADF41513_MODE_INTEGER_N; + result->int_value =3D int_value; + result->frac1 =3D 0; + result->frac2 =3D 0; + result->mod2 =3D 0; + + return 0; +} + +static int adf41513_calc_fixed_mod(struct adf41513_state *st, + struct adf41513_pll_settings *result) +{ + u64 freq_error_uhz; + u64 resolution_uhz =3D div_u64(result->pfd_frequency_uhz, ADF41513_FIXED_= MODULUS); + u64 target_frequency_uhz =3D result->target_frequency_uhz; + u32 frac1; + u16 int_value; + bool lsb_p1_offset =3D !FIELD_GET(ADF41513_REG5_LSB_P1_MSK, st->regs_hw[A= DF41513_REG5]); + + /* LSB_P1 adds a frequency offset of f_pfd/2^26 */ + if (lsb_p1_offset) + target_frequency_uhz -=3D resolution_uhz >> 1; + + int_value =3D div64_u64_rem(target_frequency_uhz, result->pfd_frequency_u= hz, + &freq_error_uhz); + + if (st->chip_info->has_prescaler_8_9 && int_value >=3D ADF41513_MIN_INT_F= RAC_8_9 && + int_value <=3D ADF41513_MAX_INT_8_9) + result->prescaler =3D 1; + else if (int_value >=3D ADF41513_MIN_INT_FRAC_4_5 && int_value <=3D ADF41= 513_MAX_INT_4_5) + result->prescaler =3D 0; + else + return -ERANGE; + + /* compute frac1 and fixed modulus error */ + frac1 =3D mul_u64_u64_div_u64(freq_error_uhz, ADF41513_FIXED_MODULUS, + result->pfd_frequency_uhz); + freq_error_uhz -=3D mul_u64_u64_div_u64(frac1, result->pfd_frequency_uhz, + ADF41513_FIXED_MODULUS); + + /* check if freq error is within a tolerance of 1/2 resolution */ + if (freq_error_uhz > (resolution_uhz >> 1) && frac1 < (ADF41513_FIXED_MOD= ULUS - 1)) { + frac1++; + freq_error_uhz =3D resolution_uhz - freq_error_uhz; + } + + if (freq_error_uhz > st->data.freq_resolution_uhz) + return -ERANGE; + + /* integer part */ + result->actual_frequency_uhz =3D (u64)int_value * result->pfd_frequency_u= hz; + /* fractional part */ + if (lsb_p1_offset) + result->actual_frequency_uhz +=3D (resolution_uhz >> 1); + result->actual_frequency_uhz +=3D mul_u64_u64_div_u64(frac1, result->pfd_= frequency_uhz, + ADF41513_FIXED_MODULUS); + result->mode =3D ADF41513_MODE_FIXED_MODULUS; + result->int_value =3D int_value; + result->frac1 =3D frac1; + result->frac2 =3D 0; + result->mod2 =3D 0; + + return 0; +} + +static int adf41513_calc_variable_mod(struct adf41513_state *st, + struct adf41513_pll_settings *result) +{ + u64 freq_error_uhz; + u32 frac1, frac2, mod2; + u16 int_value =3D div64_u64_rem(result->target_frequency_uhz, + result->pfd_frequency_uhz, + &freq_error_uhz); + + if (st->chip_info->has_prescaler_8_9 && int_value >=3D ADF41513_MIN_INT_F= RAC_8_9 && + int_value <=3D ADF41513_MAX_INT_8_9) + result->prescaler =3D 1; + else if (int_value >=3D ADF41513_MIN_INT_FRAC_4_5 && int_value <=3D ADF41= 513_MAX_INT_4_5) + result->prescaler =3D 0; + else + return -ERANGE; + + /* calculate required mod2 based on target resolution / 2 */ + mod2 =3D DIV64_U64_ROUND_CLOSEST(result->pfd_frequency_uhz << 1, + st->data.freq_resolution_uhz * ADF41513_FIXED_MODULUS); + /* ensure mod2 is at least 2 for meaningful operation */ + mod2 =3D clamp(mod2, 2, ADF41513_MAX_MOD2); + + /* calculate frac1 and frac2 */ + frac1 =3D mul_u64_u64_div_u64(freq_error_uhz, ADF41513_FIXED_MODULUS, + result->pfd_frequency_uhz); + freq_error_uhz -=3D mul_u64_u64_div_u64(frac1, result->pfd_frequency_uhz, + ADF41513_FIXED_MODULUS); + frac2 =3D mul_u64_u64_div_u64(freq_error_uhz, (u64)mod2 * ADF41513_FIXED_= MODULUS, + result->pfd_frequency_uhz); + + /* integer part */ + result->actual_frequency_uhz =3D (u64)int_value * result->pfd_frequency_u= hz; + /* fractional part */ + result->actual_frequency_uhz +=3D mul_u64_u64_div_u64((u64)frac1 * mod2 += frac2, + result->pfd_frequency_uhz, + (u64)mod2 * ADF41513_FIXED_MODULUS); + result->mode =3D ADF41513_MODE_VARIABLE_MODULUS; + result->int_value =3D int_value; + result->frac1 =3D frac1; + result->frac2 =3D frac2; + result->mod2 =3D mod2; + + return 0; +} + +static int adf41513_calc_pll_settings(struct adf41513_state *st, + struct adf41513_pll_settings *result, + u64 rf_out_uhz) +{ + u64 max_rf_freq_uhz =3D st->chip_info->max_rf_freq_hz * MICROHZ_PER_HZ; + u64 min_rf_freq_uhz =3D ADF41513_MIN_RF_FREQ * MICROHZ_PER_HZ; + u64 pfd_freq_limit_uhz; + int ret; + + if (rf_out_uhz < min_rf_freq_uhz || rf_out_uhz > max_rf_freq_uhz) { + dev_err(&st->spi->dev, "RF frequency %llu uHz out of range [%llu, %llu] = uHz\n", + rf_out_uhz, min_rf_freq_uhz, max_rf_freq_uhz); + return -EINVAL; + } + + result->target_frequency_uhz =3D rf_out_uhz; + + /* try integer-N first (best phase noise performance) */ + pfd_freq_limit_uhz =3D min(div_u64(rf_out_uhz, ADF41513_MIN_INT_4_5), + ADF41513_MAX_PFD_FREQ_INT_N_UHZ); + ret =3D adf41513_calc_pfd_frequency(st, result, pfd_freq_limit_uhz); + if (ret < 0) + return ret; + + ret =3D adf41513_calc_integer_n(st, result); + if (ret < 0) { + /* try fractional-N: recompute pfd frequency if necessary */ + pfd_freq_limit_uhz =3D min(div_u64(rf_out_uhz, ADF41513_MIN_INT_FRAC_4_5= ), + ADF41513_MAX_PFD_FREQ_FRAC_N_UHZ); + if (pfd_freq_limit_uhz < result->pfd_frequency_uhz) { + ret =3D adf41513_calc_pfd_frequency(st, result, pfd_freq_limit_uhz); + if (ret < 0) + return ret; + } + + /* fixed-modulus attempt */ + ret =3D adf41513_calc_fixed_mod(st, result); + if (ret < 0) { + /* variable-modulus attempt */ + ret =3D adf41513_calc_variable_mod(st, result); + if (ret < 0) { + dev_err(&st->spi->dev, + "no valid PLL configuration found for %llu uHz\n", + rf_out_uhz); + return -EINVAL; + } + } + } + + return 0; +} + +static int adf41513_set_frequency(struct adf41513_state *st, u64 freq_uhz,= u16 sync_mask) +{ + struct adf41513_pll_settings result; + int ret; + + ret =3D adf41513_calc_pll_settings(st, &result, freq_uhz); + if (ret < 0) + return ret; + + /* apply computed results to pll settings */ + memcpy(&st->settings, &result, sizeof(st->settings)); + + dev_dbg(&st->spi->dev, + "%s mode: int=3D%u, frac1=3D%u, frac2=3D%u, mod2=3D%u, fpdf=3D%llu Hz, p= rescaler=3D%s\n", + (result.mode =3D=3D ADF41513_MODE_INTEGER_N) ? "integer-n" : + (result.mode =3D=3D ADF41513_MODE_FIXED_MODULUS) ? "fixed-modulus" : "va= riable-modulus", + result.int_value, result.frac1, result.frac2, result.mod2, + div64_u64(result.pfd_frequency_uhz, MICROHZ_PER_HZ), + result.prescaler ? "8/9" : "4/5"); + + st->regs[ADF41513_REG0] =3D FIELD_PREP(ADF41513_REG0_INT_MSK, + st->settings.int_value); + if (st->settings.mode =3D=3D ADF41513_MODE_VARIABLE_MODULUS) + st->regs[ADF41513_REG0] |=3D ADF41513_REG0_VAR_MOD_MSK; + + st->regs[ADF41513_REG1] =3D FIELD_PREP(ADF41513_REG1_FRAC1_MSK, + st->settings.frac1); + if (st->settings.mode !=3D ADF41513_MODE_INTEGER_N) + st->regs[ADF41513_REG1] |=3D ADF41513_REG1_DITHER2_MSK; + + st->regs[ADF41513_REG3] =3D FIELD_PREP(ADF41513_REG3_FRAC2_MSK, + st->settings.frac2); + FIELD_MODIFY(ADF41513_REG4_MOD2_MSK, &st->regs[ADF41513_REG4], + st->settings.mod2); + FIELD_MODIFY(ADF41513_REG5_R_CNT_MSK, &st->regs[ADF41513_REG5], + st->settings.r_counter); + FIELD_MODIFY(ADF41513_REG5_REF_DOUBLER_MSK, &st->regs[ADF41513_REG5], + st->settings.ref_doubler); + FIELD_MODIFY(ADF41513_REG5_RDIV2_MSK, &st->regs[ADF41513_REG5], + st->settings.ref_div2); + FIELD_MODIFY(ADF41513_REG5_PRESCALER_MSK, &st->regs[ADF41513_REG5], + st->settings.prescaler); + + if (st->settings.mode =3D=3D ADF41513_MODE_INTEGER_N) { + st->regs[ADF41513_REG6] |=3D ADF41513_REG6_INT_MODE_MSK; + st->regs[ADF41513_REG6] &=3D ~ADF41513_REG6_BLEED_ENABLE_MSK; + } else { + st->regs[ADF41513_REG6] &=3D ~ADF41513_REG6_INT_MODE_MSK; + st->regs[ADF41513_REG6] |=3D ADF41513_REG6_BLEED_ENABLE_MSK; + } + + return adf41513_sync_config(st, sync_mask | ADF41513_SYNC_REG0); +} + +static int adf41513_suspend(struct adf41513_state *st) +{ + st->regs[ADF41513_REG6] |=3D FIELD_PREP(ADF41513_REG6_POWER_DOWN_MSK, 1); + return adf41513_sync_config(st, ADF41513_SYNC_DIFF); +} + +static int adf41513_resume(struct adf41513_state *st) +{ + st->regs[ADF41513_REG6] &=3D ~ADF41513_REG6_POWER_DOWN_MSK; + return adf41513_sync_config(st, ADF41513_SYNC_DIFF); +} + +static ssize_t adf41513_read_uhz(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct adf41513_state *st =3D iio_priv(indio_dev); + u64 freq_uhz; + + guard(mutex)(&st->lock); + + switch ((u32)private) { + case ADF41513_FREQ: + freq_uhz =3D adf41513_pll_get_rate(st); + if (st->lock_detect) + if (!gpiod_get_value_cansleep(st->lock_detect)) { + dev_dbg(&st->spi->dev, "PLL un-locked\n"); + return -EBUSY; + } + break; + case ADF41513_FREQ_RESOLUTION: + freq_uhz =3D st->data.freq_resolution_uhz; + break; + default: + return -EINVAL; + } + + return adf41513_uhz_to_str(freq_uhz, buf); +} + +static ssize_t adf41513_read_powerdown(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct adf41513_state *st =3D iio_priv(indio_dev); + u32 val; + + guard(mutex)(&st->lock); + + switch ((u32)private) { + case ADF41513_POWER_DOWN: + val =3D FIELD_GET(ADF41513_REG6_POWER_DOWN_MSK, + st->regs_hw[ADF41513_REG6]); + return sysfs_emit(buf, "%u\n", val); + default: + return -EINVAL; + } +} + +static ssize_t adf41513_write_uhz(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct adf41513_state *st =3D iio_priv(indio_dev); + u64 freq_uhz; + int ret; + + ret =3D adf41513_parse_uhz(buf, &freq_uhz); + if (ret) + return ret; + + guard(mutex)(&st->lock); + + switch ((u32)private) { + case ADF41513_FREQ: + ret =3D adf41513_set_frequency(st, freq_uhz, ADF41513_SYNC_DIFF); + break; + case ADF41513_FREQ_RESOLUTION: + if (freq_uhz =3D=3D 0 || freq_uhz > ADF41513_MAX_FREQ_RESOLUTION_UHZ) + return -EINVAL; + st->data.freq_resolution_uhz =3D freq_uhz; + break; + default: + return -EINVAL; + } + + return ret ? ret : len; +} + +static ssize_t adf41513_write_powerdown(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct adf41513_state *st =3D iio_priv(indio_dev); + unsigned long readin; + int ret; + + ret =3D kstrtoul(buf, 10, &readin); + if (ret) + return ret; + + guard(mutex)(&st->lock); + + switch ((u32)private) { + case ADF41513_POWER_DOWN: + if (readin) + ret =3D adf41513_suspend(st); + else + ret =3D adf41513_resume(st); + break; + default: + return -EINVAL; + } + + return ret ? ret : len; +} + +#define _ADF41513_EXT_PD_INFO(_name, _ident) { \ + .name =3D _name, \ + .read =3D adf41513_read_powerdown, \ + .write =3D adf41513_write_powerdown, \ + .private =3D _ident, \ + .shared =3D IIO_SEPARATE, \ +} + +#define _ADF41513_EXT_UHZ_INFO(_name, _ident) { \ + .name =3D _name, \ + .read =3D adf41513_read_uhz, \ + .write =3D adf41513_write_uhz, \ + .private =3D _ident, \ + .shared =3D IIO_SEPARATE, \ +} + +static const struct iio_chan_spec_ext_info adf41513_ext_info[] =3D { + /* + * Ideally we would use IIO_CHAN_INFO_FREQUENCY, but the device supports + * frequency values greater 2^32 with sub-Hz resolution, i.e. 64-bit + * fixed point with 6 decimal places values are used to represent + * frequencies. + */ + _ADF41513_EXT_UHZ_INFO("frequency", ADF41513_FREQ), + _ADF41513_EXT_UHZ_INFO("frequency_resolution", ADF41513_FREQ_RESOLUTION), + _ADF41513_EXT_PD_INFO("powerdown", ADF41513_POWER_DOWN), + { } +}; + +static const struct iio_chan_spec adf41513_chan =3D { + .type =3D IIO_ALTVOLTAGE, + .indexed =3D 1, + .output =3D 1, + .channel =3D 0, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_PHASE), + .ext_info =3D adf41513_ext_info, +}; + +static int adf41513_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long info) +{ + struct adf41513_state *st =3D iio_priv(indio_dev); + u64 phase_urad; + u16 phase_val; + + guard(mutex)(&st->lock); + + switch (info) { + case IIO_CHAN_INFO_PHASE: + phase_val =3D FIELD_GET(ADF41513_REG2_PHASE_VAL_MSK, + st->regs_hw[ADF41513_REG2]); + phase_urad =3D (u64)phase_val * ADF41513_MAX_PHASE_MICRORAD; + phase_urad >>=3D 12; + *val =3D (u32)phase_urad / MICRO; + *val2 =3D (u32)phase_urad % MICRO; + return IIO_VAL_INT_PLUS_MICRO; + default: + return -EINVAL; + } +} + +static int adf41513_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long info) +{ + struct adf41513_state *st =3D iio_priv(indio_dev); + u64 phase_urad; + u16 phase_val; + + guard(mutex)(&st->lock); + + switch (info) { + case IIO_CHAN_INFO_PHASE: + phase_urad =3D (u64)val * MICRO + val2; + if (val < 0 || val2 < 0 || phase_urad >=3D ADF41513_MAX_PHASE_MICRORAD) + return -EINVAL; + + phase_val =3D DIV_U64_ROUND_CLOSEST(phase_urad << 12, + ADF41513_MAX_PHASE_MICRORAD); + phase_val =3D min(phase_val, ADF41513_MAX_PHASE_VAL); + st->regs[ADF41513_REG2] |=3D ADF41513_REG2_PHASE_ADJ_MSK; + FIELD_MODIFY(ADF41513_REG2_PHASE_VAL_MSK, + &st->regs[ADF41513_REG2], phase_val); + return adf41513_sync_config(st, ADF41513_SYNC_REG0); + default: + return -EINVAL; + } +} + +static int adf41513_reg_access(struct iio_dev *indio_dev, + unsigned int reg, + unsigned int writeval, + unsigned int *readval) +{ + struct adf41513_state *st =3D iio_priv(indio_dev); + + if (reg > ADF41513_REG13) + return -EINVAL; + + guard(mutex)(&st->lock); + + if (!readval) { + if (reg <=3D ADF41513_REG6) + st->settings.mode =3D ADF41513_MODE_INVALID; + st->regs[reg] =3D writeval & ~0xF; /* Clear control bits */ + return adf41513_sync_config(st, BIT(reg)); + } + + *readval =3D st->regs_hw[reg]; + return 0; +} + +static const struct iio_info adf41513_info =3D { + .read_raw =3D adf41513_read_raw, + .write_raw =3D adf41513_write_raw, + .debugfs_reg_access =3D &adf41513_reg_access, +}; + +static int adf41513_parse_fw(struct adf41513_state *st) +{ + struct device *dev =3D &st->spi->dev; + int ret; + u32 tmp, cp_resistance, cp_current; + + /* power-up frequency */ + st->data.power_up_frequency_hz =3D ADF41510_MAX_RF_FREQ; + ret =3D device_property_read_u32(dev, "adi,power-up-frequency-mhz", &tmp); + if (!ret) { + st->data.power_up_frequency_hz =3D (u64)tmp * HZ_PER_MHZ; + if (st->data.power_up_frequency_hz < ADF41513_MIN_RF_FREQ || + st->data.power_up_frequency_hz > ADF41513_MAX_RF_FREQ) + return dev_err_probe(dev, -ERANGE, + "power-up frequency %llu Hz out of range\n", + st->data.power_up_frequency_hz); + } + + st->data.ref_div_factor =3D ADF41513_MIN_R_CNT; + ret =3D device_property_read_u32(dev, "adi,reference-div-factor", &tmp); + if (!ret) { + if (tmp < ADF41513_MIN_R_CNT || tmp > ADF41513_MAX_R_CNT) + return dev_err_probe(dev, -ERANGE, + "invalid reference div factor %u\n", tmp); + st->data.ref_div_factor =3D tmp; + } + + st->data.ref_doubler_en =3D device_property_read_bool(dev, "adi,reference= -doubler-enable"); + st->data.ref_div2_en =3D device_property_read_bool(dev, "adi,reference-di= v2-enable"); + + cp_resistance =3D ADF41513_DEFAULT_R_SET; + ret =3D device_property_read_u32(dev, "adi,charge-pump-resistor-ohms", &c= p_resistance); + if (!ret && (cp_resistance < ADF41513_MIN_R_SET || cp_resistance > ADF415= 13_MAX_R_SET)) + return dev_err_probe(dev, -ERANGE, "R_SET %u Ohms out of range\n", cp_re= sistance); + + st->data.charge_pump_voltage_mv =3D ADF41513_DEFAULT_CP_VOLTAGE_mV; + ret =3D device_property_read_u32(dev, "adi,charge-pump-current-microamp",= &cp_current); + if (!ret) { + tmp =3D DIV_ROUND_CLOSEST(cp_current * cp_resistance, MILLI); /* convert= to mV */ + if (tmp < ADF41513_MIN_CP_VOLTAGE_mV || tmp > ADF41513_MAX_CP_VOLTAGE_mV) + return dev_err_probe(dev, -ERANGE, "I_CP %u uA (%u Ohms) out of range\n= ", + cp_current, cp_resistance); + st->data.charge_pump_voltage_mv =3D tmp; + } + + st->data.phase_detector_polarity =3D + device_property_read_bool(dev, "adi,phase-detector-polarity-positive-ena= ble"); + + st->data.logic_lvl_1v8_en =3D device_property_read_bool(dev, "adi,logic-l= evel-1v8-enable"); + + st->data.lock_detect_count =3D ADF41513_LD_COUNT_MIN; + ret =3D device_property_read_u32(dev, "adi,lock-detector-count", &tmp); + if (!ret) { + if (tmp < ADF41513_LD_COUNT_FAST_MIN || tmp > ADF41513_LD_COUNT_MAX || + !is_power_of_2(tmp)) + return dev_err_probe(dev, -ERANGE, + "invalid lock detect count: %u\n", tmp); + st->data.lock_detect_count =3D tmp; + } + + st->data.freq_resolution_uhz =3D MICROHZ_PER_HZ; + + return 0; +} + +static int adf41513_setup(struct adf41513_state *st) +{ + u32 tmp; + + memset(st->regs_hw, 0xFF, sizeof(st->regs_hw)); + + /* assuming DLD pin is used for lock detection */ + st->regs[ADF41513_REG5] =3D FIELD_PREP(ADF41513_REG5_DLD_MODES_MSK, + ADF41513_DLD_DIG_LD); + + tmp =3D DIV_ROUND_CLOSEST(st->data.charge_pump_voltage_mv, ADF41513_MIN_C= P_VOLTAGE_mV); + st->regs[ADF41513_REG5] |=3D FIELD_PREP(ADF41513_REG5_CP_CURRENT_MSK, tmp= - 1); + + st->regs[ADF41513_REG6] =3D ADF41513_REG6_ABP_MSK | + ADF41513_REG6_LOL_ENABLE_MSK | + ADF41513_REG6_SD_RESET_MSK; + if (st->data.phase_detector_polarity) + st->regs[ADF41513_REG6] |=3D ADF41513_REG6_PD_POLARITY_MSK; + + st->regs[ADF41513_REG7] =3D FIELD_PREP(ADF41513_REG7_PS_BIAS_MSK, + ADF41513_PS_BIAS_INIT); + tmp =3D ilog2(st->data.lock_detect_count); + if (st->data.lock_detect_count < ADF41513_LD_COUNT_FAST_LIMIT) { + tmp -=3D const_ilog2(ADF41513_LD_COUNT_FAST_MIN); + st->regs[ADF41513_REG7] |=3D ADF41513_REG7_LD_CLK_SEL_MSK; + } else { + tmp -=3D const_ilog2(ADF41513_LD_COUNT_MIN); + } + st->regs[ADF41513_REG7] |=3D FIELD_PREP(ADF41513_REG7_LD_COUNT_MSK, tmp); + + st->regs[ADF41513_REG11] =3D ADF41513_REG11_POWER_DOWN_SEL_MSK; + st->regs[ADF41513_REG12] =3D FIELD_PREP(ADF41513_REG12_LOGIC_LEVEL_MSK, + st->data.logic_lvl_1v8_en ? 0 : 1); + + /* perform initialization sequence with power-up frequency */ + return adf41513_set_frequency(st, st->data.power_up_frequency_hz * MICROH= Z_PER_HZ, + ADF41513_SYNC_ALL); +} + +static void adf41513_power_down(void *data) +{ + struct adf41513_state *st =3D data; + + adf41513_suspend(st); + if (st->chip_enable) + gpiod_set_value_cansleep(st->chip_enable, 0); +} + +static int adf41513_pm_suspend(struct device *dev) +{ + return adf41513_suspend(dev_get_drvdata(dev)); +} + +static int adf41513_pm_resume(struct device *dev) +{ + return adf41513_resume(dev_get_drvdata(dev)); +} + +static const struct adf41513_chip_info adf41510_chip_info =3D { + .has_prescaler_8_9 =3D false, + .max_rf_freq_hz =3D ADF41510_MAX_RF_FREQ, +}; + +static const struct adf41513_chip_info adf41513_chip_info =3D { + .has_prescaler_8_9 =3D true, + .max_rf_freq_hz =3D ADF41513_MAX_RF_FREQ, +}; + +static int adf41513_probe(struct spi_device *spi) +{ + struct iio_dev *indio_dev; + struct adf41513_state *st; + struct device *dev =3D &spi->dev; + int ret; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + st->spi =3D spi; + st->chip_info =3D spi_get_device_match_data(spi); + if (!st->chip_info) + return -EINVAL; + + spi_set_drvdata(spi, st); + + st->ref_clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(st->ref_clk)) + return PTR_ERR(st->ref_clk); + + st->ref_freq_hz =3D clk_get_rate(st->ref_clk); + if (st->ref_freq_hz < ADF41513_MIN_REF_FREQ || st->ref_freq_hz > ADF41513= _MAX_REF_FREQ) + return dev_err_probe(dev, -ERANGE, + "reference frequency %u Hz out of range\n", + st->ref_freq_hz); + + ret =3D adf41513_parse_fw(st); + if (ret) + return ret; + + ret =3D devm_regulator_bulk_get_enable(dev, + ARRAY_SIZE(adf41513_power_supplies), + adf41513_power_supplies); + if (ret) + return dev_err_probe(dev, ret, + "failed to get and enable regulators\n"); + + st->chip_enable =3D devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_HIGH= ); + if (IS_ERR(st->chip_enable)) + return dev_err_probe(dev, PTR_ERR(st->chip_enable), + "fail to request chip enable GPIO\n"); + + st->lock_detect =3D devm_gpiod_get_optional(dev, "lock-detect", GPIOD_IN); + if (IS_ERR(st->lock_detect)) + return dev_err_probe(dev, PTR_ERR(st->lock_detect), + "fail to request lock detect GPIO\n"); + + ret =3D devm_mutex_init(dev, &st->lock); + if (ret) + return ret; + + indio_dev->name =3D spi_get_device_id(spi)->name; + indio_dev->info =3D &adf41513_info; + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->channels =3D &adf41513_chan; + indio_dev->num_channels =3D 1; + + ret =3D adf41513_setup(st); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to setup device\n"); + + ret =3D devm_add_action_or_reset(dev, adf41513_power_down, st); + if (ret) + return dev_err_probe(dev, ret, "Failed to add power down action\n"); + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct spi_device_id adf41513_id[] =3D { + {"adf41510", (kernel_ulong_t)&adf41510_chip_info}, + {"adf41513", (kernel_ulong_t)&adf41513_chip_info}, + { } +}; +MODULE_DEVICE_TABLE(spi, adf41513_id); + +static const struct of_device_id adf41513_of_match[] =3D { + { .compatible =3D "adi,adf41510", .data =3D &adf41510_chip_info }, + { .compatible =3D "adi,adf41513", .data =3D &adf41513_chip_info }, + { } +}; +MODULE_DEVICE_TABLE(of, adf41513_of_match); + +static DEFINE_SIMPLE_DEV_PM_OPS(adf41513_pm_ops, adf41513_pm_suspend, adf4= 1513_pm_resume); + +static struct spi_driver adf41513_driver =3D { + .driver =3D { + .name =3D "adf41513", + .pm =3D pm_ptr(&adf41513_pm_ops), + .of_match_table =3D adf41513_of_match, + }, + .probe =3D adf41513_probe, + .id_table =3D adf41513_id, +}; +module_spi_driver(adf41513_driver); + +MODULE_AUTHOR("Rodrigo Alencar "); +MODULE_DESCRIPTION("Analog Devices ADF41513 PLL Frequency Synthesizer"); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Sun Feb 8 18:18:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D69FF4A1A7D; Thu, 8 Jan 2026 12:15:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260108-adf41513-iio-driver-v3-3-23d1371aef48@analog.com> References: <20260108-adf41513-iio-driver-v3-0-23d1371aef48@analog.com> In-Reply-To: <20260108-adf41513-iio-driver-v3-0-23d1371aef48@analog.com> To: linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org Cc: Jonathan Cameron , David Lechner , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767874513; l=2933; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=X9/n4zTkaJgPCbGxxfeWNVQxYgRQ+AOLCLzn3Kd+1lY=; b=M9/lJEnRdexE2rLI5Z5cDbipXXX0TqcrPlQoA7EnXZJ05UYVJBYVtmi3lFqeJhmglc4JTmqKP TLwxh4na/e/ABporUU3NF4DSnkInPtizdOs7vh+2d8jTBFKb9zPxtjK X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar When LE sync is enabled, it is must be set after powering up and must be disabled when powering down. It is recommended when using the PLL as a frequency synthesizer, where reference signal will always be present while the device is being configured. Signed-off-by: Rodrigo Alencar --- drivers/iio/frequency/adf41513.c | 32 +++++++++++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/drivers/iio/frequency/adf41513.c b/drivers/iio/frequency/adf41= 513.c index 69dcbbc1f393..0cdf24989c93 100644 --- a/drivers/iio/frequency/adf41513.c +++ b/drivers/iio/frequency/adf41513.c @@ -220,6 +220,7 @@ struct adf41513_data { bool phase_detector_polarity; =20 bool logic_lvl_1v8_en; + bool le_sync_en; }; =20 struct adf41513_pll_settings { @@ -697,13 +698,25 @@ static int adf41513_set_frequency(struct adf41513_sta= te *st, u64 freq_uhz, u16 s static int adf41513_suspend(struct adf41513_state *st) { st->regs[ADF41513_REG6] |=3D FIELD_PREP(ADF41513_REG6_POWER_DOWN_MSK, 1); + st->regs[ADF41513_REG12] &=3D ~ADF41513_REG12_LE_SELECT_MSK; return adf41513_sync_config(st, ADF41513_SYNC_DIFF); } =20 static int adf41513_resume(struct adf41513_state *st) { + int ret; + st->regs[ADF41513_REG6] &=3D ~ADF41513_REG6_POWER_DOWN_MSK; - return adf41513_sync_config(st, ADF41513_SYNC_DIFF); + ret =3D adf41513_sync_config(st, ADF41513_SYNC_DIFF); + if (ret < 0) + return ret; + + if (st->data.le_sync_en) { + st->regs[ADF41513_REG12] |=3D ADF41513_REG12_LE_SELECT_MSK; + ret =3D adf41513_sync_config(st, ADF41513_SYNC_DIFF); + } + + return ret; } =20 static ssize_t adf41513_read_uhz(struct iio_dev *indio_dev, @@ -994,6 +1007,8 @@ static int adf41513_parse_fw(struct adf41513_state *st) st->data.lock_detect_count =3D tmp; } =20 + /* load enable sync */ + st->data.le_sync_en =3D device_property_read_bool(dev, "adi,le-sync-enabl= e"); st->data.freq_resolution_uhz =3D MICROHZ_PER_HZ; =20 return 0; @@ -1001,6 +1016,7 @@ static int adf41513_parse_fw(struct adf41513_state *s= t) =20 static int adf41513_setup(struct adf41513_state *st) { + int ret; u32 tmp; =20 memset(st->regs_hw, 0xFF, sizeof(st->regs_hw)); @@ -1034,8 +1050,18 @@ static int adf41513_setup(struct adf41513_state *st) st->data.logic_lvl_1v8_en ? 0 : 1); =20 /* perform initialization sequence with power-up frequency */ - return adf41513_set_frequency(st, st->data.power_up_frequency_hz * MICROH= Z_PER_HZ, - ADF41513_SYNC_ALL); + ret =3D adf41513_set_frequency(st, + st->data.power_up_frequency_hz * MICROHZ_PER_HZ, + ADF41513_SYNC_ALL); + if (ret < 0) + return ret; + + if (st->data.le_sync_en) { + st->regs[ADF41513_REG12] |=3D ADF41513_REG12_LE_SELECT_MSK; + ret =3D adf41513_sync_config(st, ADF41513_SYNC_DIFF); + } + + return ret; } =20 static void adf41513_power_down(void *data) --=20 2.43.0 From nobody Sun Feb 8 18:18:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01C3548707A; Thu, 8 Jan 2026 12:15:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767874517; cv=none; b=Liy2sA8OXLx2QJewagyvNM4LJA1NRhFxFxCRVdN2sHh81vBGnhPQmLbjw0bOxImaOxAtPmzpEwoUUy2kAtMVywGUW2SSm0On8tGRTT34NTrfy8s6vfle9QuoDCATC0QOmCYpI2MNkLmMAZrHwDhYpNy8GfLU3AmHXiI+wkviBx4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767874517; c=relaxed/simple; bh=FRu8BScto0P3wia7SaGcoWc/g7iS2VAzdGOucLD61BU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=C8cG6aGUhJNIwB+fQ/q/qbq2bxEQcibMwuKKJUWSQb0adQmsrZuxFYY3RnmwhTQYZhQ/cwHu2f9CLuxn8Vjysr7dIBGV1fr3TrVbkDv7a9cYK7cAXMx/kkTGW1hiuZotyJkJjUtxyxPFlN23e7RLCsLTKYzLxkiXfuPiqxoBZxE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FBiiHRm/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FBiiHRm/" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6129CC2BCB0; Thu, 8 Jan 2026 12:15:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1767874515; bh=FRu8BScto0P3wia7SaGcoWc/g7iS2VAzdGOucLD61BU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=FBiiHRm/M0Mc2Q37rSeZTCzGzTUlzLv3oiX30ULw2B15qFJQ5QxOtrROfn7tVFdbb hW+8rzRnFojgYyPrcW1BCDZ2GKHgWahkxnGmoDFdQcYWAXikEh/DOFlsrYX7U4v706 jt7dsVYeHBAAeUj7q/S6IGbylZBfVIe4ji/GwxXs6bg+juVw7g0j6OutRwvDVd2DUf KlOnyR29ZbQBz+aUZ2z5DicfAG2QlZWC01HEGLcHXfUYIUh0Gj2UFA1ZTq4ttAbU4P G1xnXlBBQLVRKGOWkMYdpCZAN8ReA+hGdSaUL1/i1jPLaGApZLw3WSd33M2YrSTnyz NOeH5HZtWTIpw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57AFAD185EB; Thu, 8 Jan 2026 12:15:15 +0000 (UTC) From: Rodrigo Alencar via B4 Relay Date: Thu, 08 Jan 2026 12:14:53 +0000 Subject: [PATCH v3 4/6] iio: frequency: adf41513: features on frequency change Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260108-adf41513-iio-driver-v3-4-23d1371aef48@analog.com> References: <20260108-adf41513-iio-driver-v3-0-23d1371aef48@analog.com> In-Reply-To: <20260108-adf41513-iio-driver-v3-0-23d1371aef48@analog.com> To: linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org Cc: Jonathan Cameron , David Lechner , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767874513; l=5432; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=UMWuvBM+9pvQjYkP22YDroVjp7uL8qCp5KLHrroiJPQ=; b=h0iUgA5GW8Vpok1nte3674p/djQLTuAGgF1KCsEysE8rQXnUFOIImprsLQG4FAWdKG74OTVYc 96DjNK0sjjlB0gst6kXE6/KNbp8UWEZnL7eZLXMJ+wJp0ea47CVWaNH X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar Set Bleed current when PFD frequency changes (bleed enabled when in fractional mode). Set lock detector window size, handling bias and precision. Add phase resync support, setting clock dividers when PFD frequency changes. Signed-off-by: Rodrigo Alencar --- drivers/iio/frequency/adf41513.c | 99 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 99 insertions(+) diff --git a/drivers/iio/frequency/adf41513.c b/drivers/iio/frequency/adf41= 513.c index 0cdf24989c93..c838e219ca22 100644 --- a/drivers/iio/frequency/adf41513.c +++ b/drivers/iio/frequency/adf41513.c @@ -211,6 +211,7 @@ struct adf41513_chip_info { struct adf41513_data { u64 power_up_frequency_hz; u64 freq_resolution_uhz; + u32 phase_resync_period_ns; u32 charge_pump_voltage_mv; u32 lock_detect_count; =20 @@ -275,6 +276,16 @@ struct adf41513_state { __be32 buf __aligned(IIO_DMA_MINALIGN); }; =20 +static const u16 adf41513_ld_window_p1ns[] =3D { + 9, 12, 16, 17, 21, 28, 29, 35, /* 0 - 7 */ + 43, 47, 49, 52, 70, 79, 115 /* 8 - 14 */ +}; + +static const u8 adf41513_ldp_bias[] =3D { + 0xC, 0xD, 0xE, 0x8, 0x9, 0x4, 0xA, 0x5, /* 0 - 7 */ + 0x0, 0x6, 0xB, 0x1, 0x2, 0x7, 0x3 /* 8 - 14 */ +}; + static const char * const adf41513_power_supplies[] =3D { "avdd1", "avdd2", "avdd3", "avdd4", "avdd5", "vp" }; @@ -641,9 +652,82 @@ static int adf41513_calc_pll_settings(struct adf41513_= state *st, return 0; } =20 +static void adf41513_set_bleed_val(struct adf41513_state *st) +{ + u32 bleed_value; + + if (st->data.phase_detector_polarity) + bleed_value =3D 90; + else + bleed_value =3D 144; + + bleed_value *=3D 1 + FIELD_GET(ADF41513_REG5_CP_CURRENT_MSK, + st->regs[ADF41513_REG5]); + bleed_value =3D div64_u64(st->settings.pfd_frequency_uhz * bleed_value, + 1600ULL * HZ_PER_MHZ * MICROHZ_PER_HZ); + + FIELD_MODIFY(ADF41513_REG6_BLEED_CURRENT_MSK, &st->regs[ADF41513_REG6], + bleed_value); +} + +static void adf41513_set_ld_window(struct adf41513_state *st) +{ + /* + * The ideal lock detector window size is halfway between the max + * window, set by the phase comparison period t_PFD =3D (1 / f_PFD), + * and the minimum is set by (I_BLEED/I_CP) =C3=97 t_PFD + */ + u16 ld_window_p1ns =3D div64_u64(10ULL * NANO * MICROHZ_PER_HZ, + st->settings.pfd_frequency_uhz << 1); + u8 ld_idx, ldp, ld_bias; + + if (st->settings.mode !=3D ADF41513_MODE_INTEGER_N) { + /* account for bleed current (deduced from eq.6 and eq.7) */ + if (st->data.phase_detector_polarity) + ld_window_p1ns +=3D 4; + else + ld_window_p1ns +=3D 6; + } + + ld_idx =3D find_closest(ld_window_p1ns, adf41513_ld_window_p1ns, + ARRAY_SIZE(adf41513_ld_window_p1ns)); + ldp =3D (adf41513_ldp_bias[ld_idx] >> 2) & 0x3; + ld_bias =3D adf41513_ldp_bias[ld_idx] & 0x3; + + FIELD_MODIFY(ADF41513_REG6_LDP_MSK, &st->regs[ADF41513_REG6], ldp); + FIELD_MODIFY(ADF41513_REG9_LD_BIAS_MSK, &st->regs[ADF41513_REG9], ld_bias= ); +} + +static void adf41513_set_phase_resync(struct adf41513_state *st) +{ + u32 total_div, clk1_div, clk2_div; + + if (!st->data.phase_resync_period_ns) + return; + + /* assuming both clock dividers hold similar values */ + total_div =3D mul_u64_u64_div_u64(st->settings.pfd_frequency_uhz, + st->data.phase_resync_period_ns, + 1ULL * MICRO * NANO); + clk1_div =3D clamp(int_sqrt(total_div), 1, + ADF41513_MAX_CLK_DIVIDER); + clk2_div =3D clamp(DIV_ROUND_CLOSEST(total_div, clk1_div), 1, + ADF41513_MAX_CLK_DIVIDER); + + FIELD_MODIFY(ADF41513_REG5_CLK1_DIV_MSK, &st->regs[ADF41513_REG5], + clk1_div); + FIELD_MODIFY(ADF41513_REG7_CLK2_DIV_MSK, &st->regs[ADF41513_REG7], + clk2_div); + + /* enable phase resync */ + st->regs[ADF41513_REG7] |=3D ADF41513_REG7_CLK_DIV_MODE_MSK; +} + static int adf41513_set_frequency(struct adf41513_state *st, u64 freq_uhz,= u16 sync_mask) { struct adf41513_pll_settings result; + bool pfd_change =3D false; + bool mode_change =3D false; int ret; =20 ret =3D adf41513_calc_pll_settings(st, &result, freq_uhz); @@ -651,6 +735,8 @@ static int adf41513_set_frequency(struct adf41513_state= *st, u64 freq_uhz, u16 s return ret; =20 /* apply computed results to pll settings */ + pfd_change =3D st->settings.pfd_frequency_uhz !=3D result.pfd_frequency_u= hz; + mode_change =3D st->settings.mode !=3D result.mode; memcpy(&st->settings, &result, sizeof(st->settings)); =20 dev_dbg(&st->spi->dev, @@ -692,6 +778,14 @@ static int adf41513_set_frequency(struct adf41513_stat= e *st, u64 freq_uhz, u16 s st->regs[ADF41513_REG6] |=3D ADF41513_REG6_BLEED_ENABLE_MSK; } =20 + if (pfd_change) { + adf41513_set_bleed_val(st); + adf41513_set_phase_resync(st); + } + + if (pfd_change || mode_change) + adf41513_set_ld_window(st); + return adf41513_sync_config(st, sync_mask | ADF41513_SYNC_REG0); } =20 @@ -995,6 +1089,11 @@ static int adf41513_parse_fw(struct adf41513_state *s= t) st->data.phase_detector_polarity =3D device_property_read_bool(dev, "adi,phase-detector-polarity-positive-ena= ble"); =20 + st->data.phase_resync_period_ns =3D 0; + ret =3D device_property_read_u32(dev, "adi,phase-resync-period-ns", &tmp); + if (!ret) + st->data.phase_resync_period_ns =3D tmp; + st->data.logic_lvl_1v8_en =3D device_property_read_bool(dev, "adi,logic-l= evel-1v8-enable"); =20 st->data.lock_detect_count =3D ADF41513_LD_COUNT_MIN; --=20 2.43.0 From nobody Sun Feb 8 18:18:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0165F480338; Thu, 8 Jan 2026 12:15:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260108-adf41513-iio-driver-v3-5-23d1371aef48@analog.com> References: <20260108-adf41513-iio-driver-v3-0-23d1371aef48@analog.com> In-Reply-To: <20260108-adf41513-iio-driver-v3-0-23d1371aef48@analog.com> To: linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org Cc: Jonathan Cameron , David Lechner , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767874513; l=8999; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=8oyk+0EMFPwmJHG1OC/3EQ4VesKU+46HXyz+yO6kPUA=; b=WEpjUjpcre2FmGpC6a2HuKhGvvpaJEh3FuH4dMCt8EtWyRFQabmSMD4z7cJYTu8xp0K6TIBxF e4nl885OJ3BCABOkuEU0vYH8oJpjotMZ3oqTuABifQHAE4smzdEA5Yk X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar Add documentation for ADF41513 driver which describes the device driver files and shows how userspace may consume the ABI for various tasks Signed-off-by: Rodrigo Alencar --- Documentation/iio/adf41513.rst | 199 +++++++++++++++++++++++++++++++++++++= ++++ Documentation/iio/index.rst | 1 + MAINTAINERS | 1 + 3 files changed, 201 insertions(+) diff --git a/Documentation/iio/adf41513.rst b/Documentation/iio/adf41513.rst new file mode 100644 index 000000000000..4193c825b532 --- /dev/null +++ b/Documentation/iio/adf41513.rst @@ -0,0 +1,199 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +ADF41513 driver +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +This driver supports Analog Devices' ADF41513 and similar SPI PLL frequency +synthesizers. + +1. Supported devices +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +* `ADF41510 `_ +* `ADF41513 `_ + +The ADF41513 is an ultralow noise frequency synthesizer that can be used to +implement local oscillators (LOs) as high as 26.5 GHz in the upconversion = and +downconversion sections of wireless receivers and transmitters. The ADF415= 10 +is a similar device that supports frequencies up to 10 GHz. + +Both devices support integer-N and fractional-N operation modes, providing +excellent phase noise performance and flexible frequency generation +capabilities. + +Key Features: + +- **ADF41510**: 1 GHz to 10 GHz frequency range +- **ADF41513**: 1 GHz to 26.5 GHz frequency range +- Integer-N and fractional-N operation modes +- Ultra-low phase noise (-235 dBc/Hz integer-N, -231 dBc/Hz fractional-N) +- High maximum PFD frequency (250 MHz integer-N, 125 MHz fractional-N) +- 25-bit fixed modulus or 49-bit variable modulus fractional modes +- Programmable charge pump currents with 16x range +- Digital lock detect functionality +- Phase resync capability for consistent output phase + +2. Device attributes +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The ADF41513 driver provides the following IIO extended attributes for +frequency control and monitoring: + +Each IIO device has a device folder under ``/sys/bus/iio/devices/iio:devic= eX``, +where X is the IIO index of the device. Under these folders reside a set of +device files that provide access to the synthesizer's functionality. + +The following table shows the ADF41513 related device files: + ++----------------------+--------------------------------------------------= -----+ +| Device file | Description = | ++=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D+ +| frequency | RF output frequency control and readback (Hz) = | ++----------------------+--------------------------------------------------= -----+ +| frequency_resolution | Target frequency resolution control (Hz) = | ++----------------------+--------------------------------------------------= -----+ +| powerdown | Power management control (0=3Dactive, 1=3Dpower d= own) | ++----------------------+--------------------------------------------------= -----+ +| phase | RF output phase adjustment and readback (radians)= | ++----------------------+--------------------------------------------------= -----+ + +2.1 Frequency Control +---------------------- + +The ``frequency`` attribute controls the RF output frequency with sub-Hz +precision. The driver automatically selects between integer-N and fraction= al-N +modes to achieve the requested frequency with the best possible phase noise +performance. + +**Supported ranges:** + +- **ADF41510**: 1,000,000,000 Hz to 10,000,000,000 Hz (1 GHz to 10 GHz) +- **ADF41513**: 1,000,000,000 Hz to 26,500,000,000 Hz (1 GHz to 26.5 GHz) + +The frequency is specified in Hz, for sub-Hz precision use decimal notatio= n. +For example, 12.102 GHz would be written as "12102000000.000000". + +2.2 Frequency Resolution Control +-------------------------------- + +The ``frequency_resolution`` attribute controls the target frequency resol= ution +that the driver attempts to achieve. This affects the choice between integ= er-N +and fractional-N modes, including fixed modulus (25-bit) and variable modu= lus +(49-bit) fractional-N modes: + +- **Integer-N**: Resolution =3D f_PFD +- **Fixed modulus**: Resolution =3D f_PFD / 2^25 (~3 Hz with 100 MHz PFD) +- **Variable modulus**: Resolution =3D f_PFD / 2^49 (=C2=B5Hz resolution p= ossible) + +Default resolution is 1 Hz (1,000,000 =C2=B5Hz). + +2.3 Phase adjustment +-------------------- + +The ``phase`` attribute allows adjustment of the output phase in radians. +Setting this attribute enables phase adjustment. It can be set from 0 to 2= *pi +radians. Reading this attribute returns the current phase offset of the ou= tput +signal. To create a consistent phase relationship with the reference signa= l, +the phase resync feature needs to be enabled by setting a non-zero value t= o the +``adi,phase-resync-period-ns`` device property, which triggers a phase +resynchronization after locking is achieved. + +3. Operating modes +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +3.1 Integer-N Mode +------------------ + +When the requested frequency can be achieved as an integer multiple of the= PFD +frequency (within the specified resolution tolerance), the driver automati= cally +selects integer-N mode for optimal phase noise performance. + +In integer-N mode: + +- Phase noise: -235 dBc/Hz normalized floor +- Frequency resolution: f_PFD (same as PFD frequency) +- Maximum PFD frequency: 250 MHz +- Bleed current: Disabled + +3.2 Fractional-N Mode +--------------------- + +When sub-integer frequency steps are required, the driver automatically se= lects +fractional-N mode using either fixed or variable modulus. + +**Fixed Modulus (25-bit)**: + +- Used when variable modulus is not required +- Resolution: f_PFD / 2^25 +- Simpler implementation, faster settling + +**Variable Modulus (49-bit)**: + +- Used for maximum resolution requirements +- Resolution: f_PFD / 2^49 (theoretical) +- Exact frequency synthesis capability + +In fractional-N mode: + +- Phase noise: -231 dBc/Hz normalized floor +- Maximum PFD frequency: 125 MHz +- Bleed current: Automatically enabled and optimized +- Dithering: Enabled to reduce fractional spurs + +3.3 Automatic Mode Selection +---------------------------- + +The driver automatically selects the optimal operating mode based on: + +1. **Frequency accuracy requirements**: Determined by frequency_resolution= setting +2. **Phase noise optimization**: Integer-N preferred when possible +3. **PFD frequency constraints**: Different limits for integer vs fraction= al modes +4. **Prescaler selection**: Automatic 4/5 vs 8/9 prescaler selection based= on frequency + +4. Usage examples +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +4.1 Basic Frequency Setting +---------------------------- + +Set output frequency to 12.102 GHz: + +.. code-block:: bash + + root:/sys/bus/iio/devices/iio:device0> echo 12102000000 > out_altvolta= ge0_frequency + +Read current frequency: + +.. code-block:: bash + + root:/sys/bus/iio/devices/iio:device0> cat out_altvoltage0_frequency + 12101999999.582767 + +4.2 High Resolution Frequency Control +------------------------------------- + +Configure for sub-Hz resolution and set a precise frequency: + +.. code-block:: bash + + # Set resolution to 0.1 Hz (100,000 =C2=B5Hz) + root:/sys/bus/iio/devices/iio:device0> echo 0.1 > out_altvoltage0_freq= uency_resolution + + # Set frequency to 12.102 GHz (1 =C2=B5Hz precision) + root:/sys/bus/iio/devices/iio:device0> echo 12102000000 > out_altvolta= ge0_frequency + root:/sys/bus/iio/devices/iio:device0> cat out_altvoltage0_frequency + 12101999999.980131 + +4.3 Monitor Lock Status +----------------------- + +When lock detect GPIO is configured, check if PLL is locked: + +.. code-block:: bash + + # Read frequency - will return error if not locked + root:/sys/bus/iio/devices/iio:device0> cat out_altvoltage0_frequency + +If the PLL is not locked, the frequency read will return ``-EBUSY`` (Devic= e or +resource busy). diff --git a/Documentation/iio/index.rst b/Documentation/iio/index.rst index ba3e609c6a13..605871765c78 100644 --- a/Documentation/iio/index.rst +++ b/Documentation/iio/index.rst @@ -30,6 +30,7 @@ Industrial I/O Kernel Drivers ad7625 ad7944 ade9000 + adf41513 adis16475 adis16480 adis16550 diff --git a/MAINTAINERS b/MAINTAINERS index a5c5f76f47c6..3bb7d9fe7ed8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1616,6 +1616,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/frequency/adi,adf41513.yaml +F: Documentation/iio/adf41513.rst F: drivers/iio/frequency/adf41513.c =20 ANALOG DEVICES INC ADF4377 DRIVER --=20 2.43.0 From nobody Sun Feb 8 18:18:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01748482201; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260108-adf41513-iio-driver-v3-6-23d1371aef48@analog.com> References: <20260108-adf41513-iio-driver-v3-0-23d1371aef48@analog.com> In-Reply-To: <20260108-adf41513-iio-driver-v3-0-23d1371aef48@analog.com> To: linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org Cc: Jonathan Cameron , David Lechner , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767874513; l=1730; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=G8lkskp439tmkyRoT9F24VAmxHi49pi19EkNAx8s4Mc=; b=3wJO6+sacBSehsN32V8hDJVbltIkuZW6oQEBtjzTIHPVBMMZAPW88TZVj39pbuwlb1qMTqhDi utJND7YHF5HDjNPZAcL55s0Dny6c5+s1CuuuR7mBLK9q8R1XWDa64R+ X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar Add ABI documentation file for PLL/DDS devices with frequency_resolution sysfs entry attribute used by ADF4350 and ADF41513 Signed-off-by: Rodrigo Alencar --- Documentation/ABI/testing/sysfs-bus-iio-frequency | 11 +++++++++++ MAINTAINERS | 1 + 2 files changed, 12 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-iio-frequency b/Documentat= ion/ABI/testing/sysfs-bus-iio-frequency new file mode 100644 index 000000000000..1ce8ae578fd6 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-iio-frequency @@ -0,0 +1,11 @@ +What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_frequency_resoluti= on +KernelVersion: 6.20 +Contact: linux-iio@vger.kernel.org +Description: + Stores channel Y frequency resolution/channel spacing in Hz for PLL + devices. The given value directly influences the operating mode when + fractional-N synthesis is required, as it derives values for + configurable modulus parameters used in the calculation of the output + frequency. It is assumed that the algorithm that is used to compute + the various dividers, is able to generate proper values for multiples + of channel spacing. diff --git a/MAINTAINERS b/MAINTAINERS index 3bb7d9fe7ed8..f0dc0e7c1bbc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1615,6 +1615,7 @@ M: Rodrigo Alencar L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers +F: Documentation/ABI/testing/sysfs-bus-iio-frequency F: Documentation/devicetree/bindings/iio/frequency/adi,adf41513.yaml F: Documentation/iio/adf41513.rst F: drivers/iio/frequency/adf41513.c --=20 2.43.0