From nobody Sun Feb 8 16:24:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52658339B34; Thu, 8 Jan 2026 06:08:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767852506; cv=none; b=hfP50I+0Cmx/3htaOtgmh6U1KRPehJ5m3ZT6zXCA+WwdWOo4+FrziDn/x7rKgXGPdKiGz1vxhn03TI+UFdCyEIwEyw4/cmSRMQKZmMzQAQz5PVCw185G1gg4nc/3gI/YMfLqyzuIfjPlwgTQ1n6HVwtNzfJ+XCjt+bUM9LZ6cF0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767852506; c=relaxed/simple; bh=GDS2hOEC3ZDMsbfoCk7m1oWy+PAW91PnnU7hk34o6d0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XtLvwlKHrHDJP85xpgamVjL77ebJnOWaK8pNKbb8Do87cwShwNvRitedTUtm4Myqp2P4fvPlHf0jJFTZA9DcoZezdlVDdX2UoX+HG9OrVckx8eAiCJ+5ArDytDK6LS352q2BEzaLRsu/EidQW1qyXiHRL5A3u4yZwFNHs06xpqY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=g2/gf8aC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="g2/gf8aC" Received: by smtp.kernel.org (Postfix) with ESMTPS id DAA23C116D0; Thu, 8 Jan 2026 06:08:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1767852505; bh=GDS2hOEC3ZDMsbfoCk7m1oWy+PAW91PnnU7hk34o6d0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=g2/gf8aCpIoiwtoZzo6kjKyluMeMzlAmbMWxqU5H45oGHsLwPFi1bXqbbBv7wvEp2 ZuC+1hFUyuZqR04SsB7XQC6fouSQM/Aoiv3RX3M5liC7F2CJzEFdFXA71ytJiV6dsb XG/+XDSQ7TvmhCPi/ZmuIJrAbZn2QkR/Zt/4VqOVKFXkyMfGKjIgjr0oTcxUVM5K4c S4TiDBLTMxkkLs4BbR3u2UcuFmxQeucaODYy86F8tv3ZjNxU1M0+rE/HeUeXuQvz3F 9cNeKFqLfRrNdss9UIrAjwgFMq1YimHyvEPtLNHVgyJ5qdr8b0ybifRvSKUwjUVkT+ uNyfh5jF2rv8w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C997DD1489E; Thu, 8 Jan 2026 06:08:25 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Thu, 08 Jan 2026 14:08:16 +0800 Subject: [PATCH v5 2/8] dt-bindings: clock: Add Amlogic A5 PLL clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260108-a5-clk-v5-2-9a69fc1ef00a@amlogic.com> References: <20260108-a5-clk-v5-0-9a69fc1ef00a@amlogic.com> In-Reply-To: <20260108-a5-clk-v5-0-9a69fc1ef00a@amlogic.com> To: Chuan Liu , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Xianwei Zhao , Kevin Hilman , Martin Blumenstingl Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767852503; l=3306; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=L2WtYBPXP83bh/la2DnEiOjTXuQi8+YFfWCWfb93CxI=; b=lWjjGLzJcwiOSvSxEqkuF0rhfMHSu9w8NIQtylMNMhiR1/oifwNvWmxU3pH3t/PZPKVCIcoWy aC9OG55TkCbB/2pJ8rRjhKDXnhNnkIeAfj0ZoDH2RdXP5TijWIF4Q1s X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add the PLL clock controller dt-bindings for the Amlogic A5 SoC family. Co-developed-by: Xianwei Zhao Signed-off-by: Xianwei Zhao Signed-off-by: Chuan Liu Reviewed-by: Rob Herring (Arm) --- .../bindings/clock/amlogic,a5-pll-clkc.yaml | 63 ++++++++++++++++++= ++++ include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 +++++++++ 2 files changed, 87 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic,a5-pll-clkc.ya= ml b/Documentation/devicetree/bindings/clock/amlogic,a5-pll-clkc.yaml new file mode 100644 index 000000000000..d74570a90926 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,a5-pll-clkc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2024 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,a5-pll-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic A5 series PLL Clock Controller + +maintainers: + - Chuan Liu + - Xianwei Zhao + +properties: + compatible: + const: amlogic,a5-pll-clkc + + reg: + maxItems: 1 + + clocks: + items: + - description: input oscillator + - description: input fix pll dco + - description: input fix pll + + clock-names: + items: + - const: xtal + - const: fix_dco + - const: fix + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include + apb { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@8000 { + compatible =3D "amlogic,a5-pll-clkc"; + reg =3D <0x0 0x8000 0x0 0x1a4>; + clocks =3D <&xtal>, + <&scmi_clk CLKID_FIXED_PLL_DCO>, + <&scmi_clk CLKID_FIXED_PLL>; + clock-names =3D "xtal", + "fix_dco", + "fix"; + #clock-cells =3D <1>; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,a5-pll-clkc.h b/include/dt-b= indings/clock/amlogic,a5-pll-clkc.h new file mode 100644 index 000000000000..a74c448a8d8a --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a5-pll-clkc.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu + */ + +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_A5_PLL_CLKC_H +#define _DT_BINDINGS_CLOCK_AMLOGIC_A5_PLL_CLKC_H + +#define CLKID_MPLL_PREDIV 0 +#define CLKID_MPLL0_DIV 1 +#define CLKID_MPLL0 2 +#define CLKID_MPLL1_DIV 3 +#define CLKID_MPLL1 4 +#define CLKID_MPLL2_DIV 5 +#define CLKID_MPLL2 6 +#define CLKID_MPLL3_DIV 7 +#define CLKID_MPLL3 8 +#define CLKID_GP0_PLL_DCO 9 +#define CLKID_GP0_PLL 10 +#define CLKID_HIFI_PLL_DCO 11 +#define CLKID_HIFI_PLL 12 + +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_A5_PLL_CLKC_H */ --=20 2.42.0