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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jan 2026 17:45:40.4781 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0b94e537-2c27-453e-e86b-08de4e149301 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.194];Helo=[lewvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004684.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLAPR10MB5107 Content-Type: text/plain; charset="utf-8" TI's AM62P SoC contains two instances of the TI Keystone Display SubSystem (DSS), each with two video ports and two video planes. These instances support up to three independent video streams through OLDI, DPI, and DSI interfaces. DSS0 (first instance) supports: - Two OLDI transmitters on video port 1, configurable in dual-link or single-link mode. - DPI output on video port 2. DSS1 (second instance) supports: - One OLDI transmitter on video port 1 (single-link mode only). - DSI controller output on video port 2. The two OLDI transmitters can be configured in clone mode to drive a pair of identical OLDI single-link displays. DPI outputs from DSS0 VP2, DSS1 VP1, and DSS1 VP2 are multiplexed, allowing only one DPI output at a time. Add the compatible string "ti,am62p-dss" and update related description accordingly. AM62P has different power domains for DSS and OLDI compared to other Keystone SoCs. Therefore, add 'minItems' and set to 1 and 'maxItems' field in the power-domains property to 3 for the "ti,am62p-dss" compatible entry to reflect this hardware difference. Signed-off-by: Swamil Jain --- .../bindings/display/ti/ti,am65x-dss.yaml | 33 ++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml= b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index 38fcee91211e..e74e710934fc 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -24,6 +24,19 @@ description: | DPI signals are also routed internally to DSI Tx controller present with= in the SoC. Due to clocking limitations only one of the interface i.e. either D= SI or DPI can be used at once. + The AM62P has two instances of TI Keystone Display SubSystem, each with = two + video ports and two video planes. These instances can support up to 3 + independent video streams through OLDI, DPI, and DSI interfaces. + DSS0 (first instance) supports: + - Two OLDI TXes on video port 1, configurable in dual-link or + single link clone mode + - DPI output on video port 2 + DSS1 (second instance) supports: + - One OLDI TX on video port 1 (single-link mode only) + - DSI controller output on video port 2 + The two OLDI TXes can be configured in clone mode to drive a pair of + identical OLDI single-link displays. DPI outputs from DSS0 VP2, DSS1 VP1, + and DSS1 VP2 are muxed, allowing only one DPI output at a time. =20 properties: compatible: @@ -31,6 +44,7 @@ properties: - ti,am625-dss - ti,am62a7-dss - ti,am62l-dss + - ti,am62p-dss - ti,am65x-dss =20 reg: @@ -81,7 +95,8 @@ properties: maxItems: 1 =20 power-domains: - maxItems: 1 + minItems: 1 + maxItems: 3 description: phandle to the associated power domain =20 dma-coherent: true @@ -196,6 +211,22 @@ allOf: properties: endpoint@1: false =20 + - if: + properties: + compatible: + contains: + const: ti,am62p-dss + then: + properties: + power-domains: + minItems: 1 + maxItems: 3 + else: + properties: + power-domains: + minItems: 1 + maxItems: 1 + required: - compatible - reg From nobody Sun Feb 8 09:23:01 2026 Received: from CH5PR02CU005.outbound.protection.outlook.com (mail-northcentralusazon11012033.outbound.protection.outlook.com [40.107.200.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CB29338596; 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jan 2026 17:45:46.5681 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f2f60222-10f4-4a1f-e0ac-08de4e1496a1 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075EF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN0PR10MB4918 Content-Type: text/plain; charset="utf-8" From: Devarsh Thakkar Some SoC's such as AM62P have dedicated power domains for OLDI which need to be powered on separately along with display controller. So during driver probe, power up all attached PM domains enumerated in devicetree node for DSS. This also prepares base to add display support for AM62P. Signed-off-by: Devarsh Thakkar [j-choudhary@ti.com: fix PM call sequence causing kernel crash in OLDI] Signed-off-by: Jayesh Choudhary Signed-off-by: Swamil Jain Tested-by: Michael Walle # on am67a --- drivers/gpu/drm/tidss/tidss_drv.c | 83 +++++++++++++++++++++++++++++-- drivers/gpu/drm/tidss/tidss_drv.h | 4 ++ 2 files changed, 83 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_drv.c b/drivers/gpu/drm/tidss/tids= s_drv.c index 1c8cc18bc53c..33a10fba4325 100644 --- a/drivers/gpu/drm/tidss/tidss_drv.c +++ b/drivers/gpu/drm/tidss/tidss_drv.c @@ -8,6 +8,7 @@ #include #include #include +#include #include =20 #include @@ -107,6 +108,68 @@ static const struct drm_driver tidss_driver =3D { .minor =3D 0, }; =20 +static int tidss_detach_pm_domains(struct tidss_device *tidss) +{ + int i; + + if (tidss->num_domains <=3D 1) + return 0; + + for (i =3D 0; i < tidss->num_domains; i++) { + if (!IS_ERR_OR_NULL(tidss->pd_link[i])) + device_link_del(tidss->pd_link[i]); + if (!IS_ERR_OR_NULL(tidss->pd_dev[i])) + dev_pm_domain_detach(tidss->pd_dev[i], true); + tidss->pd_dev[i] =3D NULL; + tidss->pd_link[i] =3D NULL; + } + + return 0; +} + +static int tidss_attach_pm_domains(struct tidss_device *tidss) +{ + struct device *dev =3D tidss->dev; + int i; + int ret; + struct platform_device *pdev =3D to_platform_device(dev); + struct device_node *np =3D pdev->dev.of_node; + + tidss->num_domains =3D of_count_phandle_with_args(np, "power-domains", + "#power-domain-cells"); + + tidss->pd_dev =3D devm_kmalloc_array(dev, tidss->num_domains, + sizeof(*tidss->pd_dev), GFP_KERNEL); + if (!tidss->pd_dev) + return -ENOMEM; + + tidss->pd_link =3D devm_kmalloc_array(dev, tidss->num_domains, + sizeof(*tidss->pd_link), GFP_KERNEL); + if (!tidss->pd_link) + return -ENOMEM; + + for (i =3D 0; i < tidss->num_domains; i++) { + tidss->pd_dev[i] =3D dev_pm_domain_attach_by_id(dev, i); + if (IS_ERR(tidss->pd_dev[i])) { + ret =3D PTR_ERR(tidss->pd_dev[i]); + goto fail; + } + + tidss->pd_link[i] =3D device_link_add(dev, tidss->pd_dev[i], + DL_FLAG_STATELESS | + DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); + if (!tidss->pd_link[i]) { + ret =3D -EINVAL; + goto fail; + } + } + + return 0; +fail: + tidss_detach_pm_domains(tidss); + return ret; +} + static int tidss_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -129,15 +192,21 @@ static int tidss_probe(struct platform_device *pdev) =20 spin_lock_init(&tidss->irq_lock); =20 + ret =3D tidss_attach_pm_domains(tidss); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to attach power domains\n"); + ret =3D dispc_init(tidss); if (ret) { - dev_err(dev, "failed to initialize dispc: %d\n", ret); - return ret; + dev_err_probe(dev, ret, "failed to initialize dispc\n"); + goto err_detach_pm_domains; } =20 ret =3D tidss_oldi_init(tidss); - if (ret) - return dev_err_probe(dev, ret, "failed to init OLDI\n"); + if (ret) { + dev_err_probe(dev, ret, "failed to init OLDI\n"); + goto err_oldi_deinit; + } =20 pm_runtime_enable(dev); =20 @@ -203,8 +272,12 @@ static int tidss_probe(struct platform_device *pdev) pm_runtime_dont_use_autosuspend(dev); pm_runtime_disable(dev); =20 +err_oldi_deinit: tidss_oldi_deinit(tidss); =20 +err_detach_pm_domains: + tidss_detach_pm_domains(tidss); + return ret; } =20 @@ -232,6 +305,8 @@ static void tidss_remove(struct platform_device *pdev) /* devm allocated dispc goes away with the dev so mark it NULL */ dispc_remove(tidss); =20 + tidss_detach_pm_domains(tidss); + dev_dbg(dev, "%s done\n", __func__); } =20 diff --git a/drivers/gpu/drm/tidss/tidss_drv.h b/drivers/gpu/drm/tidss/tids= s_drv.h index e1c1f41d8b4b..6625b989b815 100644 --- a/drivers/gpu/drm/tidss/tidss_drv.h +++ b/drivers/gpu/drm/tidss/tidss_drv.h @@ -41,6 +41,10 @@ struct tidss_device { /* protects the irq masks field and irqenable/irqstatus registers */ spinlock_t irq_lock; dispc_irq_t irq_mask; /* enabled irqs */ + + int num_domains; /* Count of PM domains to be handled */ + struct device **pd_dev; + struct device_link **pd_link; }; =20 #define to_tidss(__dev) container_of(__dev, struct tidss_device, ddev) From nobody Sun Feb 8 09:23:01 2026 Received: from CY7PR03CU001.outbound.protection.outlook.com (mail-westcentralusazon11010034.outbound.protection.outlook.com [40.93.198.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0705134BA5A; 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jan 2026 17:45:55.8131 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf1d711a-1bd2-4a7a-9d02-08de4e149c27 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.194];Helo=[lewvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B36F.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR10MB7402 Content-Type: text/plain; charset="utf-8" The DSS controller on TI's AM62P SoC features two instances of the TI DSS. Each DSS instance supports two video ports, similar to the DSS controller found on the TI AM62X SoC. This allows three independent video streams to be supported: OLDI, DPI, and DSI. Since the DSS instances on AM62P are architecturally similar to those on the AM62X DSS controller, the existing dispc_am625_feats configuration can be reused for the AM62P DSS support. This patch adds the necessary device tree compatibility entry for "ti,am62p-dss" in the tidss driver, pointing to dispc_am625_feats, thereby enabling DSS support on AM62P devices. Reviewed-by: Tomi Valkeinen Signed-off-by: Swamil Jain --- drivers/gpu/drm/tidss/tidss_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/tidss/tidss_drv.c b/drivers/gpu/drm/tidss/tids= s_drv.c index 33a10fba4325..0c6087adee2c 100644 --- a/drivers/gpu/drm/tidss/tidss_drv.c +++ b/drivers/gpu/drm/tidss/tidss_drv.c @@ -320,6 +320,7 @@ static const struct of_device_id tidss_of_table[] =3D { { .compatible =3D "ti,am625-dss", .data =3D &dispc_am625_feats, }, { .compatible =3D "ti,am62a7-dss", .data =3D &dispc_am62a7_feats, }, { .compatible =3D "ti,am62l-dss", .data =3D &dispc_am62l_feats, }, + { .compatible =3D "ti,am62p-dss", .data =3D &dispc_am625_feats, }, { .compatible =3D "ti,am65x-dss", .data =3D &dispc_am65x_feats, }, { .compatible =3D "ti,j721e-dss", .data =3D &dispc_j721e_feats, }, { }