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Wed, 7 Jan 2026 06:27:07 -0800 From: Kartik Rajput To: , , , , , , , , , CC: Kartik Rajput Subject: [PATCH v5 4/4] i2c: tegra: Add support for Tegra410 Date: Wed, 7 Jan 2026 19:56:49 +0530 Message-ID: <20260107142649.14917-5-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260107142649.14917-1-kkartik@nvidia.com> References: <20260107142649.14917-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD6:EE_|LV2PR12MB5944:EE_ X-MS-Office365-Filtering-Correlation-Id: 23b0dad8-8375-439d-928b-08de4df8e206 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?aTnkN1Zp1bLee152E1fT2p50A9V7zVdPfmB29Ij6Aqw4U1Rn9HP9G7LOeBZl?= =?us-ascii?Q?QvScbBtaI0iDKj5znca1j2szN4wMlo6rsaxE7E3Oy3aKP2XOZjiz1xMz76Ak?= =?us-ascii?Q?A7v1udlUTXZOPGKGAbikPAy8NpWUOZ2MNux3jkDym1lK9rmAAzLeCTiHgd/m?= =?us-ascii?Q?2RpmLxUfgd7qyWbU1FVZNFSzOTKNbW9HEVTLgw43YxkmRWx4j6m2jmJW/f6J?= =?us-ascii?Q?ui9rS/xuYjeqmKHCcfRrZtMDWL8kS9ble2AgHpEGZrJ8IFJPL/1RCI05FTf6?= =?us-ascii?Q?1aOK2n4uLzpWVni7vYkEvGsDukWDo0ZuBba9Q1IbwalrkwTRqgRGCyi0vhFg?= =?us-ascii?Q?dFF2hBA8HuosvxU1sry1YfcdX/8HhTUZjUcdwMXnWtsQh5Lmjvvt2CI8Z1L/?= =?us-ascii?Q?7rn/yhr/UT5GeVQQD8GYaGQvjv8VHeJKUfqS/R/wz5hdKK9IBye9YcgBMn7m?= =?us-ascii?Q?i+nocvu5gtu97KSn26W0qFmTg9PUD6b5rFXL++udCJcemqFX1lJCurlL/8ix?= =?us-ascii?Q?zmq6rx0PuchF7Balp4ikPw89iocmUT1AdTybMybX3zJy6doDvhrUHxPy9Dpv?= =?us-ascii?Q?59KsahwKQt+TUw6Xbx4/byL3etyfur7KRPQ5jh6lAEyS71Z21eTc9BPM/3Af?= =?us-ascii?Q?zThspi0rLBCcCMmwQQ5I70rN6TvZEg8rEL/cJ+9MfG5VcnjteVIl9KyRtcrg?= =?us-ascii?Q?HCGFPwEW0y6uU0y0NNUCTVLUNSMz+P5mtNwAzVLIKWzB6DH6xtfw83hTIvWa?= =?us-ascii?Q?l/doEZ6tqDpVm3/vYBh7iu4o1Nx4fkB5qXckxbu4LmY0nnVhrtCL2B/8xzNK?= =?us-ascii?Q?1aGWwoAQGWTr5iaGTLoF3hJ/G4B3qMvhBUL7+N1R8VYlFL4Qf/roaFq0pG7s?= =?us-ascii?Q?JteGLgqVUB1SHjxfmO3BKijKU94yRtFluQoZSYmHJPJOWpDZuS+gBRfj7ao+?= =?us-ascii?Q?3mZViW96XxEPnx0VLcN6MFih6+5btq3EuLS0bbEs8syTRa/Eea6T7P7jKcT2?= =?us-ascii?Q?ini0sQ3Noe+e7Bnujb1QosKEKUCO05BbsXlt6CYzQ4hi/SvwZ/tDSw9L1qKb?= =?us-ascii?Q?qVfnM3Cw+VNUJ/9rxvepfh84D/7H54rOqt4d4MCzeG7LuHTCG8/t81ib5kHA?= =?us-ascii?Q?PvLUgvMmoywlrk4Zg114wEui2tb9SNKFFbLHSqkycNb5KNjg6k/po5usUle8?= =?us-ascii?Q?JT9XrHhv+uOQNw92QQ54ix6T0V0onlOOQIYljy6xGF/IqxMMWdZ3eG6g+RSk?= =?us-ascii?Q?2GdTRK2A9dg15bGSU1iBqrLXLVQSOIiit29BZJzvKdRNwKK4cUmFiZK6Dzk8?= =?us-ascii?Q?7Ojs62h3i8Dc+loPJnETVtgl1upOuHlllzhSmQ3hMNxdMp8K5d6pCn8ABxjb?= =?us-ascii?Q?zeSvolV4WFXJ1+WFhlf5wDwa2jLxNnPN01uu4+UVqkTe7i6TBlbTdfwTblmD?= =?us-ascii?Q?b+yGpYAvRZAb45bECjbD7phgKjKsG1+bDoQJ15m3qhfASTkD+imtMEuPPjpx?= =?us-ascii?Q?4/Sc5LcewAkBhdsnbgwdUhR3lIRyN6KRo+DIvRPI/hVmEyAeFSLThp77JEQO?= =?us-ascii?Q?WalRu0u23186enuh9ySYjOqvjGThlozpK7Ru9xua?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jan 2026 14:27:27.1476 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 23b0dad8-8375-439d-928b-08de4df8e206 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5944 Content-Type: text/plain; charset="utf-8" Add support for the Tegra410 SoC, which has 4 I2C controllers. The controllers are feature-equivalent to Tegra264; only the register offsets differ. Signed-off-by: Kartik Rajput --- Changes in v3: * Updated timing parameters for Tegra410. --- drivers/i2c/busses/i2c-tegra.c | 64 ++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 821e7627e56e..44afef32d656 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -280,6 +280,35 @@ static const struct tegra_i2c_regs tegra264_i2c_regs = =3D { .sw_mutex =3D 0x0ec, }; =20 +static const struct tegra_i2c_regs tegra410_i2c_regs =3D { + .cnfg =3D 0x000, + .status =3D 0x01c, + .sl_cnfg =3D 0x020, + .sl_addr1 =3D 0x02c, + .sl_addr2 =3D 0x030, + .tlow_sext =3D 0x034, + .tx_fifo =3D 0x054, + .rx_fifo =3D 0x058, + .packet_transfer_status =3D 0x05c, + .fifo_control =3D 0x060, + .fifo_status =3D 0x064, + .int_mask =3D 0x068, + .int_status =3D 0x06c, + .clk_divisor =3D 0x070, + .bus_clear_cnfg =3D 0x088, + .bus_clear_status =3D 0x08c, + .config_load =3D 0x090, + .clken_override =3D 0x094, + .interface_timing_0 =3D 0x098, + .interface_timing_1 =3D 0x09c, + .hs_interface_timing_0 =3D 0x0a0, + .hs_interface_timing_1 =3D 0x0a4, + .master_reset_cntrl =3D 0x0ac, + .mst_fifo_control =3D 0x0b8, + .mst_fifo_status =3D 0x0bc, + .sw_mutex =3D 0x0f0, +}; + /* * msg_end_type: The bus control which needs to be sent at end of transfer. * @MSG_END_STOP: Send stop pulse. @@ -2081,6 +2110,40 @@ static const struct tegra_i2c_hw_feature tegra264_i2= c_hw =3D { .regs =3D &tegra264_i2c_regs, }; =20 +static const struct tegra_i2c_hw_feature tegra410_i2c_hw =3D { + .has_continue_xfer_support =3D true, + .has_per_pkt_xfer_complete_irq =3D true, + .clk_divisor_hs_mode =3D 1, + .clk_divisor_std_mode =3D 0x3f, + .clk_divisor_fast_mode =3D 0x2c, + .clk_divisor_fast_plus_mode =3D 0x11, + .has_config_load_reg =3D true, + .has_multi_master_mode =3D true, + .has_slcg_override_reg =3D true, + .has_mst_fifo =3D true, + .has_mst_reset =3D true, + .quirks =3D &tegra194_i2c_quirks, + .supports_bus_clear =3D true, + .has_apb_dma =3D false, + .tlow_std_mode =3D 0x8, + .thigh_std_mode =3D 0x7, + .tlow_fast_mode =3D 0x2, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x2, + .thigh_fastplus_mode =3D 0x2, + .tlow_hs_mode =3D 0x8, + .thigh_hs_mode =3D 0x6, + .setup_hold_time_std_mode =3D 0x08080808, + .setup_hold_time_fast_mode =3D 0x02020202, + .setup_hold_time_fastplus_mode =3D 0x02020202, + .setup_hold_time_hs_mode =3D 0x0b0b0b, + .has_interface_timing_reg =3D true, + .enable_hs_mode_support =3D true, + .has_mutex =3D true, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, + .regs =3D &tegra410_i2c_regs, +}; + static const struct of_device_id tegra_i2c_of_match[] =3D { { .compatible =3D "nvidia,tegra264-i2c", .data =3D &tegra264_i2c_hw, }, { .compatible =3D "nvidia,tegra256-i2c", .data =3D &tegra256_i2c_hw, }, @@ -2391,6 +2454,7 @@ static const struct acpi_device_id tegra_i2c_acpi_mat= ch[] =3D { {.id =3D "NVDA0101", .driver_data =3D (kernel_ulong_t)&tegra210_i2c_hw}, {.id =3D "NVDA0201", .driver_data =3D (kernel_ulong_t)&tegra186_i2c_hw}, {.id =3D "NVDA0301", .driver_data =3D (kernel_ulong_t)&tegra194_i2c_hw}, + {.id =3D "NVDA2017", .driver_data =3D (kernel_ulong_t)&tegra410_i2c_hw}, { } }; MODULE_DEVICE_TABLE(acpi, tegra_i2c_acpi_match); --=20 2.43.0