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Wed, 7 Jan 2026 06:27:00 -0800 From: Kartik Rajput To: , , , , , , , , , CC: Kartik Rajput Subject: [PATCH v5 2/4] i2c: tegra: Move variant to tegra_i2c_hw_feature Date: Wed, 7 Jan 2026 19:56:47 +0530 Message-ID: <20260107142649.14917-3-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260107142649.14917-1-kkartik@nvidia.com> References: <20260107142649.14917-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD0:EE_|DM4PR12MB5867:EE_ X-MS-Office365-Filtering-Correlation-Id: 8cc24dc1-fb38-48d8-8b6a-08de4df8dd72 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?pYnrXFVo70ONXYZWYsbisweuVsmTyVXBLin46cGEnUlY/xTdDS7dgYgiDbW1?= =?us-ascii?Q?F7yDLY7HrbQBJwoiPZ4Woi/Swbka/b842b9U58OWVy8uAHMCFZlA2qguWFO1?= =?us-ascii?Q?lJjXk0MUJpjHARUueBNArwigq8l+04VC6qo5g8FoSGkeXtlVHW0EX/fnNbWD?= =?us-ascii?Q?GFb5H5ALPI2m/kEV0YUCznQjctjpI6aJrAhzvzp8MGkN8hCw0d5FLf2XKIeI?= =?us-ascii?Q?SNTTlCG7n7E7h4CvB5T6sTsqZ38K6OgYeOihzt18UjdIuA0dZpTeAVL+31qi?= =?us-ascii?Q?WfGvazHAfsRE/kQg+aXMIQ1YjWAZWk3GTVWj463/xU9TSXI+0hiLM9hGTs0k?= =?us-ascii?Q?SdGiZVZbRKhvB6e8UEzj/l9BxDaBRgjOh+uOHlfCiMQCON0+IJUP+MpnIrjF?= =?us-ascii?Q?C+JMbaqXruTyKpJ9k+DqC4MgcVRtT9UI887Ddf59PPYbmMYXXd52a35S6VMU?= =?us-ascii?Q?HTh8l2S58WaSSrV7eDN77Yksq8hLHva8O+q++0tv+UjPu3O3XKq/92sWAYc0?= =?us-ascii?Q?RnzSSd4RGkSmE9ANDa9tKUc8fCPnjvpK60zZ0CJS+xPBeX41GwhKWbYHaWkf?= =?us-ascii?Q?NdEtQvf7tkeZSLwo75Ax1TtSHBPYtNJQO4ThN//fRbnGJtOxI44ok7PMBDTg?= =?us-ascii?Q?CTBUBF1Puah5g4lQRFeYWSbTAfau4t6qRmpLc/oUhf1Jfi98qRklqoNoEABP?= =?us-ascii?Q?IYwvHykTLim/gbCW+fmTMt6ZbipU6H+nW1vJ0u9Xioi0/RKKpmGk4/MI8bT4?= =?us-ascii?Q?KvHJFug5eHxLWdLes8tA3unJRL3wW7o7PI3+AWKOpLND6NoaMaTPoRJLIyqK?= =?us-ascii?Q?Z2erypJeiZv9bH/Lm71A+pj/Eqq0MXX4FIvgK8CUba5F8jzKNP596tP9D+Z/?= =?us-ascii?Q?rAMHOz8ALspWIbHQyN26s0jFmRBt93jPAWtIuJ9LA9OyRZKzFkoRVDeimy1d?= =?us-ascii?Q?JicnciWY/mA0y1H4A89324Wfez36AKuFsHlfopiwlPnCSqxdOt8zbZFwl3gX?= =?us-ascii?Q?52fStP5pA8pShaxQshEgT0+mVb4DUF6lAbCr4NCCDp3bTWDZ9wd3m/yaGhM6?= =?us-ascii?Q?rkKnz5yGYEIYZGUlb45WvHoqrdJol02RQIOa+/MouIhGwUffA9HxO3hYl4Gd?= =?us-ascii?Q?FXTiYBruxFqmjEPUonUJzze7YUFgiQucSaDR8NLm7DWYYeSP0EUdpHnI69UB?= =?us-ascii?Q?xi93AMLt3x02nYdcMGahjUXLqz4nG4pUuirOi+dXQoM9bbjaO8j0oH0Tfs8q?= =?us-ascii?Q?JiIUceBlvIvE0g/1lZgiQ6quLU23pDOMNO+jEHFBpKOyCeE0pMZ/IoEhYZ0L?= =?us-ascii?Q?YPNpz9oKoaYHTVlKPDw3/ytzgAQJkPvJ+IthbOuFmDLhHr0DmyJylkiEcXCX?= =?us-ascii?Q?ZUXgTI+T1hoPksykMddjvL4ejXpd4olHBnOSAkcmhl3baoMvAc7ytkILUMBb?= =?us-ascii?Q?OmvsZ0qSO4EvfLOD36AA09wnvQgVeZvlwLrI9k5xXcUoAwTOmiP059YccgbO?= =?us-ascii?Q?2+Lp7ghJcemN74kfjeuOrcNs4LH4rHwgevOHiSBoaI6PbKDQxOyrbRgLwDcY?= =?us-ascii?Q?kfaZUD3sVExfvsQpAvSp4j+kDSZCHYc5A2GK4ows?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jan 2026 14:27:19.5228 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8cc24dc1-fb38-48d8-8b6a-08de4df8dd72 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5867 Content-Type: text/plain; charset="utf-8" Move the variant field into tegra_i2c_hw_feature and populate it for all SoCs. Add dedicated SoC data for "nvidia,tegra20-i2c-dvc" and "nvidia,tegra210-i2c-vi" compatibles. Drop the compatible-string checks from tegra_i2c_parse_dt to initialize the Tegra I2C variant. Signed-off-by: Kartik Rajput --- Changes in v5: * Updated commit message. Changes in v4: * Reverted the change to remove config checks from IS_DVC and IS_VI macros. --- drivers/i2c/busses/i2c-tegra.c | 98 ++++++++++++++++++++++++++++------ 1 file changed, 81 insertions(+), 17 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 9a09079dcc9c..cb6455fb3ee1 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -235,6 +235,7 @@ enum tegra_i2c_variant { * timing settings. * @enable_hs_mode_support: Enable support for high speed (HS) mode transf= ers. * @has_mutex: Has mutex register for mutual exclusion with other firmware= s or VMs. + * @variant: This represents the I2C controller variant. */ struct tegra_i2c_hw_feature { bool has_continue_xfer_support; @@ -266,6 +267,7 @@ struct tegra_i2c_hw_feature { bool has_interface_timing_reg; bool enable_hs_mode_support; bool has_mutex; + enum tegra_i2c_variant variant; }; =20 /** @@ -281,7 +283,6 @@ struct tegra_i2c_hw_feature { * @base_phys: physical base address of the I2C controller * @cont_id: I2C controller ID, used for packet header * @irq: IRQ number of transfer complete interrupt - * @variant: This represents the I2C controller variant. * @msg_complete: transfer completion notifier * @msg_buf_remaining: size of unsent data in the message buffer * @msg_len: length of message in current transfer @@ -334,13 +335,12 @@ struct tegra_i2c_dev { bool atomic_mode; bool dma_mode; bool msg_read; - enum tegra_i2c_variant variant; }; =20 #define IS_DVC(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && \ - (dev)->variant =3D=3D TEGRA_I2C_VARIANT_DVC) + (dev)->hw->variant =3D=3D TEGRA_I2C_VARIANT_DVC) #define IS_VI(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && \ - (dev)->variant =3D=3D TEGRA_I2C_VARIANT_VI) + (dev)->hw->variant =3D=3D TEGRA_I2C_VARIANT_VI) =20 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg) @@ -1649,8 +1649,42 @@ static const struct tegra_i2c_hw_feature tegra20_i2c= _hw =3D { .has_interface_timing_reg =3D false, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 +#if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) +static const struct tegra_i2c_hw_feature tegra20_dvc_i2c_hw =3D { + .has_continue_xfer_support =3D false, + .has_per_pkt_xfer_complete_irq =3D false, + .clk_divisor_hs_mode =3D 3, + .clk_divisor_std_mode =3D 0, + .clk_divisor_fast_mode =3D 0, + .clk_divisor_fast_plus_mode =3D 0, + .has_config_load_reg =3D false, + .has_multi_master_mode =3D false, + .has_slcg_override_reg =3D false, + .has_mst_fifo =3D false, + .has_mst_reset =3D false, + .quirks =3D &tegra_i2c_quirks, + .supports_bus_clear =3D false, + .has_apb_dma =3D true, + .tlow_std_mode =3D 0x4, + .thigh_std_mode =3D 0x2, + .tlow_fast_mode =3D 0x4, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x4, + .thigh_fastplus_mode =3D 0x2, + .setup_hold_time_std_mode =3D 0x0, + .setup_hold_time_fast_mode =3D 0x0, + .setup_hold_time_fastplus_mode =3D 0x0, + .setup_hold_time_hs_mode =3D 0x0, + .has_interface_timing_reg =3D false, + .enable_hs_mode_support =3D false, + .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DVC, +}; +#endif + static const struct tegra_i2c_hw_feature tegra30_i2c_hw =3D { .has_continue_xfer_support =3D true, .has_per_pkt_xfer_complete_irq =3D false, @@ -1679,6 +1713,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_= hw =3D { .has_interface_timing_reg =3D false, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra114_i2c_hw =3D { @@ -1709,6 +1744,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c= _hw =3D { .has_interface_timing_reg =3D false, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra124_i2c_hw =3D { @@ -1739,6 +1775,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra210_i2c_hw =3D { @@ -1769,8 +1806,42 @@ static const struct tegra_i2c_hw_feature tegra210_i2= c_hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 +#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) +static const struct tegra_i2c_hw_feature tegra210_vi_i2c_hw =3D { + .has_continue_xfer_support =3D true, + .has_per_pkt_xfer_complete_irq =3D true, + .clk_divisor_hs_mode =3D 1, + .clk_divisor_std_mode =3D 0x19, + .clk_divisor_fast_mode =3D 0x19, + .clk_divisor_fast_plus_mode =3D 0x10, + .has_config_load_reg =3D true, + .has_multi_master_mode =3D false, + .has_slcg_override_reg =3D true, + .has_mst_fifo =3D false, + .has_mst_reset =3D false, + .quirks =3D &tegra_i2c_quirks, + .supports_bus_clear =3D true, + .has_apb_dma =3D true, + .tlow_std_mode =3D 0x4, + .thigh_std_mode =3D 0x2, + .tlow_fast_mode =3D 0x4, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x4, + .thigh_fastplus_mode =3D 0x2, + .setup_hold_time_std_mode =3D 0, + .setup_hold_time_fast_mode =3D 0, + .setup_hold_time_fastplus_mode =3D 0, + .setup_hold_time_hs_mode =3D 0, + .has_interface_timing_reg =3D true, + .enable_hs_mode_support =3D false, + .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_VI, +}; +#endif + static const struct tegra_i2c_hw_feature tegra186_i2c_hw =3D { .has_continue_xfer_support =3D true, .has_per_pkt_xfer_complete_irq =3D true, @@ -1799,6 +1870,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra194_i2c_hw =3D { @@ -1831,6 +1903,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D true, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra256_i2c_hw =3D { @@ -1863,6 +1936,7 @@ static const struct tegra_i2c_hw_feature tegra256_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D true, .has_mutex =3D true, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra264_i2c_hw =3D { @@ -1895,6 +1969,7 @@ static const struct tegra_i2c_hw_feature tegra264_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D true, .has_mutex =3D true, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct of_device_id tegra_i2c_of_match[] =3D { @@ -1903,7 +1978,7 @@ static const struct of_device_id tegra_i2c_of_match[]= =3D { { .compatible =3D "nvidia,tegra194-i2c", .data =3D &tegra194_i2c_hw, }, { .compatible =3D "nvidia,tegra186-i2c", .data =3D &tegra186_i2c_hw, }, #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) - { .compatible =3D "nvidia,tegra210-i2c-vi", .data =3D &tegra210_i2c_hw, }, + { .compatible =3D "nvidia,tegra210-i2c-vi", .data =3D &tegra210_vi_i2c_hw= , }, #endif { .compatible =3D "nvidia,tegra210-i2c", .data =3D &tegra210_i2c_hw, }, { .compatible =3D "nvidia,tegra124-i2c", .data =3D &tegra124_i2c_hw, }, @@ -1911,7 +1986,7 @@ static const struct of_device_id tegra_i2c_of_match[]= =3D { { .compatible =3D "nvidia,tegra30-i2c", .data =3D &tegra30_i2c_hw, }, { .compatible =3D "nvidia,tegra20-i2c", .data =3D &tegra20_i2c_hw, }, #if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) - { .compatible =3D "nvidia,tegra20-i2c-dvc", .data =3D &tegra20_i2c_hw, }, + { .compatible =3D "nvidia,tegra20-i2c-dvc", .data =3D &tegra20_dvc_i2c_hw= , }, #endif {}, }; @@ -1919,23 +1994,12 @@ MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); =20 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) { - struct device_node *np =3D i2c_dev->dev->of_node; bool multi_mode; =20 i2c_parse_fw_timings(i2c_dev->dev, &i2c_dev->timings, true); =20 multi_mode =3D device_property_read_bool(i2c_dev->dev, "multi-master"); i2c_dev->multimaster_mode =3D multi_mode; - - i2c_dev->variant =3D TEGRA_I2C_VARIANT_DEFAULT; - - if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && - of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc")) - i2c_dev->variant =3D TEGRA_I2C_VARIANT_DVC; - - if (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && - of_device_is_compatible(np, "nvidia,tegra210-i2c-vi")) - i2c_dev->variant =3D TEGRA_I2C_VARIANT_VI; } =20 static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev) --=20 2.43.0