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Miller" , Eric Dumazet , Jakub Kicinski , "Paolo Abeni" , Satananda Burla , "Abhijit Ayarekar" Subject: [PATCH net v3 1/3] octeon_ep: disable per ring interrupts Date: Wed, 7 Jan 2026 13:18:54 +0000 Message-ID: <20260107131857.3434352-2-vimleshk@marvell.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260107131857.3434352-1-vimleshk@marvell.com> References: <20260107131857.3434352-1-vimleshk@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 4Zggx9QfxoO52tEzBqQXZtQWSXesDyAj X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA3MDEwMiBTYWx0ZWRfX6MNz5A9Du/pN 1Lz9no9wQilq6phm0yRzwenpJmsSytpegYs9kEDBipYHHpl1GDMBnfXru1oMAyo7e2TzFZAUe1X 9INUeTAaGaK+KZ2hcOrfadUXFZ+T1vmYwzBbV8bgRCJrlMLcmVzLCxpf06LCi3RsAwaQ4dYUE2o Ap9xynD6jAP8Tz6KwmomzujRl06fNTEeRDP2+wfsONrpxej6g192Hr8STjg4cciWrnbg0Gkzr/L T25giQ9YX3lzEbfv+n8J3s4acOsKcWXCvEyoAxOkAVqG4A8p8wzZbUony0SUhq1kaKOnA2NV/nH sll+tNKp2w7s7piu4sqq2GWo2pdrdIOlul8FwT+xEUlntoXwcBkctz76XZ94tKiQJP5kgsD5ZHL a5vgRPWfqVPiZZeNl14HqSe8q4i7tvL1+Q9Xsnmg5XuGE3ZZvQfepLMobQxsBfa7GvGV0BvVp49 0yUNn/MnSHLVfqwDo8A== X-Authority-Analysis: v=2.4 cv=EOILElZC c=1 sm=1 tr=0 ts=695e5d50 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=vUbySO9Y5rIA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=M5GUcnROAAAA:8 a=BjJIY8cOur314jIlsncA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: 4Zggx9QfxoO52tEzBqQXZtQWSXesDyAj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-07_01,2026-01-06_01,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Disable the MSI-X per ring interrupt for every PF ring when PF netdev goes down. Fixes: 1f2c2d0cee023 ("octeon_ep: add hardware configuration APIs") Signed-off-by: Sathesh Edara Signed-off-by: Shinas Rasheed Signed-off-by: Vimlesh Kumar --- V3: - No change V2: https://lore.kernel.org/all/20251219100751.3063135-2-vimleshk@marvell.c= om/ V1: https://lore.kernel.org/all/20251212122304.2562229-2-vimleshk@marvell.c= om/ .../ethernet/marvell/octeon_ep/octep_cn9k_pf.c | 18 +++++++++++++++--- .../ethernet/marvell/octeon_ep/octep_cnxk_pf.c | 18 +++++++++++++++--- .../marvell/octeon_ep/octep_regs_cn9k_pf.h | 1 + .../marvell/octeon_ep/octep_regs_cnxk_pf.h | 1 + 4 files changed, 32 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c b/drive= rs/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c index b5805969404f..2574a6061e3d 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c @@ -696,14 +696,26 @@ static void octep_enable_interrupts_cn93_pf(struct oc= tep_device *oct) /* Disable all interrupts */ static void octep_disable_interrupts_cn93_pf(struct octep_device *oct) { - u64 intr_mask =3D 0ULL; + u64 reg_val, intr_mask =3D 0ULL; int srn, num_rings, i; =20 srn =3D CFG_GET_PORTS_PF_SRN(oct->conf); num_rings =3D CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); =20 - for (i =3D 0; i < num_rings; i++) - intr_mask |=3D (0x1ULL << (srn + i)); + for (i =3D 0; i < num_rings; i++) { + intr_mask |=3D (BIT_ULL(srn + i)); + reg_val =3D octep_read_csr64(oct, + CN93_SDP_R_IN_INT_LEVELS(srn + i)); + reg_val &=3D (~CN93_INT_ENA_BIT); + octep_write_csr64(oct, + CN93_SDP_R_IN_INT_LEVELS(srn + i), reg_val); + + reg_val =3D octep_read_csr64(oct, + CN93_SDP_R_OUT_INT_LEVELS(srn + i)); + reg_val &=3D (~CN93_INT_ENA_BIT); + octep_write_csr64(oct, + CN93_SDP_R_OUT_INT_LEVELS(srn + i), reg_val); + } =20 octep_write_csr64(oct, CN93_SDP_EPF_IRERR_RINT_ENA_W1C, intr_mask); octep_write_csr64(oct, CN93_SDP_EPF_ORERR_RINT_ENA_W1C, intr_mask); diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c b/drive= rs/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c index 5de0b5ecbc5f..73cd0ca758f0 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c @@ -720,14 +720,26 @@ static void octep_enable_interrupts_cnxk_pf(struct oc= tep_device *oct) /* Disable all interrupts */ static void octep_disable_interrupts_cnxk_pf(struct octep_device *oct) { - u64 intr_mask =3D 0ULL; + u64 reg_val, intr_mask =3D 0ULL; int srn, num_rings, i; =20 srn =3D CFG_GET_PORTS_PF_SRN(oct->conf); num_rings =3D CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); =20 - for (i =3D 0; i < num_rings; i++) - intr_mask |=3D (0x1ULL << (srn + i)); + for (i =3D 0; i < num_rings; i++) { + intr_mask |=3D BIT_ULL(srn + i); + reg_val =3D octep_read_csr64(oct, + CNXK_SDP_R_IN_INT_LEVELS(srn + i)); + reg_val &=3D (~CNXK_INT_ENA_BIT); + octep_write_csr64(oct, + CNXK_SDP_R_IN_INT_LEVELS(srn + i), reg_val); + + reg_val =3D octep_read_csr64(oct, + CNXK_SDP_R_OUT_INT_LEVELS(srn + i)); + reg_val &=3D (~CNXK_INT_ENA_BIT); + octep_write_csr64(oct, + CNXK_SDP_R_OUT_INT_LEVELS(srn + i), reg_val); + } =20 octep_write_csr64(oct, CNXK_SDP_EPF_IRERR_RINT_ENA_W1C, intr_mask); octep_write_csr64(oct, CNXK_SDP_EPF_ORERR_RINT_ENA_W1C, intr_mask); diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h b/= drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h index ca473502d7a0..42cb199bd085 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h @@ -386,5 +386,6 @@ #define CN93_PEM_BAR4_INDEX 7 #define CN93_PEM_BAR4_INDEX_SIZE 0x400000ULL #define CN93_PEM_BAR4_INDEX_OFFSET (CN93_PEM_BAR4_INDEX * CN93_PEM_BAR= 4_INDEX_SIZE) +#define CN93_INT_ENA_BIT (BIT_ULL(62)) =20 #endif /* _OCTEP_REGS_CN9K_PF_H_ */ diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h b/= drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h index e637d7c8224d..9eaadded9c50 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h @@ -412,5 +412,6 @@ #define CNXK_PEM_BAR4_INDEX 7 #define CNXK_PEM_BAR4_INDEX_SIZE 0x400000ULL #define CNXK_PEM_BAR4_INDEX_OFFSET (CNXK_PEM_BAR4_INDEX * CNXK_PEM_BAR4_IN= DEX_SIZE) +#define CNXK_INT_ENA_BIT (BIT_ULL(62)) =20 #endif /* _OCTEP_REGS_CNXK_PF_H_ */ --=20 2.47.0