From nobody Sat Feb 7 13:05:28 2026 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1470C328B5B; Wed, 7 Jan 2026 13:19:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767791964; cv=none; b=ChLNWY2LjbOu4+ubVUJKI6Nl8xkpzVLiq/yAu/GEysLnB2v6eb1tLhGDP1e90e0yunNOTf0gJP6O9b37CO1vEBwq1Ssp+xkM6kUBQVVIWqfQh9Yi8ymjYumcMHY4hE3ZfLqeAM7IDkQSPrcP5O+mVFiFHwLpZpWjBO4QhNan+8M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767791964; c=relaxed/simple; bh=gsKC0zaiIawdpqHIM2SJnRUt8D2667wj6rp34hRdTaI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QcTRzytlDy9QcpbumMpG0UsA7bSQaN/yeFcJR4gDHe72a1YG2+4K6fhPxLvaDA7oi4opJWRCLZ5+jYyKNvavKFCmeVyhOCZO0GKmTQsqjKmr3vFtuLwQXPPsunYVMj470cA/E6MbN6lxwGgAzOFLK7yUTk5IzgvuOW/9EGsT9Wg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=HTqDTlgu; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="HTqDTlgu" Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 607BjkvT2113136; Wed, 7 Jan 2026 05:19:12 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=I A4Z9AZGj6MgXH+XaiZrFZxX4YjzVClXqMqL5rUA8j0=; b=HTqDTlguZ5IvPx7cw Un0LGHukHgXpoUOEcy3406B3O9gLF3iqKVjNLuQSVpqvpeRTMq5daGsOY932FoYr skngZ3nZid44shDm7atAAfy3AUqsFMMrtaGn5POZVbfLuX3AN+qCy//vcm2fE5zf RF4mrd29vwZ8k6GphnnDYS4quwBmr9hht6nKbT+SbHNGeRGm//CFTeUBjXpgKgZk yewPxnpeCyS0izNj67sNLXiKV4dMwy+pcAPMtqtNNI8mtqtJ3q0n95munsxLDgZJ 1xW6dDbaZIiwKTb0ugIOu4+IUcQm0sJrizuAO0yIlwE15C3vePUrnGBX2JWQ2zR+ UlS5Q== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 4bhc3n1bcd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 07 Jan 2026 05:19:12 -0800 (PST) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Wed, 7 Jan 2026 05:19:11 -0800 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Wed, 7 Jan 2026 05:19:11 -0800 Received: from sapphire1.sclab.marvell.com (unknown [10.111.132.245]) by maili.marvell.com (Postfix) with ESMTP id B67933F704A; Wed, 7 Jan 2026 05:19:10 -0800 (PST) From: Vimlesh Kumar To: , CC: , , , "Vimlesh Kumar" , Veerasenareddy Burru , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , "Paolo Abeni" , Satananda Burla , "Abhijit Ayarekar" Subject: [PATCH net v3 1/3] octeon_ep: disable per ring interrupts Date: Wed, 7 Jan 2026 13:18:54 +0000 Message-ID: <20260107131857.3434352-2-vimleshk@marvell.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260107131857.3434352-1-vimleshk@marvell.com> References: <20260107131857.3434352-1-vimleshk@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 4Zggx9QfxoO52tEzBqQXZtQWSXesDyAj X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA3MDEwMiBTYWx0ZWRfX6MNz5A9Du/pN 1Lz9no9wQilq6phm0yRzwenpJmsSytpegYs9kEDBipYHHpl1GDMBnfXru1oMAyo7e2TzFZAUe1X 9INUeTAaGaK+KZ2hcOrfadUXFZ+T1vmYwzBbV8bgRCJrlMLcmVzLCxpf06LCi3RsAwaQ4dYUE2o Ap9xynD6jAP8Tz6KwmomzujRl06fNTEeRDP2+wfsONrpxej6g192Hr8STjg4cciWrnbg0Gkzr/L T25giQ9YX3lzEbfv+n8J3s4acOsKcWXCvEyoAxOkAVqG4A8p8wzZbUony0SUhq1kaKOnA2NV/nH sll+tNKp2w7s7piu4sqq2GWo2pdrdIOlul8FwT+xEUlntoXwcBkctz76XZ94tKiQJP5kgsD5ZHL a5vgRPWfqVPiZZeNl14HqSe8q4i7tvL1+Q9Xsnmg5XuGE3ZZvQfepLMobQxsBfa7GvGV0BvVp49 0yUNn/MnSHLVfqwDo8A== X-Authority-Analysis: v=2.4 cv=EOILElZC c=1 sm=1 tr=0 ts=695e5d50 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=vUbySO9Y5rIA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=M5GUcnROAAAA:8 a=BjJIY8cOur314jIlsncA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: 4Zggx9QfxoO52tEzBqQXZtQWSXesDyAj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-07_01,2026-01-06_01,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Disable the MSI-X per ring interrupt for every PF ring when PF netdev goes down. Fixes: 1f2c2d0cee023 ("octeon_ep: add hardware configuration APIs") Signed-off-by: Sathesh Edara Signed-off-by: Shinas Rasheed Signed-off-by: Vimlesh Kumar --- V3: - No change V2: https://lore.kernel.org/all/20251219100751.3063135-2-vimleshk@marvell.c= om/ V1: https://lore.kernel.org/all/20251212122304.2562229-2-vimleshk@marvell.c= om/ .../ethernet/marvell/octeon_ep/octep_cn9k_pf.c | 18 +++++++++++++++--- .../ethernet/marvell/octeon_ep/octep_cnxk_pf.c | 18 +++++++++++++++--- .../marvell/octeon_ep/octep_regs_cn9k_pf.h | 1 + .../marvell/octeon_ep/octep_regs_cnxk_pf.h | 1 + 4 files changed, 32 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c b/drive= rs/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c index b5805969404f..2574a6061e3d 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c @@ -696,14 +696,26 @@ static void octep_enable_interrupts_cn93_pf(struct oc= tep_device *oct) /* Disable all interrupts */ static void octep_disable_interrupts_cn93_pf(struct octep_device *oct) { - u64 intr_mask =3D 0ULL; + u64 reg_val, intr_mask =3D 0ULL; int srn, num_rings, i; =20 srn =3D CFG_GET_PORTS_PF_SRN(oct->conf); num_rings =3D CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); =20 - for (i =3D 0; i < num_rings; i++) - intr_mask |=3D (0x1ULL << (srn + i)); + for (i =3D 0; i < num_rings; i++) { + intr_mask |=3D (BIT_ULL(srn + i)); + reg_val =3D octep_read_csr64(oct, + CN93_SDP_R_IN_INT_LEVELS(srn + i)); + reg_val &=3D (~CN93_INT_ENA_BIT); + octep_write_csr64(oct, + CN93_SDP_R_IN_INT_LEVELS(srn + i), reg_val); + + reg_val =3D octep_read_csr64(oct, + CN93_SDP_R_OUT_INT_LEVELS(srn + i)); + reg_val &=3D (~CN93_INT_ENA_BIT); + octep_write_csr64(oct, + CN93_SDP_R_OUT_INT_LEVELS(srn + i), reg_val); + } =20 octep_write_csr64(oct, CN93_SDP_EPF_IRERR_RINT_ENA_W1C, intr_mask); octep_write_csr64(oct, CN93_SDP_EPF_ORERR_RINT_ENA_W1C, intr_mask); diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c b/drive= rs/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c index 5de0b5ecbc5f..73cd0ca758f0 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c @@ -720,14 +720,26 @@ static void octep_enable_interrupts_cnxk_pf(struct oc= tep_device *oct) /* Disable all interrupts */ static void octep_disable_interrupts_cnxk_pf(struct octep_device *oct) { - u64 intr_mask =3D 0ULL; + u64 reg_val, intr_mask =3D 0ULL; int srn, num_rings, i; =20 srn =3D CFG_GET_PORTS_PF_SRN(oct->conf); num_rings =3D CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); =20 - for (i =3D 0; i < num_rings; i++) - intr_mask |=3D (0x1ULL << (srn + i)); + for (i =3D 0; i < num_rings; i++) { + intr_mask |=3D BIT_ULL(srn + i); + reg_val =3D octep_read_csr64(oct, + CNXK_SDP_R_IN_INT_LEVELS(srn + i)); + reg_val &=3D (~CNXK_INT_ENA_BIT); + octep_write_csr64(oct, + CNXK_SDP_R_IN_INT_LEVELS(srn + i), reg_val); + + reg_val =3D octep_read_csr64(oct, + CNXK_SDP_R_OUT_INT_LEVELS(srn + i)); + reg_val &=3D (~CNXK_INT_ENA_BIT); + octep_write_csr64(oct, + CNXK_SDP_R_OUT_INT_LEVELS(srn + i), reg_val); + } =20 octep_write_csr64(oct, CNXK_SDP_EPF_IRERR_RINT_ENA_W1C, intr_mask); octep_write_csr64(oct, CNXK_SDP_EPF_ORERR_RINT_ENA_W1C, intr_mask); diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h b/= drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h index ca473502d7a0..42cb199bd085 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h @@ -386,5 +386,6 @@ #define CN93_PEM_BAR4_INDEX 7 #define CN93_PEM_BAR4_INDEX_SIZE 0x400000ULL #define CN93_PEM_BAR4_INDEX_OFFSET (CN93_PEM_BAR4_INDEX * CN93_PEM_BAR= 4_INDEX_SIZE) +#define CN93_INT_ENA_BIT (BIT_ULL(62)) =20 #endif /* _OCTEP_REGS_CN9K_PF_H_ */ diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h b/= drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h index e637d7c8224d..9eaadded9c50 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h @@ -412,5 +412,6 @@ #define CNXK_PEM_BAR4_INDEX 7 #define CNXK_PEM_BAR4_INDEX_SIZE 0x400000ULL #define CNXK_PEM_BAR4_INDEX_OFFSET (CNXK_PEM_BAR4_INDEX * CNXK_PEM_BAR4_IN= DEX_SIZE) +#define CNXK_INT_ENA_BIT (BIT_ULL(62)) =20 #endif /* _OCTEP_REGS_CNXK_PF_H_ */ --=20 2.47.0 From nobody Sat Feb 7 13:05:28 2026 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7DD2329392; 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Miller" , Eric Dumazet , Jakub Kicinski , "Paolo Abeni" Subject: [PATCH net v3 2/3] octeon_ep: ensure dbell BADDR updation Date: Wed, 7 Jan 2026 13:18:55 +0000 Message-ID: <20260107131857.3434352-3-vimleshk@marvell.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260107131857.3434352-1-vimleshk@marvell.com> References: <20260107131857.3434352-1-vimleshk@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: Lbylz-FJUTwfXSJwtUiDdtbH7IDaieXu X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA3MDEwMiBTYWx0ZWRfX3T/ibImXZpT2 bEwMWuJK6h28yA4kgMvYWDoCRKm8/reJZeh7105ekZcm7mXOjtnSGgzohMfj2Q08Th5FXQ1pOnD XAtPhH0jD59jWcFiO4ULwG2ZPTd5DJ2TWCMrj9b6HJSeoXXr+N+y1yIE0VZRv7THaDNtoGt4bdl 29GBi42bFgchuD2yDUmq3Ia3VtdT6hE68rb+d362aJIVUsmwMR5HV9GNk1K6bdL10+esNHHJ/d7 yOzlaijGecu1P7kxYR8yxyV+N//m8f/Ylrlb+l9fJPQbVkp204uDaAKtyOdKVC+3qXDvcHjQ+5Z wqEw/+BoLXlGfSIG8odZ62InV3NRUcKixdVh9vcQHsZUmq8+KRZsufOWOGe2psL3TQrQTTlxSem fhnbC+hoz4hgsFi6k+NT0JYp/+TviB3+hXAW7C6ynqZd9XGhk5uTXVMrj0RU7R/jXZ+qPO8EWMz IzX/WEk5Boy0oQ128vg== X-Authority-Analysis: v=2.4 cv=EOILElZC c=1 sm=1 tr=0 ts=695e5d53 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=vUbySO9Y5rIA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=M5GUcnROAAAA:8 a=HhD5TD71VMN5Ao0PvCkA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: Lbylz-FJUTwfXSJwtUiDdtbH7IDaieXu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-07_01,2026-01-06_01,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Make sure the OUT DBELL base address reflects the latest values written to it. Fix: Add a wait until the OUT DBELL base address register is updated with the DMA ring descriptor address, and modify the setup_oq function to properly handle failures. Fixes: 0807dc76f3bf5 ("octeon_ep: support Octeon CN10K devices") Signed-off-by: Sathesh Edara Signed-off-by: Shinas Rasheed Signed-off-by: Vimlesh Kumar --- V3: - Use reverse christmas tree order variable declaration. - Return error if timeout happens during setup oq. =20 V2: https://lore.kernel.org/all/20251219100751.3063135-3-vimleshk@marvell.c= om/ V1: https://lore.kernel.org/all/20251212122304.2562229-3-vimleshk@marvell.c= om/ .../marvell/octeon_ep/octep_cn9k_pf.c | 3 +- .../marvell/octeon_ep/octep_cnxk_pf.c | 46 +++++++++++++++---- .../ethernet/marvell/octeon_ep/octep_main.h | 2 +- .../net/ethernet/marvell/octeon_ep/octep_rx.c | 4 +- 4 files changed, 44 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c b/drive= rs/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c index 2574a6061e3d..2a5cebbf1ff8 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c @@ -307,7 +307,7 @@ static void octep_setup_iq_regs_cn93_pf(struct octep_de= vice *oct, int iq_no) } =20 /* Setup registers for a hardware Rx Queue */ -static void octep_setup_oq_regs_cn93_pf(struct octep_device *oct, int oq_n= o) +static int octep_setup_oq_regs_cn93_pf(struct octep_device *oct, int oq_no) { u64 reg_val; u64 oq_ctl =3D 0ULL; @@ -355,6 +355,7 @@ static void octep_setup_oq_regs_cn93_pf(struct octep_de= vice *oct, int oq_no) reg_val =3D ((u64)time_threshold << 32) | CFG_GET_OQ_INTR_PKT(oct->conf); octep_write_csr64(oct, CN93_SDP_R_OUT_INT_LEVELS(oq_no), reg_val); + return 0; } =20 /* Setup registers for a PF mailbox */ diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c b/drive= rs/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c index 73cd0ca758f0..8d17ff71507f 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c @@ -8,6 +8,7 @@ #include #include #include +#include =20 #include "octep_config.h" #include "octep_main.h" @@ -327,12 +328,14 @@ static void octep_setup_iq_regs_cnxk_pf(struct octep_= device *oct, int iq_no) } =20 /* Setup registers for a hardware Rx Queue */ -static void octep_setup_oq_regs_cnxk_pf(struct octep_device *oct, int oq_n= o) +static int octep_setup_oq_regs_cnxk_pf(struct octep_device *oct, int oq_no) { - u64 reg_val; - u64 oq_ctl =3D 0ULL; - u32 time_threshold =3D 0; struct octep_oq *oq =3D oct->oq[oq_no]; + unsigned long t_out_jiffies; + u32 time_threshold =3D 0; + u64 oq_ctl =3D 0ULL; + u64 reg_ba_val; + u64 reg_val; =20 oq_no +=3D CFG_GET_PORTS_PF_SRN(oct->conf); reg_val =3D octep_read_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no)); @@ -343,6 +346,36 @@ static void octep_setup_oq_regs_cnxk_pf(struct octep_d= evice *oct, int oq_no) reg_val =3D octep_read_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no)); } while (!(reg_val & CNXK_R_OUT_CTL_IDLE)); } + octep_write_csr64(oct, CNXK_SDP_R_OUT_WMARK(oq_no), oq->max_count); + /* Wait for WMARK to get applied */ + usleep_range(10, 15); + + octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(oq_no), + oq->desc_ring_dma); + octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_RSIZE(oq_no), + oq->max_count); + reg_ba_val =3D octep_read_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(oq_no)); + + if (reg_ba_val !=3D oq->desc_ring_dma) { + t_out_jiffies =3D jiffies + 10 * HZ; + do { + if (reg_ba_val =3D=3D ULLONG_MAX) + return -EFAULT; + octep_write_csr64(oct, + CNXK_SDP_R_OUT_SLIST_BADDR(oq_no), + oq->desc_ring_dma); + octep_write_csr64(oct, + CNXK_SDP_R_OUT_SLIST_RSIZE(oq_no), + oq->max_count); + reg_ba_val =3D + octep_read_csr64(oct, + CNXK_SDP_R_OUT_SLIST_BADDR(oq_no)); + } while ((reg_ba_val !=3D oq->desc_ring_dma) && + time_before(jiffies, t_out_jiffies)); + + if (reg_ba_val !=3D oq->desc_ring_dma) + return -EAGAIN; + } =20 reg_val &=3D ~(CNXK_R_OUT_CTL_IMODE); reg_val &=3D ~(CNXK_R_OUT_CTL_ROR_P); @@ -356,10 +389,6 @@ static void octep_setup_oq_regs_cnxk_pf(struct octep_d= evice *oct, int oq_no) reg_val |=3D (CNXK_R_OUT_CTL_ES_P); =20 octep_write_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no), reg_val); - octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_BADDR(oq_no), - oq->desc_ring_dma); - octep_write_csr64(oct, CNXK_SDP_R_OUT_SLIST_RSIZE(oq_no), - oq->max_count); =20 oq_ctl =3D octep_read_csr64(oct, CNXK_SDP_R_OUT_CONTROL(oq_no)); =20 @@ -385,6 +414,7 @@ static void octep_setup_oq_regs_cnxk_pf(struct octep_de= vice *oct, int oq_no) reg_val &=3D ~0xFFFFFFFFULL; reg_val |=3D CFG_GET_OQ_WMARK(oct->conf); octep_write_csr64(oct, CNXK_SDP_R_OUT_WMARK(oq_no), reg_val); + return 0; } =20 /* Setup registers for a PF mailbox */ diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_main.h b/drivers/= net/ethernet/marvell/octeon_ep/octep_main.h index 81ac4267811c..35d0ff289a70 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_main.h +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_main.h @@ -77,7 +77,7 @@ struct octep_pci_win_regs { =20 struct octep_hw_ops { void (*setup_iq_regs)(struct octep_device *oct, int q); - void (*setup_oq_regs)(struct octep_device *oct, int q); + int (*setup_oq_regs)(struct octep_device *oct, int q); void (*setup_mbox_regs)(struct octep_device *oct, int mbox); =20 irqreturn_t (*mbox_intr_handler)(void *ioq_vector); diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_rx.c b/drivers/ne= t/ethernet/marvell/octeon_ep/octep_rx.c index 82b6b19e76b4..1581cc468d74 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_rx.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_rx.c @@ -170,7 +170,9 @@ static int octep_setup_oq(struct octep_device *oct, int= q_no) goto oq_fill_buff_err; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Subject: [PATCH net v3 3/3] octeon_ep_vf: ensure dbell BADDR updation Date: Wed, 7 Jan 2026 13:18:56 +0000 Message-ID: <20260107131857.3434352-4-vimleshk@marvell.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260107131857.3434352-1-vimleshk@marvell.com> References: <20260107131857.3434352-1-vimleshk@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=PLgCOPqC c=1 sm=1 tr=0 ts=695e5d56 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=vUbySO9Y5rIA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=M5GUcnROAAAA:8 a=9s7rcsES4n5jIWhP9eIA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA3MDEwMiBTYWx0ZWRfX1RRc3EyiXZCj 4wyhtuPJ93ny+jfRKsMu+4gfqfOXLSIEoFVKWxUeLjFjcZ8+J52KdX0JrsImM8rKnuGJmHiQEbh zLPshSiPyzIUWidKM/AhzblbCGlToXxvy7dBygh/Bn2UzcwgPwzMMnNLnTBT+eodCR8Ms3ae7eQ GrCTrDju2a6sufiWrOJRBFE+xFOvnIIi9d3NcegoaWO/Snr3hLMBb51M2c5UdmQvK+4cz9hVD3X LHqYOCslbCt5/vRXljUbsVSxjztIjUV4xB/MMONDvI1dInkwz9W6M/yGEjqWE9YMchKuUqvrWnF XxA4+fXMIby45rMYvSFfYGMmAzge5SKGmvCGcO+/5VKD83OBD2OejTDeDnhOq/C28gktMAAT4Pf 0Dah08c9XVYrcgrgDj/xMIJr5H1liPY53RgVsj7Sw8L6SHbAQSc4NOoz8kql8npQ7uBaWNfqMAv oGRXhXss89hZMHchBow== X-Proofpoint-GUID: Mg6Uzxfj6zxL_9a35aaU4KMeI3aZbU6S X-Proofpoint-ORIG-GUID: Mg6Uzxfj6zxL_9a35aaU4KMeI3aZbU6S X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-07_01,2026-01-06_01,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Make sure the OUT DBELL base address reflects the latest values written to it. Fix: Add a wait until the OUT DBELL base address register is updated with the DMA ring descriptor address, and modify the setup_oq function to properly handle failures. Fixes: 2c0c32c72be29 ("octeon_ep_vf: add hardware configuration APIs") Signed-off-by: Sathesh Edara Signed-off-by: Shinas Rasheed Signed-off-by: Vimlesh Kumar --- V3: - Use reverse christmas tree order variable declaration. - Return error if timeout happens during setup oq. V2: https://lore.kernel.org/all/20251219100751.3063135-4-vimleshk@marvell.c= om/ V1: https://lore.kernel.org/all/20251212122304.2562229-4-vimleshk@marvell.c= om/ .../marvell/octeon_ep_vf/octep_vf_cn9k.c | 3 +- .../marvell/octeon_ep_vf/octep_vf_cnxk.c | 39 +++++++++++++++++-- .../marvell/octeon_ep_vf/octep_vf_main.h | 2 +- .../marvell/octeon_ep_vf/octep_vf_rx.c | 4 +- 4 files changed, 42 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c b/dr= ivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c index 88937fce75f1..4c769b27c278 100644 --- a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c +++ b/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c @@ -196,7 +196,7 @@ static void octep_vf_setup_iq_regs_cn93(struct octep_vf= _device *oct, int iq_no) } =20 /* Setup registers for a hardware Rx Queue */ -static void octep_vf_setup_oq_regs_cn93(struct octep_vf_device *oct, int o= q_no) +static int octep_vf_setup_oq_regs_cn93(struct octep_vf_device *oct, int oq= _no) { struct octep_vf_oq *oq =3D oct->oq[oq_no]; u32 time_threshold =3D 0; @@ -239,6 +239,7 @@ static void octep_vf_setup_oq_regs_cn93(struct octep_vf= _device *oct, int oq_no) time_threshold =3D CFG_GET_OQ_INTR_TIME(oct->conf); reg_val =3D ((u64)time_threshold << 32) | CFG_GET_OQ_INTR_PKT(oct->conf); octep_vf_write_csr64(oct, CN93_VF_SDP_R_OUT_INT_LEVELS(oq_no), reg_val); + return 0; } =20 /* Setup registers for a VF mailbox */ diff --git a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c b/dr= ivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c index 1f79dfad42c6..a968b93a6794 100644 --- a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c +++ b/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c @@ -199,11 +199,13 @@ static void octep_vf_setup_iq_regs_cnxk(struct octep_= vf_device *oct, int iq_no) } =20 /* Setup registers for a hardware Rx Queue */ -static void octep_vf_setup_oq_regs_cnxk(struct octep_vf_device *oct, int o= q_no) +static int octep_vf_setup_oq_regs_cnxk(struct octep_vf_device *oct, int oq= _no) { struct octep_vf_oq *oq =3D oct->oq[oq_no]; + unsigned long t_out_jiffies; u32 time_threshold =3D 0; u64 oq_ctl =3D ULL(0); + u64 reg_ba_val; u64 reg_val; =20 reg_val =3D octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no)); @@ -214,6 +216,38 @@ static void octep_vf_setup_oq_regs_cnxk(struct octep_v= f_device *oct, int oq_no) reg_val =3D octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no)); } while (!(reg_val & CNXK_VF_R_OUT_CTL_IDLE)); } + octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_WMARK(oq_no), + oq->max_count); + /* Wait for WMARK to get applied */ + usleep_range(10, 15); + + octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_BADDR(oq_no), + oq->desc_ring_dma); + octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_RSIZE(oq_no), + oq->max_count); + reg_ba_val =3D octep_vf_read_csr64(oct, + CNXK_VF_SDP_R_OUT_SLIST_BADDR(oq_no)); + if (reg_ba_val !=3D oq->desc_ring_dma) { + t_out_jiffies =3D jiffies + 10 * HZ; + do { + if (reg_ba_val =3D=3D ULLONG_MAX) + return -EFAULT; + octep_vf_write_csr64(oct, + CNXK_VF_SDP_R_OUT_SLIST_BADDR + (oq_no), oq->desc_ring_dma); + octep_vf_write_csr64(oct, + CNXK_VF_SDP_R_OUT_SLIST_RSIZE + (oq_no), oq->max_count); + reg_ba_val =3D + octep_vf_read_csr64(oct, + CNXK_VF_SDP_R_OUT_SLIST_BADDR + (oq_no)); + } while ((reg_ba_val !=3D oq->desc_ring_dma) && + time_before(jiffies, t_out_jiffies)); + + if (reg_ba_val !=3D oq->desc_ring_dma) + return -EAGAIN; + } =20 reg_val &=3D ~(CNXK_VF_R_OUT_CTL_IMODE); reg_val &=3D ~(CNXK_VF_R_OUT_CTL_ROR_P); @@ -227,8 +261,6 @@ static void octep_vf_setup_oq_regs_cnxk(struct octep_vf= _device *oct, int oq_no) reg_val |=3D (CNXK_VF_R_OUT_CTL_ES_P); =20 octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no), reg_val); - octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_BADDR(oq_no), oq->desc_= ring_dma); - octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_SLIST_RSIZE(oq_no), oq->max_c= ount); =20 oq_ctl =3D octep_vf_read_csr64(oct, CNXK_VF_SDP_R_OUT_CONTROL(oq_no)); /* Clear the ISIZE and BSIZE (22-0) */ @@ -250,6 +282,7 @@ static void octep_vf_setup_oq_regs_cnxk(struct octep_vf= _device *oct, int oq_no) reg_val &=3D ~GENMASK_ULL(31, 0); reg_val |=3D CFG_GET_OQ_WMARK(oct->conf); octep_vf_write_csr64(oct, CNXK_VF_SDP_R_OUT_WMARK(oq_no), reg_val); + return 0; } =20 /* Setup registers for a VF mailbox */ diff --git a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h b/dr= ivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h index b9f13506f462..c74cd2369e90 100644 --- a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h +++ b/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h @@ -55,7 +55,7 @@ struct octep_vf_mmio { =20 struct octep_vf_hw_ops { void (*setup_iq_regs)(struct octep_vf_device *oct, int q); - void (*setup_oq_regs)(struct octep_vf_device *oct, int q); + int (*setup_oq_regs)(struct octep_vf_device *oct, int q); void (*setup_mbox_regs)(struct octep_vf_device *oct, int mbox); =20 irqreturn_t (*non_ioq_intr_handler)(void *ioq_vector); diff --git a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_rx.c b/driv= ers/net/ethernet/marvell/octeon_ep_vf/octep_vf_rx.c index d70c8be3cfc4..6446f6bf0b90 100644 --- a/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_rx.c +++ b/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_rx.c @@ -171,7 +171,9 @@ static int octep_vf_setup_oq(struct octep_vf_device *oc= t, int q_no) goto oq_fill_buff_err; =20 octep_vf_oq_reset_indices(oq); - oct->hw_ops.setup_oq_regs(oct, q_no); + if (oct->hw_ops.setup_oq_regs(oct, q_no)) + goto oq_fill_buff_err; + oct->num_oqs++; =20 return 0; --=20 2.47.0