From nobody Sun Feb 8 23:03:52 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9594F26E165; Wed, 7 Jan 2026 06:03:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767765790; cv=none; b=C4djGo6ZZv0LN4PPTy19UPdJiWVVaHnOIXl0zakfycc8tNg7sqvtwLDkOk4rHIDndLClwsAYzinx4glAcHbXOXZNhla1/mJ6YoAccBIxibxM8KPWjjh2VKSH2x4IjeGe7Bi8Mkd1A0CcqHkykFi0gSJDnMfFboAOgVKuKYnbsp4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767765790; c=relaxed/simple; bh=MHePFF7lYadLcrrUHPZkpMVvmyN5YOUQoizHrLlIgJg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=g+cQ2FTo2Pp3tTynWEcVXC1PdcQ0Bslhx2hHJXb8akWrZknWkeK0AJKNjvkDFlLlWxVJHKHrAglguk4YHTd5OrxOf7bdBcp4FDKibzTL5/kjfMvQ0JZIpvJthoW+S38Cn3ewDHyEJQevwlUbNeBq53VGv44tr5xZjhTNcYWNHQg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=CfpsMU7x; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="CfpsMU7x" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1767765788; x=1799301788; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MHePFF7lYadLcrrUHPZkpMVvmyN5YOUQoizHrLlIgJg=; b=CfpsMU7xUgDfuLgUSJ4HaMBfVpP3Hfvt0p5ZUldgXi0DUuzV0/XbzQiV DLC/oFB+J74NhJD3vOPzouBy4heRcc8EB7ALr6FE1ONAaxxK+3BbXd0us dnMCwBQM3RzKes52CmXp6bjNCMG6Q+SJS3NNieCvYhhOXyjAQX5ulkUJH oC1w1zvT2uiNPEZ+GiB+RtI3Me5QOjbaOHLttWgncNvzP6tBNQUFUot3P s2Y+hWkCFbdcvNrwExYiZDd1qFRw8mcXrVHYreimX42oicMTeagYxsknF bZaWe7ZJhFVDdP2Jn27pt9EZLDD+GI9K4YMmlJDu5CVo6mIsvuGybjd7k w==; X-CSE-ConnectionGUID: JldrSdXXRsS5pX6svHBNCg== X-CSE-MsgGUID: /I+HSuwJSYextdR3ko5QYA== X-IronPort-AV: E=McAfee;i="6800,10657,11663"; a="79434352" X-IronPort-AV: E=Sophos;i="6.21,207,1763452800"; d="scan'208";a="79434352" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jan 2026 22:03:02 -0800 X-CSE-ConnectionGUID: a3jXbSUuRNWuFfryRpRLkg== X-CSE-MsgGUID: gD4s+bVQT1K3AGh1eD5X8w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,207,1763452800"; d="scan'208";a="202746877" Received: from spandruv-desk.jf.intel.com ([10.54.55.20]) by fmviesa006.fm.intel.com with ESMTP; 06 Jan 2026 22:03:02 -0800 From: Srinivas Pandruvada To: hansg@kernel.org, ilpo.jarvinen@linux.intel.com Cc: platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Pandruvada , stable@vger.kernel.org Subject: [PATCH v2 2/2] platform/x86: ISST: Store and restore all domains data Date: Tue, 6 Jan 2026 22:02:56 -0800 Message-ID: <20260107060256.1634188-3-srinivas.pandruvada@linux.intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260107060256.1634188-1-srinivas.pandruvada@linux.intel.com> References: <20260107060256.1634188-1-srinivas.pandruvada@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The suspend/resume callbacks currently only store and restore the configuration for power domain 0. However, other power domains may also have modified configurations that need to be preserved across suspend/ resume cycles. Extend the store/restore functionality to handle all power domains. Fixes: 91576acab020 ("platform/x86: ISST: Add suspend/resume callbacks") Signed-off-by: Srinivas Pandruvada CC: stable@vger.kernel.org --- v2: - Remove new line in tpmi_sst_dev_suspend() after cp_base assignment .../intel/speed_select_if/isst_tpmi_core.c | 54 +++++++++++-------- 1 file changed, 33 insertions(+), 21 deletions(-) diff --git a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c b/= drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c index f587709ddd47..13b11c3a2ec4 100644 --- a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c +++ b/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c @@ -1723,55 +1723,67 @@ EXPORT_SYMBOL_NS_GPL(tpmi_sst_dev_remove, "INTEL_TP= MI_SST"); void tpmi_sst_dev_suspend(struct auxiliary_device *auxdev) { struct tpmi_sst_struct *tpmi_sst =3D auxiliary_get_drvdata(auxdev); - struct tpmi_per_power_domain_info *power_domain_info; + struct tpmi_per_power_domain_info *power_domain_info, *pd_info; struct oobmsm_plat_info *plat_info; void __iomem *cp_base; + int num_resources, i; =20 plat_info =3D tpmi_get_platform_data(auxdev); if (!plat_info) return; =20 power_domain_info =3D tpmi_sst->power_domain_info[plat_info->partition]; + num_resources =3D tpmi_sst->number_of_power_domains[plat_info->partition]; =20 - cp_base =3D power_domain_info->sst_base + power_domain_info->sst_header.c= p_offset; - power_domain_info->saved_sst_cp_control =3D readq(cp_base + SST_CP_CONTRO= L_OFFSET); - - memcpy_fromio(power_domain_info->saved_clos_configs, cp_base + SST_CLOS_C= ONFIG_0_OFFSET, - sizeof(power_domain_info->saved_clos_configs)); + for (i =3D 0; i < num_resources; i++) { + pd_info =3D &power_domain_info[i]; + if (!pd_info || !pd_info->sst_base) + continue; =20 - memcpy_fromio(power_domain_info->saved_clos_assocs, cp_base + SST_CLOS_AS= SOC_0_OFFSET, - sizeof(power_domain_info->saved_clos_assocs)); + cp_base =3D pd_info->sst_base + pd_info->sst_header.cp_offset; + pd_info->saved_sst_cp_control =3D readq(cp_base + SST_CP_CONTROL_OFFSET); + memcpy_fromio(pd_info->saved_clos_configs, cp_base + SST_CLOS_CONFIG_0_O= FFSET, + sizeof(pd_info->saved_clos_configs)); + memcpy_fromio(pd_info->saved_clos_assocs, cp_base + SST_CLOS_ASSOC_0_OFF= SET, + sizeof(pd_info->saved_clos_assocs)); =20 - power_domain_info->saved_pp_control =3D readq(power_domain_info->sst_base= + - power_domain_info->sst_header.pp_offset + - SST_PP_CONTROL_OFFSET); + pd_info->saved_pp_control =3D readq(pd_info->sst_base + + pd_info->sst_header.pp_offset + + SST_PP_CONTROL_OFFSET); + } } EXPORT_SYMBOL_NS_GPL(tpmi_sst_dev_suspend, "INTEL_TPMI_SST"); =20 void tpmi_sst_dev_resume(struct auxiliary_device *auxdev) { struct tpmi_sst_struct *tpmi_sst =3D auxiliary_get_drvdata(auxdev); - struct tpmi_per_power_domain_info *power_domain_info; + struct tpmi_per_power_domain_info *power_domain_info, *pd_info; struct oobmsm_plat_info *plat_info; void __iomem *cp_base; + int num_resources, i; =20 plat_info =3D tpmi_get_platform_data(auxdev); if (!plat_info) return; =20 power_domain_info =3D tpmi_sst->power_domain_info[plat_info->partition]; + num_resources =3D tpmi_sst->number_of_power_domains[plat_info->partition]; =20 - cp_base =3D power_domain_info->sst_base + power_domain_info->sst_header.c= p_offset; - writeq(power_domain_info->saved_sst_cp_control, cp_base + SST_CP_CONTROL_= OFFSET); - - memcpy_toio(cp_base + SST_CLOS_CONFIG_0_OFFSET, power_domain_info->saved_= clos_configs, - sizeof(power_domain_info->saved_clos_configs)); + for (i =3D 0; i < num_resources; i++) { + pd_info =3D &power_domain_info[i]; + if (!pd_info || !pd_info->sst_base) + continue; =20 - memcpy_toio(cp_base + SST_CLOS_ASSOC_0_OFFSET, power_domain_info->saved_c= los_assocs, - sizeof(power_domain_info->saved_clos_assocs)); + cp_base =3D pd_info->sst_base + pd_info->sst_header.cp_offset; + writeq(pd_info->saved_sst_cp_control, cp_base + SST_CP_CONTROL_OFFSET); + memcpy_toio(cp_base + SST_CLOS_CONFIG_0_OFFSET, pd_info->saved_clos_conf= igs, + sizeof(pd_info->saved_clos_configs)); + memcpy_toio(cp_base + SST_CLOS_ASSOC_0_OFFSET, pd_info->saved_clos_assoc= s, + sizeof(pd_info->saved_clos_assocs)); =20 - writeq(power_domain_info->saved_pp_control, power_domain_info->sst_base + - power_domain_info->sst_header.pp_offset + SST_PP_CONTROL_OFFSET); + writeq(pd_info->saved_pp_control, power_domain_info->sst_base + + pd_info->sst_header.pp_offset + SST_PP_CONTROL_OFFSET); + } } EXPORT_SYMBOL_NS_GPL(tpmi_sst_dev_resume, "INTEL_TPMI_SST"); =20 --=20 2.52.0